+static uint32_t soc15_get_register_value(struct amdgpu_device *adev,
+ bool indexed, u32 se_num,
+ u32 sh_num, u32 reg_offset)
+{
+ if (indexed) {
+ return soc15_read_indexed_register(adev, se_num, sh_num, reg_offset);
+ } else {
+ switch (reg_offset) {
+ case SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG):
+ return adev->gfx.config.gb_addr_config;
+ default:
+ return RREG32(reg_offset);
+ }
+ }
+}
+