virt/kvm/ioapic.c

   1 /*
   2  *  Copyright (C) 2001  MandrakeSoft S.A.
   3  *
   4  *    MandrakeSoft S.A.
   5  *    43, rue d'Aboukir
   6  *    75002 Paris - France
   7  *    http://www.linux-mandrake.com/
   8  *    http://www.mandrakesoft.com/
   9  *
  10  *  This library is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU Lesser General Public
  12  *  License as published by the Free Software Foundation; either
  13  *  version 2 of the License, or (at your option) any later version.
  14  *
  15  *  This library is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  *  Lesser General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU Lesser General Public
  21  *  License along with this library; if not, write to the Free Software
  22  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  *
  24  *  Yunhong Jiang <yunhong.jiang@intel.com>
  25  *  Yaozu (Eddie) Dong <eddie.dong@intel.com>
  26  *  Based on Xen 3.1 code.
  27  */
  28
  29 #include <linux/kvm_host.h>
  30 #include <linux/kvm.h>
  31 #include <linux/mm.h>
  32 #include <linux/highmem.h>
  33 #include <linux/smp.h>
  34 #include <linux/hrtimer.h>
  35 #include <linux/io.h>
  36 #include <asm/processor.h>
  37 #include <asm/page.h>
  38 #include <asm/current.h>
  39
  40 #include "ioapic.h"
  41 #include "lapic.h"
  42 #include "irq.h"
  43
  44 #if 0
  45 #define ioapic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg)
  46 #else
  47 #define ioapic_debug(fmt, arg...)
  48 #endif
  49 static int ioapic_deliver(struct kvm_ioapic *vioapic, int irq);
  50
  51 static unsigned long ioapic_read_indirect(struct kvm_ioapic *ioapic,
  52                                           unsigned long addr,
  53                                           unsigned long length)
  54 {
  55         unsigned long result = 0;
  56
  57         switch (ioapic->ioregsel) {
  58         case IOAPIC_REG_VERSION:
  59                 result = ((((IOAPIC_NUM_PINS - 1) & 0xff) << 16)
  60                           | (IOAPIC_VERSION_ID & 0xff));
  61                 break;
  62
  63         case IOAPIC_REG_APIC_ID:
  64         case IOAPIC_REG_ARB_ID:
  65                 result = ((ioapic->id & 0xf) << 24);
  66                 break;
  67
  68         default:
  69                 {
  70                         u32 redir_index = (ioapic->ioregsel - 0x10) >> 1;
  71                         u64 redir_content;
  72
  73                         ASSERT(redir_index < IOAPIC_NUM_PINS);
  74
  75                         redir_content = ioapic->redirtbl[redir_index].bits;
  76                         result = (ioapic->ioregsel & 0x1) ?
  77                             (redir_content >> 32) & 0xffffffff :
  78                             redir_content & 0xffffffff;
  79                         break;
  80                 }
  81         }
  82
  83         return result;
  84 }
  85
  86 static int ioapic_service(struct kvm_ioapic *ioapic, unsigned int idx)
  87 {
  88         union kvm_ioapic_redirect_entry *pent;
  89         int injected = -1;
  90
  91         pent = &ioapic->redirtbl[idx];
  92
  93         if (!pent->fields.mask) {
  94                 injected = ioapic_deliver(ioapic, idx);
  95                 if (injected && pent->fields.trig_mode == IOAPIC_LEVEL_TRIG)
  96                         pent->fields.remote_irr = 1;
  97         }
  98
  99         return injected;
 100 }
 101
 102 static void ioapic_write_indirect(struct kvm_ioapic *ioapic, u32 val)
 103 {
 104         unsigned index;
 105         bool mask_before, mask_after;
 106
 107         switch (ioapic->ioregsel) {
 108         case IOAPIC_REG_VERSION:
 109                 /* Writes are ignored. */
 110                 break;
 111
 112         case IOAPIC_REG_APIC_ID:
 113                 ioapic->id = (val >> 24) & 0xf;
 114                 break;
 115
 116         case IOAPIC_REG_ARB_ID:
 117                 break;
 118
 119         default:
 120                 index = (ioapic->ioregsel - 0x10) >> 1;
 121
 122                 ioapic_debug("change redir index %x val %x\n", index, val);
 123                 if (index >= IOAPIC_NUM_PINS)
 124                         return;
 125                 mask_before = ioapic->redirtbl[index].fields.mask;
 126                 if (ioapic->ioregsel & 1) {
 127                         ioapic->redirtbl[index].bits &= 0xffffffff;
 128                         ioapic->redirtbl[index].bits |= (u64) val << 32;
 129                 } else {
 130                         ioapic->redirtbl[index].bits &= ~0xffffffffULL;
 131                         ioapic->redirtbl[index].bits |= (u32) val;
 132                         ioapic->redirtbl[index].fields.remote_irr = 0;
 133                 }
 134                 mask_after = ioapic->redirtbl[index].fields.mask;
 135                 if (mask_before != mask_after)
 136                         kvm_fire_mask_notifiers(ioapic->kvm, index, mask_after);
 137                 if (ioapic->redirtbl[index].fields.trig_mode == IOAPIC_LEVEL_TRIG
 138                     && ioapic->irr & (1 << index))
 139                         ioapic_service(ioapic, index);
 140                 break;
 141         }
 142 }
 143
 144 static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
 145 {
 146         union kvm_ioapic_redirect_entry *entry = &ioapic->redirtbl[irq];
 147         struct kvm_lapic_irq irqe;
 148
 149         ioapic_debug("dest=%x dest_mode=%x delivery_mode=%x "
 150                      "vector=%x trig_mode=%x\n",
 151                      entry->fields.dest, entry->fields.dest_mode,
 152                      entry->fields.delivery_mode, entry->fields.vector,
 153                      entry->fields.trig_mode);
 154
 155         irqe.dest_id = entry->fields.dest_id;
 156         irqe.vector = entry->fields.vector;
 157         irqe.dest_mode = entry->fields.dest_mode;
 158         irqe.trig_mode = entry->fields.trig_mode;
 159         irqe.delivery_mode = entry->fields.delivery_mode << 8;
 160         irqe.level = 1;
 161         irqe.shorthand = 0;
 162
 163 #ifdef CONFIG_X86
 164         /* Always delivery PIT interrupt to vcpu 0 */
 165         if (irq == 0) {
 166                 irqe.dest_mode = 0; /* Physical mode. */
 167                 /* need to read apic_id from apic regiest since
 168                  * it can be rewritten */
 169                 irqe.dest_id = ioapic->kvm->bsp_vcpu->vcpu_id;
 170         }
 171 #endif
 172         return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
 173 }
 174
 175 int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
 176 {
 177         u32 old_irr = ioapic->irr;
 178         u32 mask = 1 << irq;
 179         union kvm_ioapic_redirect_entry entry;
 180         int ret = 1;
 181
 182         if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
 183                 entry = ioapic->redirtbl[irq];
 184                 level ^= entry.fields.polarity;
 185                 if (!level)
 186                         ioapic->irr &= ~mask;
 187                 else {
 188                         int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
 189                         ioapic->irr |= mask;
 190                         if ((edge && old_irr != ioapic->irr) ||
 191                             (!edge && !entry.fields.remote_irr))
 192                                 ret = ioapic_service(ioapic, irq);
 193                 }
 194         }
 195         return ret;
 196 }
 197
 198 static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int pin,
 199                                     int trigger_mode)
 200 {
 201         union kvm_ioapic_redirect_entry *ent;
 202
 203         ent = &ioapic->redirtbl[pin];
 204
 205         kvm_notify_acked_irq(ioapic->kvm, KVM_IRQCHIP_IOAPIC, pin);
 206
 207         if (trigger_mode == IOAPIC_LEVEL_TRIG) {
 208                 ASSERT(ent->fields.trig_mode == IOAPIC_LEVEL_TRIG);
 209                 ent->fields.remote_irr = 0;
 210                 if (!ent->fields.mask && (ioapic->irr & (1 << pin)))
 211                         ioapic_service(ioapic, pin);
 212         }
 213 }
 214
 215 void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode)
 216 {
 217         struct kvm_ioapic *ioapic = kvm->arch.vioapic;
 218         int i;
 219
 220         for (i = 0; i < IOAPIC_NUM_PINS; i++)
 221                 if (ioapic->redirtbl[i].fields.vector == vector)
 222                         __kvm_ioapic_update_eoi(ioapic, i, trigger_mode);
 223 }
 224
 225 static inline struct kvm_ioapic *to_ioapic(struct kvm_io_device *dev)
 226 {
 227         return container_of(dev, struct kvm_ioapic, dev);
 228 }
 229
 230 static int ioapic_in_range(struct kvm_io_device *this, gpa_t addr,
 231                            int len, int is_write)
 232 {
 233         struct kvm_ioapic *ioapic = to_ioapic(this);
 234
 235         return ((addr >= ioapic->base_address &&
 236                  (addr < ioapic->base_address + IOAPIC_MEM_LENGTH)));
 237 }
 238
 239 static void ioapic_mmio_read(struct kvm_io_device *this, gpa_t addr, int len,
 240                              void *val)
 241 {
 242         struct kvm_ioapic *ioapic = to_ioapic(this);
 243         u32 result;
 244
 245         ioapic_debug("addr %lx\n", (unsigned long)addr);
 246         ASSERT(!(addr & 0xf));  /* check alignment */
 247
 248         mutex_lock(&ioapic->kvm->irq_lock);
 249         addr &= 0xff;
 250         switch (addr) {
 251         case IOAPIC_REG_SELECT:
 252                 result = ioapic->ioregsel;
 253                 break;
 254
 255         case IOAPIC_REG_WINDOW:
 256                 result = ioapic_read_indirect(ioapic, addr, len);
 257                 break;
 258
 259         default:
 260                 result = 0;
 261                 break;
 262         }
 263         switch (len) {
 264         case 8:
 265                 *(u64 *) val = result;
 266                 break;
 267         case 1:
 268         case 2:
 269         case 4:
 270                 memcpy(val, (char *)&result, len);
 271                 break;
 272         default:
 273                 printk(KERN_WARNING "ioapic: wrong length %d\n", len);
 274         }
 275         mutex_unlock(&ioapic->kvm->irq_lock);
 276 }
 277
 278 static void ioapic_mmio_write(struct kvm_io_device *this, gpa_t addr, int len,
 279                               const void *val)
 280 {
 281         struct kvm_ioapic *ioapic = to_ioapic(this);
 282         u32 data;
 283
 284         ioapic_debug("ioapic_mmio_write addr=%p len=%d val=%p\n",
 285                      (void*)addr, len, val);
 286         ASSERT(!(addr & 0xf));  /* check alignment */
 287
 288         mutex_lock(&ioapic->kvm->irq_lock);
 289         if (len == 4 || len == 8)
 290                 data = *(u32 *) val;
 291         else {
 292                 printk(KERN_WARNING "ioapic: Unsupported size %d\n", len);
 293                 return;
 294         }
 295
 296         addr &= 0xff;
 297         switch (addr) {
 298         case IOAPIC_REG_SELECT:
 299                 ioapic->ioregsel = data;
 300                 break;
 301
 302         case IOAPIC_REG_WINDOW:
 303                 ioapic_write_indirect(ioapic, data);
 304                 break;
 305 #ifdef  CONFIG_IA64
 306         case IOAPIC_REG_EOI:
 307                 kvm_ioapic_update_eoi(ioapic->kvm, data, IOAPIC_LEVEL_TRIG);
 308                 break;
 309 #endif
 310
 311         default:
 312                 break;
 313         }
 314         mutex_unlock(&ioapic->kvm->irq_lock);
 315 }
 316
 317 void kvm_ioapic_reset(struct kvm_ioapic *ioapic)
 318 {
 319         int i;
 320
 321         for (i = 0; i < IOAPIC_NUM_PINS; i++)
 322                 ioapic->redirtbl[i].fields.mask = 1;
 323         ioapic->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 324         ioapic->ioregsel = 0;
 325         ioapic->irr = 0;
 326         ioapic->id = 0;
 327 }
 328
 329 static const struct kvm_io_device_ops ioapic_mmio_ops = {
 330         .read     = ioapic_mmio_read,
 331         .write    = ioapic_mmio_write,
 332         .in_range = ioapic_in_range,
 333 };
 334
 335 int kvm_ioapic_init(struct kvm *kvm)
 336 {
 337         struct kvm_ioapic *ioapic;
 338
 339         ioapic = kzalloc(sizeof(struct kvm_ioapic), GFP_KERNEL);
 340         if (!ioapic)
 341                 return -ENOMEM;
 342         kvm->arch.vioapic = ioapic;
 343         kvm_ioapic_reset(ioapic);
 344         kvm_iodevice_init(&ioapic->dev, &ioapic_mmio_ops);
 345         ioapic->kvm = kvm;
 346         kvm_io_bus_register_dev(&kvm->mmio_bus, &ioapic->dev);
 347         return 0;
 348 }
 349