2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/cpu.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_host.h>
22 #include <linux/interrupt.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/uaccess.h>
29 #include <linux/irqchip/arm-gic.h>
31 #include <asm/kvm_emulate.h>
32 #include <asm/kvm_arm.h>
33 #include <asm/kvm_mmu.h>
36 * How the whole thing works (courtesy of Christoffer Dall):
38 * - At any time, the dist->irq_pending_on_cpu is the oracle that knows if
39 * something is pending on the CPU interface.
40 * - Interrupts that are pending on the distributor are stored on the
41 * vgic.irq_pending vgic bitmap (this bitmap is updated by both user land
42 * ioctls and guest mmio ops, and other in-kernel peripherals such as the
44 * - Every time the bitmap changes, the irq_pending_on_cpu oracle is
46 * - To calculate the oracle, we need info for each cpu from
47 * compute_pending_for_cpu, which considers:
48 * - PPI: dist->irq_pending & dist->irq_enable
49 * - SPI: dist->irq_pending & dist->irq_enable & dist->irq_spi_target
50 * - irq_spi_target is a 'formatted' version of the GICD_ITARGETSRn
51 * registers, stored on each vcpu. We only keep one bit of
52 * information per interrupt, making sure that only one vcpu can
53 * accept the interrupt.
54 * - If any of the above state changes, we must recalculate the oracle.
55 * - The same is true when injecting an interrupt, except that we only
56 * consider a single interrupt at a time. The irq_spi_cpu array
57 * contains the target CPU for each SPI.
59 * The handling of level interrupts adds some extra complexity. We
60 * need to track when the interrupt has been EOIed, so we can sample
61 * the 'line' again. This is achieved as such:
63 * - When a level interrupt is moved onto a vcpu, the corresponding
64 * bit in irq_queued is set. As long as this bit is set, the line
65 * will be ignored for further interrupts. The interrupt is injected
66 * into the vcpu with the GICH_LR_EOI bit set (generate a
67 * maintenance interrupt on EOI).
68 * - When the interrupt is EOIed, the maintenance interrupt fires,
69 * and clears the corresponding bit in irq_queued. This allows the
70 * interrupt line to be sampled again.
71 * - Note that level-triggered interrupts can also be set to pending from
72 * writes to GICD_ISPENDRn and lowering the external input line does not
73 * cause the interrupt to become inactive in such a situation.
74 * Conversely, writes to GICD_ICPENDRn do not cause the interrupt to become
75 * inactive as long as the external input line is held high.
78 #define VGIC_ADDR_UNDEF (-1)
79 #define IS_VGIC_ADDR_UNDEF(_x) ((_x) == VGIC_ADDR_UNDEF)
81 #define PRODUCT_ID_KVM 0x4b /* ASCII code K */
82 #define IMPLEMENTER_ARM 0x43b
83 #define GICC_ARCH_VERSION_V2 0x2
85 #define ACCESS_READ_VALUE (1 << 0)
86 #define ACCESS_READ_RAZ (0 << 0)
87 #define ACCESS_READ_MASK(x) ((x) & (1 << 0))
88 #define ACCESS_WRITE_IGNORED (0 << 1)
89 #define ACCESS_WRITE_SETBIT (1 << 1)
90 #define ACCESS_WRITE_CLEARBIT (2 << 1)
91 #define ACCESS_WRITE_VALUE (3 << 1)
92 #define ACCESS_WRITE_MASK(x) ((x) & (3 << 1))
94 static int vgic_init(struct kvm *kvm);
95 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu);
96 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu);
97 static void vgic_update_state(struct kvm *kvm);
98 static void vgic_kick_vcpus(struct kvm *kvm);
99 static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi);
100 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg);
101 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr);
102 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr, struct vgic_lr lr_desc);
103 static void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
104 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
106 static const struct vgic_ops *vgic_ops;
107 static const struct vgic_params *vgic;
110 * struct vgic_bitmap contains a bitmap made of unsigned longs, but
111 * extracts u32s out of them.
113 * This does not work on 64-bit BE systems, because the bitmap access
114 * will store two consecutive 32-bit words with the higher-addressed
115 * register's bits at the lower index and the lower-addressed register's
116 * bits at the higher index.
118 * Therefore, swizzle the register index when accessing the 32-bit word
119 * registers to access the right register's value.
121 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 64
122 #define REG_OFFSET_SWIZZLE 1
124 #define REG_OFFSET_SWIZZLE 0
127 static int vgic_init_bitmap(struct vgic_bitmap *b, int nr_cpus, int nr_irqs)
131 nr_longs = nr_cpus + BITS_TO_LONGS(nr_irqs - VGIC_NR_PRIVATE_IRQS);
133 b->private = kzalloc(sizeof(unsigned long) * nr_longs, GFP_KERNEL);
137 b->shared = b->private + nr_cpus;
142 static void vgic_free_bitmap(struct vgic_bitmap *b)
150 * Call this function to convert a u64 value to an unsigned long * bitmask
151 * in a way that works on both 32-bit and 64-bit LE and BE platforms.
153 * Warning: Calling this function may modify *val.
155 static unsigned long *u64_to_bitmask(u64 *val)
157 #if defined(CONFIG_CPU_BIG_ENDIAN) && BITS_PER_LONG == 32
158 *val = (*val >> 32) | (*val << 32);
160 return (unsigned long *)val;
163 static u32 *vgic_bitmap_get_reg(struct vgic_bitmap *x,
164 int cpuid, u32 offset)
168 return (u32 *)(x->private + cpuid) + REG_OFFSET_SWIZZLE;
170 return (u32 *)(x->shared) + ((offset - 1) ^ REG_OFFSET_SWIZZLE);
173 static int vgic_bitmap_get_irq_val(struct vgic_bitmap *x,
176 if (irq < VGIC_NR_PRIVATE_IRQS)
177 return test_bit(irq, x->private + cpuid);
179 return test_bit(irq - VGIC_NR_PRIVATE_IRQS, x->shared);
182 static void vgic_bitmap_set_irq_val(struct vgic_bitmap *x, int cpuid,
187 if (irq < VGIC_NR_PRIVATE_IRQS) {
188 reg = x->private + cpuid;
191 irq -= VGIC_NR_PRIVATE_IRQS;
200 static unsigned long *vgic_bitmap_get_cpu_map(struct vgic_bitmap *x, int cpuid)
202 return x->private + cpuid;
205 static unsigned long *vgic_bitmap_get_shared_map(struct vgic_bitmap *x)
210 static int vgic_init_bytemap(struct vgic_bytemap *x, int nr_cpus, int nr_irqs)
214 size = nr_cpus * VGIC_NR_PRIVATE_IRQS;
215 size += nr_irqs - VGIC_NR_PRIVATE_IRQS;
217 x->private = kzalloc(size, GFP_KERNEL);
221 x->shared = x->private + nr_cpus * VGIC_NR_PRIVATE_IRQS / sizeof(u32);
225 static void vgic_free_bytemap(struct vgic_bytemap *b)
232 static u32 *vgic_bytemap_get_reg(struct vgic_bytemap *x, int cpuid, u32 offset)
236 if (offset < VGIC_NR_PRIVATE_IRQS) {
238 offset += cpuid * VGIC_NR_PRIVATE_IRQS;
241 offset -= VGIC_NR_PRIVATE_IRQS;
244 return reg + (offset / sizeof(u32));
247 #define VGIC_CFG_LEVEL 0
248 #define VGIC_CFG_EDGE 1
250 static bool vgic_irq_is_edge(struct kvm_vcpu *vcpu, int irq)
252 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
255 irq_val = vgic_bitmap_get_irq_val(&dist->irq_cfg, vcpu->vcpu_id, irq);
256 return irq_val == VGIC_CFG_EDGE;
259 static int vgic_irq_is_enabled(struct kvm_vcpu *vcpu, int irq)
261 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
263 return vgic_bitmap_get_irq_val(&dist->irq_enabled, vcpu->vcpu_id, irq);
266 static int vgic_irq_is_queued(struct kvm_vcpu *vcpu, int irq)
268 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
270 return vgic_bitmap_get_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq);
273 static void vgic_irq_set_queued(struct kvm_vcpu *vcpu, int irq)
275 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
277 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 1);
280 static void vgic_irq_clear_queued(struct kvm_vcpu *vcpu, int irq)
282 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
284 vgic_bitmap_set_irq_val(&dist->irq_queued, vcpu->vcpu_id, irq, 0);
287 static int vgic_dist_irq_get_level(struct kvm_vcpu *vcpu, int irq)
289 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
291 return vgic_bitmap_get_irq_val(&dist->irq_level, vcpu->vcpu_id, irq);
294 static void vgic_dist_irq_set_level(struct kvm_vcpu *vcpu, int irq)
296 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
298 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 1);
301 static void vgic_dist_irq_clear_level(struct kvm_vcpu *vcpu, int irq)
303 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
305 vgic_bitmap_set_irq_val(&dist->irq_level, vcpu->vcpu_id, irq, 0);
308 static int vgic_dist_irq_soft_pend(struct kvm_vcpu *vcpu, int irq)
310 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
312 return vgic_bitmap_get_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq);
315 static void vgic_dist_irq_clear_soft_pend(struct kvm_vcpu *vcpu, int irq)
317 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
319 vgic_bitmap_set_irq_val(&dist->irq_soft_pend, vcpu->vcpu_id, irq, 0);
322 static int vgic_dist_irq_is_pending(struct kvm_vcpu *vcpu, int irq)
324 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
326 return vgic_bitmap_get_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq);
329 static void vgic_dist_irq_set_pending(struct kvm_vcpu *vcpu, int irq)
331 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
333 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 1);
336 static void vgic_dist_irq_clear_pending(struct kvm_vcpu *vcpu, int irq)
338 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
340 vgic_bitmap_set_irq_val(&dist->irq_pending, vcpu->vcpu_id, irq, 0);
343 static void vgic_cpu_irq_set(struct kvm_vcpu *vcpu, int irq)
345 if (irq < VGIC_NR_PRIVATE_IRQS)
346 set_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
348 set_bit(irq - VGIC_NR_PRIVATE_IRQS,
349 vcpu->arch.vgic_cpu.pending_shared);
352 static void vgic_cpu_irq_clear(struct kvm_vcpu *vcpu, int irq)
354 if (irq < VGIC_NR_PRIVATE_IRQS)
355 clear_bit(irq, vcpu->arch.vgic_cpu.pending_percpu);
357 clear_bit(irq - VGIC_NR_PRIVATE_IRQS,
358 vcpu->arch.vgic_cpu.pending_shared);
361 static bool vgic_can_sample_irq(struct kvm_vcpu *vcpu, int irq)
363 return vgic_irq_is_edge(vcpu, irq) || !vgic_irq_is_queued(vcpu, irq);
366 static u32 mmio_data_read(struct kvm_exit_mmio *mmio, u32 mask)
368 return le32_to_cpu(*((u32 *)mmio->data)) & mask;
371 static void mmio_data_write(struct kvm_exit_mmio *mmio, u32 mask, u32 value)
373 *((u32 *)mmio->data) = cpu_to_le32(value) & mask;
377 * vgic_reg_access - access vgic register
378 * @mmio: pointer to the data describing the mmio access
379 * @reg: pointer to the virtual backing of vgic distributor data
380 * @offset: least significant 2 bits used for word offset
381 * @mode: ACCESS_ mode (see defines above)
383 * Helper to make vgic register access easier using one of the access
384 * modes defined for vgic register access
385 * (read,raz,write-ignored,setbit,clearbit,write)
387 static void vgic_reg_access(struct kvm_exit_mmio *mmio, u32 *reg,
388 phys_addr_t offset, int mode)
390 int word_offset = (offset & 3) * 8;
391 u32 mask = (1UL << (mmio->len * 8)) - 1;
395 * Any alignment fault should have been delivered to the guest
396 * directly (ARM ARM B3.12.7 "Prioritization of aborts").
402 BUG_ON(mode != (ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED));
406 if (mmio->is_write) {
407 u32 data = mmio_data_read(mmio, mask) << word_offset;
408 switch (ACCESS_WRITE_MASK(mode)) {
409 case ACCESS_WRITE_IGNORED:
412 case ACCESS_WRITE_SETBIT:
416 case ACCESS_WRITE_CLEARBIT:
420 case ACCESS_WRITE_VALUE:
421 regval = (regval & ~(mask << word_offset)) | data;
426 switch (ACCESS_READ_MASK(mode)) {
427 case ACCESS_READ_RAZ:
431 case ACCESS_READ_VALUE:
432 mmio_data_write(mmio, mask, regval >> word_offset);
437 static bool handle_mmio_misc(struct kvm_vcpu *vcpu,
438 struct kvm_exit_mmio *mmio, phys_addr_t offset)
441 u32 word_offset = offset & 3;
443 switch (offset & ~3) {
444 case 0: /* GICD_CTLR */
445 reg = vcpu->kvm->arch.vgic.enabled;
446 vgic_reg_access(mmio, ®, word_offset,
447 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
448 if (mmio->is_write) {
449 vcpu->kvm->arch.vgic.enabled = reg & 1;
450 vgic_update_state(vcpu->kvm);
455 case 4: /* GICD_TYPER */
456 reg = (atomic_read(&vcpu->kvm->online_vcpus) - 1) << 5;
457 reg |= (vcpu->kvm->arch.vgic.nr_irqs >> 5) - 1;
458 vgic_reg_access(mmio, ®, word_offset,
459 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
462 case 8: /* GICD_IIDR */
463 reg = (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
464 vgic_reg_access(mmio, ®, word_offset,
465 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
472 static bool handle_mmio_raz_wi(struct kvm_vcpu *vcpu,
473 struct kvm_exit_mmio *mmio, phys_addr_t offset)
475 vgic_reg_access(mmio, NULL, offset,
476 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
480 static bool handle_mmio_set_enable_reg(struct kvm_vcpu *vcpu,
481 struct kvm_exit_mmio *mmio,
484 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
485 vcpu->vcpu_id, offset);
486 vgic_reg_access(mmio, reg, offset,
487 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
488 if (mmio->is_write) {
489 vgic_update_state(vcpu->kvm);
496 static bool handle_mmio_clear_enable_reg(struct kvm_vcpu *vcpu,
497 struct kvm_exit_mmio *mmio,
500 u32 *reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_enabled,
501 vcpu->vcpu_id, offset);
502 vgic_reg_access(mmio, reg, offset,
503 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
504 if (mmio->is_write) {
505 if (offset < 4) /* Force SGI enabled */
507 vgic_retire_disabled_irqs(vcpu);
508 vgic_update_state(vcpu->kvm);
515 static bool handle_mmio_set_pending_reg(struct kvm_vcpu *vcpu,
516 struct kvm_exit_mmio *mmio,
521 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
523 reg = vgic_bitmap_get_reg(&dist->irq_cfg, vcpu->vcpu_id, offset);
524 level_mask = (~(*reg));
526 /* Mark both level and edge triggered irqs as pending */
527 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
529 vgic_reg_access(mmio, reg, offset,
530 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
532 if (mmio->is_write) {
533 /* Set the soft-pending flag only for level-triggered irqs */
534 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
535 vcpu->vcpu_id, offset);
536 vgic_reg_access(mmio, reg, offset,
537 ACCESS_READ_VALUE | ACCESS_WRITE_SETBIT);
540 /* Ignore writes to SGIs */
543 *reg |= orig & 0xffff;
546 vgic_update_state(vcpu->kvm);
553 static bool handle_mmio_clear_pending_reg(struct kvm_vcpu *vcpu,
554 struct kvm_exit_mmio *mmio,
559 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
561 reg = vgic_bitmap_get_reg(&dist->irq_pending, vcpu->vcpu_id, offset);
563 vgic_reg_access(mmio, reg, offset,
564 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
565 if (mmio->is_write) {
566 /* Re-set level triggered level-active interrupts */
567 level_active = vgic_bitmap_get_reg(&dist->irq_level,
568 vcpu->vcpu_id, offset);
569 reg = vgic_bitmap_get_reg(&dist->irq_pending,
570 vcpu->vcpu_id, offset);
571 *reg |= *level_active;
573 /* Ignore writes to SGIs */
576 *reg |= orig & 0xffff;
579 /* Clear soft-pending flags */
580 reg = vgic_bitmap_get_reg(&dist->irq_soft_pend,
581 vcpu->vcpu_id, offset);
582 vgic_reg_access(mmio, reg, offset,
583 ACCESS_READ_VALUE | ACCESS_WRITE_CLEARBIT);
585 vgic_update_state(vcpu->kvm);
592 static bool handle_mmio_priority_reg(struct kvm_vcpu *vcpu,
593 struct kvm_exit_mmio *mmio,
596 u32 *reg = vgic_bytemap_get_reg(&vcpu->kvm->arch.vgic.irq_priority,
597 vcpu->vcpu_id, offset);
598 vgic_reg_access(mmio, reg, offset,
599 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
603 #define GICD_ITARGETSR_SIZE 32
604 #define GICD_CPUTARGETS_BITS 8
605 #define GICD_IRQS_PER_ITARGETSR (GICD_ITARGETSR_SIZE / GICD_CPUTARGETS_BITS)
606 static u32 vgic_get_target_reg(struct kvm *kvm, int irq)
608 struct vgic_dist *dist = &kvm->arch.vgic;
612 irq -= VGIC_NR_PRIVATE_IRQS;
614 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++)
615 val |= 1 << (dist->irq_spi_cpu[irq + i] + i * 8);
620 static void vgic_set_target_reg(struct kvm *kvm, u32 val, int irq)
622 struct vgic_dist *dist = &kvm->arch.vgic;
623 struct kvm_vcpu *vcpu;
628 irq -= VGIC_NR_PRIVATE_IRQS;
631 * Pick the LSB in each byte. This ensures we target exactly
632 * one vcpu per IRQ. If the byte is null, assume we target
635 for (i = 0; i < GICD_IRQS_PER_ITARGETSR; i++) {
636 int shift = i * GICD_CPUTARGETS_BITS;
637 target = ffs((val >> shift) & 0xffU);
638 target = target ? (target - 1) : 0;
639 dist->irq_spi_cpu[irq + i] = target;
640 kvm_for_each_vcpu(c, vcpu, kvm) {
641 bmap = vgic_bitmap_get_shared_map(&dist->irq_spi_target[c]);
643 set_bit(irq + i, bmap);
645 clear_bit(irq + i, bmap);
650 static bool handle_mmio_target_reg(struct kvm_vcpu *vcpu,
651 struct kvm_exit_mmio *mmio,
656 /* We treat the banked interrupts targets as read-only */
658 u32 roreg = 1 << vcpu->vcpu_id;
660 roreg |= roreg << 16;
662 vgic_reg_access(mmio, &roreg, offset,
663 ACCESS_READ_VALUE | ACCESS_WRITE_IGNORED);
667 reg = vgic_get_target_reg(vcpu->kvm, offset & ~3U);
668 vgic_reg_access(mmio, ®, offset,
669 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
670 if (mmio->is_write) {
671 vgic_set_target_reg(vcpu->kvm, reg, offset & ~3U);
672 vgic_update_state(vcpu->kvm);
679 static u32 vgic_cfg_expand(u16 val)
685 * Turn a 16bit value like abcd...mnop into a 32bit word
686 * a0b0c0d0...m0n0o0p0, which is what the HW cfg register is.
688 for (i = 0; i < 16; i++)
689 res |= ((val >> i) & VGIC_CFG_EDGE) << (2 * i + 1);
694 static u16 vgic_cfg_compress(u32 val)
700 * Turn a 32bit word a0b0c0d0...m0n0o0p0 into 16bit value like
701 * abcd...mnop which is what we really care about.
703 for (i = 0; i < 16; i++)
704 res |= ((val >> (i * 2 + 1)) & VGIC_CFG_EDGE) << i;
710 * The distributor uses 2 bits per IRQ for the CFG register, but the
711 * LSB is always 0. As such, we only keep the upper bit, and use the
712 * two above functions to compress/expand the bits
714 static bool handle_mmio_cfg_reg(struct kvm_vcpu *vcpu,
715 struct kvm_exit_mmio *mmio, phys_addr_t offset)
720 reg = vgic_bitmap_get_reg(&vcpu->kvm->arch.vgic.irq_cfg,
721 vcpu->vcpu_id, offset >> 1);
728 val = vgic_cfg_expand(val);
729 vgic_reg_access(mmio, &val, offset,
730 ACCESS_READ_VALUE | ACCESS_WRITE_VALUE);
731 if (mmio->is_write) {
733 *reg = ~0U; /* Force PPIs/SGIs to 1 */
737 val = vgic_cfg_compress(val);
742 *reg &= 0xffff << 16;
750 static bool handle_mmio_sgi_reg(struct kvm_vcpu *vcpu,
751 struct kvm_exit_mmio *mmio, phys_addr_t offset)
754 vgic_reg_access(mmio, ®, offset,
755 ACCESS_READ_RAZ | ACCESS_WRITE_VALUE);
756 if (mmio->is_write) {
757 vgic_dispatch_sgi(vcpu, reg);
758 vgic_update_state(vcpu->kvm);
766 * vgic_unqueue_irqs - move pending IRQs from LRs to the distributor
767 * @vgic_cpu: Pointer to the vgic_cpu struct holding the LRs
769 * Move any pending IRQs that have already been assigned to LRs back to the
770 * emulated distributor state so that the complete emulated state can be read
771 * from the main emulation structures without investigating the LRs.
773 * Note that IRQs in the active state in the LRs get their pending state moved
774 * to the distributor but the active state stays in the LRs, because we don't
775 * track the active state on the distributor side.
777 static void vgic_unqueue_irqs(struct kvm_vcpu *vcpu)
779 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
780 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
781 int vcpu_id = vcpu->vcpu_id;
784 for_each_set_bit(i, vgic_cpu->lr_used, vgic_cpu->nr_lr) {
785 struct vgic_lr lr = vgic_get_lr(vcpu, i);
788 * There are three options for the state bits:
792 * 11: pending and active
794 * If the LR holds only an active interrupt (not pending) then
795 * just leave it alone.
797 if ((lr.state & LR_STATE_MASK) == LR_STATE_ACTIVE)
801 * Reestablish the pending state on the distributor and the
802 * CPU interface. It may have already been pending, but that
803 * is fine, then we are only setting a few bits that were
806 vgic_dist_irq_set_pending(vcpu, lr.irq);
807 if (lr.irq < VGIC_NR_SGIS)
808 *vgic_get_sgi_sources(dist, vcpu_id, lr.irq) |= 1 << lr.source;
809 lr.state &= ~LR_STATE_PENDING;
810 vgic_set_lr(vcpu, i, lr);
813 * If there's no state left on the LR (it could still be
814 * active), then the LR does not hold any useful info and can
815 * be marked as free for other use.
817 if (!(lr.state & LR_STATE_MASK)) {
818 vgic_retire_lr(i, lr.irq, vcpu);
819 vgic_irq_clear_queued(vcpu, lr.irq);
822 /* Finally update the VGIC state. */
823 vgic_update_state(vcpu->kvm);
827 /* Handle reads of GICD_CPENDSGIRn and GICD_SPENDSGIRn */
828 static bool read_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
829 struct kvm_exit_mmio *mmio,
832 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
834 int min_sgi = (offset & ~0x3);
835 int max_sgi = min_sgi + 3;
836 int vcpu_id = vcpu->vcpu_id;
839 /* Copy source SGIs from distributor side */
840 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
841 int shift = 8 * (sgi - min_sgi);
842 reg |= ((u32)*vgic_get_sgi_sources(dist, vcpu_id, sgi)) << shift;
845 mmio_data_write(mmio, ~0, reg);
849 static bool write_set_clear_sgi_pend_reg(struct kvm_vcpu *vcpu,
850 struct kvm_exit_mmio *mmio,
851 phys_addr_t offset, bool set)
853 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
855 int min_sgi = (offset & ~0x3);
856 int max_sgi = min_sgi + 3;
857 int vcpu_id = vcpu->vcpu_id;
859 bool updated = false;
861 reg = mmio_data_read(mmio, ~0);
863 /* Clear pending SGIs on the distributor */
864 for (sgi = min_sgi; sgi <= max_sgi; sgi++) {
865 u8 mask = reg >> (8 * (sgi - min_sgi));
866 u8 *src = vgic_get_sgi_sources(dist, vcpu_id, sgi);
868 if ((*src & mask) != mask)
879 vgic_update_state(vcpu->kvm);
884 static bool handle_mmio_sgi_set(struct kvm_vcpu *vcpu,
885 struct kvm_exit_mmio *mmio,
889 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
891 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, true);
894 static bool handle_mmio_sgi_clear(struct kvm_vcpu *vcpu,
895 struct kvm_exit_mmio *mmio,
899 return read_set_clear_sgi_pend_reg(vcpu, mmio, offset);
901 return write_set_clear_sgi_pend_reg(vcpu, mmio, offset, false);
905 * I would have liked to use the kvm_bus_io_*() API instead, but it
906 * cannot cope with banked registers (only the VM pointer is passed
907 * around, and we need the vcpu). One of these days, someone please
914 bool (*handle_mmio)(struct kvm_vcpu *vcpu, struct kvm_exit_mmio *mmio,
918 static const struct mmio_range vgic_dist_ranges[] = {
920 .base = GIC_DIST_CTRL,
923 .handle_mmio = handle_mmio_misc,
926 .base = GIC_DIST_IGROUP,
927 .len = VGIC_MAX_IRQS / 8,
929 .handle_mmio = handle_mmio_raz_wi,
932 .base = GIC_DIST_ENABLE_SET,
933 .len = VGIC_MAX_IRQS / 8,
935 .handle_mmio = handle_mmio_set_enable_reg,
938 .base = GIC_DIST_ENABLE_CLEAR,
939 .len = VGIC_MAX_IRQS / 8,
941 .handle_mmio = handle_mmio_clear_enable_reg,
944 .base = GIC_DIST_PENDING_SET,
945 .len = VGIC_MAX_IRQS / 8,
947 .handle_mmio = handle_mmio_set_pending_reg,
950 .base = GIC_DIST_PENDING_CLEAR,
951 .len = VGIC_MAX_IRQS / 8,
953 .handle_mmio = handle_mmio_clear_pending_reg,
956 .base = GIC_DIST_ACTIVE_SET,
957 .len = VGIC_MAX_IRQS / 8,
959 .handle_mmio = handle_mmio_raz_wi,
962 .base = GIC_DIST_ACTIVE_CLEAR,
963 .len = VGIC_MAX_IRQS / 8,
965 .handle_mmio = handle_mmio_raz_wi,
968 .base = GIC_DIST_PRI,
969 .len = VGIC_MAX_IRQS,
971 .handle_mmio = handle_mmio_priority_reg,
974 .base = GIC_DIST_TARGET,
975 .len = VGIC_MAX_IRQS,
977 .handle_mmio = handle_mmio_target_reg,
980 .base = GIC_DIST_CONFIG,
981 .len = VGIC_MAX_IRQS / 4,
983 .handle_mmio = handle_mmio_cfg_reg,
986 .base = GIC_DIST_SOFTINT,
988 .handle_mmio = handle_mmio_sgi_reg,
991 .base = GIC_DIST_SGI_PENDING_CLEAR,
993 .handle_mmio = handle_mmio_sgi_clear,
996 .base = GIC_DIST_SGI_PENDING_SET,
998 .handle_mmio = handle_mmio_sgi_set,
1004 struct mmio_range *find_matching_range(const struct mmio_range *ranges,
1005 struct kvm_exit_mmio *mmio,
1008 const struct mmio_range *r = ranges;
1011 if (offset >= r->base &&
1012 (offset + mmio->len) <= (r->base + r->len))
1020 static bool vgic_validate_access(const struct vgic_dist *dist,
1021 const struct mmio_range *range,
1022 unsigned long offset)
1026 if (!range->bits_per_irq)
1027 return true; /* Not an irq-based access */
1029 irq = offset * 8 / range->bits_per_irq;
1030 if (irq >= dist->nr_irqs)
1037 * vgic_handle_mmio - handle an in-kernel MMIO access
1038 * @vcpu: pointer to the vcpu performing the access
1039 * @run: pointer to the kvm_run structure
1040 * @mmio: pointer to the data describing the access
1042 * returns true if the MMIO access has been performed in kernel space,
1043 * and false if it needs to be emulated in user space.
1045 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
1046 struct kvm_exit_mmio *mmio)
1048 const struct mmio_range *range;
1049 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1050 unsigned long base = dist->vgic_dist_base;
1052 unsigned long offset;
1054 if (!irqchip_in_kernel(vcpu->kvm) ||
1055 mmio->phys_addr < base ||
1056 (mmio->phys_addr + mmio->len) > (base + KVM_VGIC_V2_DIST_SIZE))
1059 /* We don't support ldrd / strd or ldm / stm to the emulated vgic */
1060 if (mmio->len > 4) {
1061 kvm_inject_dabt(vcpu, mmio->phys_addr);
1065 offset = mmio->phys_addr - base;
1066 range = find_matching_range(vgic_dist_ranges, mmio, offset);
1067 if (unlikely(!range || !range->handle_mmio)) {
1068 pr_warn("Unhandled access %d %08llx %d\n",
1069 mmio->is_write, mmio->phys_addr, mmio->len);
1073 spin_lock(&vcpu->kvm->arch.vgic.lock);
1074 offset = mmio->phys_addr - range->base - base;
1075 if (vgic_validate_access(dist, range, offset)) {
1076 updated_state = range->handle_mmio(vcpu, mmio, offset);
1078 vgic_reg_access(mmio, NULL, offset,
1079 ACCESS_READ_RAZ | ACCESS_WRITE_IGNORED);
1080 updated_state = false;
1082 spin_unlock(&vcpu->kvm->arch.vgic.lock);
1083 kvm_prepare_mmio(run, mmio);
1084 kvm_handle_mmio_return(vcpu, run);
1087 vgic_kick_vcpus(vcpu->kvm);
1092 static u8 *vgic_get_sgi_sources(struct vgic_dist *dist, int vcpu_id, int sgi)
1094 return dist->irq_sgi_sources + vcpu_id * VGIC_NR_SGIS + sgi;
1097 static void vgic_dispatch_sgi(struct kvm_vcpu *vcpu, u32 reg)
1099 struct kvm *kvm = vcpu->kvm;
1100 struct vgic_dist *dist = &kvm->arch.vgic;
1101 int nrcpus = atomic_read(&kvm->online_vcpus);
1103 int sgi, mode, c, vcpu_id;
1105 vcpu_id = vcpu->vcpu_id;
1108 target_cpus = (reg >> 16) & 0xff;
1109 mode = (reg >> 24) & 3;
1118 target_cpus = ((1 << nrcpus) - 1) & ~(1 << vcpu_id) & 0xff;
1122 target_cpus = 1 << vcpu_id;
1126 kvm_for_each_vcpu(c, vcpu, kvm) {
1127 if (target_cpus & 1) {
1128 /* Flag the SGI as pending */
1129 vgic_dist_irq_set_pending(vcpu, sgi);
1130 *vgic_get_sgi_sources(dist, c, sgi) |= 1 << vcpu_id;
1131 kvm_debug("SGI%d from CPU%d to CPU%d\n", sgi, vcpu_id, c);
1138 static int vgic_nr_shared_irqs(struct vgic_dist *dist)
1140 return dist->nr_irqs - VGIC_NR_PRIVATE_IRQS;
1143 static int compute_pending_for_cpu(struct kvm_vcpu *vcpu)
1145 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1146 unsigned long *pending, *enabled, *pend_percpu, *pend_shared;
1147 unsigned long pending_private, pending_shared;
1148 int nr_shared = vgic_nr_shared_irqs(dist);
1151 vcpu_id = vcpu->vcpu_id;
1152 pend_percpu = vcpu->arch.vgic_cpu.pending_percpu;
1153 pend_shared = vcpu->arch.vgic_cpu.pending_shared;
1155 pending = vgic_bitmap_get_cpu_map(&dist->irq_pending, vcpu_id);
1156 enabled = vgic_bitmap_get_cpu_map(&dist->irq_enabled, vcpu_id);
1157 bitmap_and(pend_percpu, pending, enabled, VGIC_NR_PRIVATE_IRQS);
1159 pending = vgic_bitmap_get_shared_map(&dist->irq_pending);
1160 enabled = vgic_bitmap_get_shared_map(&dist->irq_enabled);
1161 bitmap_and(pend_shared, pending, enabled, nr_shared);
1162 bitmap_and(pend_shared, pend_shared,
1163 vgic_bitmap_get_shared_map(&dist->irq_spi_target[vcpu_id]),
1166 pending_private = find_first_bit(pend_percpu, VGIC_NR_PRIVATE_IRQS);
1167 pending_shared = find_first_bit(pend_shared, nr_shared);
1168 return (pending_private < VGIC_NR_PRIVATE_IRQS ||
1169 pending_shared < vgic_nr_shared_irqs(dist));
1173 * Update the interrupt state and determine which CPUs have pending
1174 * interrupts. Must be called with distributor lock held.
1176 static void vgic_update_state(struct kvm *kvm)
1178 struct vgic_dist *dist = &kvm->arch.vgic;
1179 struct kvm_vcpu *vcpu;
1182 if (!dist->enabled) {
1183 set_bit(0, dist->irq_pending_on_cpu);
1187 kvm_for_each_vcpu(c, vcpu, kvm) {
1188 if (compute_pending_for_cpu(vcpu)) {
1189 pr_debug("CPU%d has pending interrupts\n", c);
1190 set_bit(c, dist->irq_pending_on_cpu);
1195 static struct vgic_lr vgic_get_lr(const struct kvm_vcpu *vcpu, int lr)
1197 return vgic_ops->get_lr(vcpu, lr);
1200 static void vgic_set_lr(struct kvm_vcpu *vcpu, int lr,
1203 vgic_ops->set_lr(vcpu, lr, vlr);
1206 static void vgic_sync_lr_elrsr(struct kvm_vcpu *vcpu, int lr,
1209 vgic_ops->sync_lr_elrsr(vcpu, lr, vlr);
1212 static inline u64 vgic_get_elrsr(struct kvm_vcpu *vcpu)
1214 return vgic_ops->get_elrsr(vcpu);
1217 static inline u64 vgic_get_eisr(struct kvm_vcpu *vcpu)
1219 return vgic_ops->get_eisr(vcpu);
1222 static inline u32 vgic_get_interrupt_status(struct kvm_vcpu *vcpu)
1224 return vgic_ops->get_interrupt_status(vcpu);
1227 static inline void vgic_enable_underflow(struct kvm_vcpu *vcpu)
1229 vgic_ops->enable_underflow(vcpu);
1232 static inline void vgic_disable_underflow(struct kvm_vcpu *vcpu)
1234 vgic_ops->disable_underflow(vcpu);
1237 static inline void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1239 vgic_ops->get_vmcr(vcpu, vmcr);
1242 static void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
1244 vgic_ops->set_vmcr(vcpu, vmcr);
1247 static inline void vgic_enable(struct kvm_vcpu *vcpu)
1249 vgic_ops->enable(vcpu);
1252 static void vgic_retire_lr(int lr_nr, int irq, struct kvm_vcpu *vcpu)
1254 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1255 struct vgic_lr vlr = vgic_get_lr(vcpu, lr_nr);
1258 vgic_set_lr(vcpu, lr_nr, vlr);
1259 clear_bit(lr_nr, vgic_cpu->lr_used);
1260 vgic_cpu->vgic_irq_lr_map[irq] = LR_EMPTY;
1264 * An interrupt may have been disabled after being made pending on the
1265 * CPU interface (the classic case is a timer running while we're
1266 * rebooting the guest - the interrupt would kick as soon as the CPU
1267 * interface gets enabled, with deadly consequences).
1269 * The solution is to examine already active LRs, and check the
1270 * interrupt is still enabled. If not, just retire it.
1272 static void vgic_retire_disabled_irqs(struct kvm_vcpu *vcpu)
1274 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1277 for_each_set_bit(lr, vgic_cpu->lr_used, vgic->nr_lr) {
1278 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1280 if (!vgic_irq_is_enabled(vcpu, vlr.irq)) {
1281 vgic_retire_lr(lr, vlr.irq, vcpu);
1282 if (vgic_irq_is_queued(vcpu, vlr.irq))
1283 vgic_irq_clear_queued(vcpu, vlr.irq);
1289 * Queue an interrupt to a CPU virtual interface. Return true on success,
1290 * or false if it wasn't possible to queue it.
1292 static bool vgic_queue_irq(struct kvm_vcpu *vcpu, u8 sgi_source_id, int irq)
1294 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1295 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1299 /* Sanitize the input... */
1300 BUG_ON(sgi_source_id & ~7);
1301 BUG_ON(sgi_source_id && irq >= VGIC_NR_SGIS);
1302 BUG_ON(irq >= dist->nr_irqs);
1304 kvm_debug("Queue IRQ%d\n", irq);
1306 lr = vgic_cpu->vgic_irq_lr_map[irq];
1308 /* Do we have an active interrupt for the same CPUID? */
1309 if (lr != LR_EMPTY) {
1310 vlr = vgic_get_lr(vcpu, lr);
1311 if (vlr.source == sgi_source_id) {
1312 kvm_debug("LR%d piggyback for IRQ%d\n", lr, vlr.irq);
1313 BUG_ON(!test_bit(lr, vgic_cpu->lr_used));
1314 vlr.state |= LR_STATE_PENDING;
1315 vgic_set_lr(vcpu, lr, vlr);
1320 /* Try to use another LR for this interrupt */
1321 lr = find_first_zero_bit((unsigned long *)vgic_cpu->lr_used,
1323 if (lr >= vgic->nr_lr)
1326 kvm_debug("LR%d allocated for IRQ%d %x\n", lr, irq, sgi_source_id);
1327 vgic_cpu->vgic_irq_lr_map[irq] = lr;
1328 set_bit(lr, vgic_cpu->lr_used);
1331 vlr.source = sgi_source_id;
1332 vlr.state = LR_STATE_PENDING;
1333 if (!vgic_irq_is_edge(vcpu, irq))
1334 vlr.state |= LR_EOI_INT;
1336 vgic_set_lr(vcpu, lr, vlr);
1341 static bool vgic_queue_sgi(struct kvm_vcpu *vcpu, int irq)
1343 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1344 unsigned long sources;
1345 int vcpu_id = vcpu->vcpu_id;
1348 sources = *vgic_get_sgi_sources(dist, vcpu_id, irq);
1350 for_each_set_bit(c, &sources, dist->nr_cpus) {
1351 if (vgic_queue_irq(vcpu, c, irq))
1352 clear_bit(c, &sources);
1355 *vgic_get_sgi_sources(dist, vcpu_id, irq) = sources;
1358 * If the sources bitmap has been cleared it means that we
1359 * could queue all the SGIs onto link registers (see the
1360 * clear_bit above), and therefore we are done with them in
1361 * our emulated gic and can get rid of them.
1364 vgic_dist_irq_clear_pending(vcpu, irq);
1365 vgic_cpu_irq_clear(vcpu, irq);
1372 static bool vgic_queue_hwirq(struct kvm_vcpu *vcpu, int irq)
1374 if (!vgic_can_sample_irq(vcpu, irq))
1375 return true; /* level interrupt, already queued */
1377 if (vgic_queue_irq(vcpu, 0, irq)) {
1378 if (vgic_irq_is_edge(vcpu, irq)) {
1379 vgic_dist_irq_clear_pending(vcpu, irq);
1380 vgic_cpu_irq_clear(vcpu, irq);
1382 vgic_irq_set_queued(vcpu, irq);
1392 * Fill the list registers with pending interrupts before running the
1395 static void __kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1397 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1398 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1402 vcpu_id = vcpu->vcpu_id;
1405 * We may not have any pending interrupt, or the interrupts
1406 * may have been serviced from another vcpu. In all cases,
1409 if (!kvm_vgic_vcpu_pending_irq(vcpu)) {
1410 pr_debug("CPU%d has no pending interrupt\n", vcpu_id);
1415 for_each_set_bit(i, vgic_cpu->pending_percpu, VGIC_NR_SGIS) {
1416 if (!vgic_queue_sgi(vcpu, i))
1421 for_each_set_bit_from(i, vgic_cpu->pending_percpu, VGIC_NR_PRIVATE_IRQS) {
1422 if (!vgic_queue_hwirq(vcpu, i))
1427 for_each_set_bit(i, vgic_cpu->pending_shared, vgic_nr_shared_irqs(dist)) {
1428 if (!vgic_queue_hwirq(vcpu, i + VGIC_NR_PRIVATE_IRQS))
1434 vgic_enable_underflow(vcpu);
1436 vgic_disable_underflow(vcpu);
1438 * We're about to run this VCPU, and we've consumed
1439 * everything the distributor had in store for
1440 * us. Claim we don't have anything pending. We'll
1441 * adjust that if needed while exiting.
1443 clear_bit(vcpu_id, dist->irq_pending_on_cpu);
1447 static bool vgic_process_maintenance(struct kvm_vcpu *vcpu)
1449 u32 status = vgic_get_interrupt_status(vcpu);
1450 bool level_pending = false;
1452 kvm_debug("STATUS = %08x\n", status);
1454 if (status & INT_STATUS_EOI) {
1456 * Some level interrupts have been EOIed. Clear their
1459 u64 eisr = vgic_get_eisr(vcpu);
1460 unsigned long *eisr_ptr = u64_to_bitmask(&eisr);
1463 for_each_set_bit(lr, eisr_ptr, vgic->nr_lr) {
1464 struct vgic_lr vlr = vgic_get_lr(vcpu, lr);
1465 WARN_ON(vgic_irq_is_edge(vcpu, vlr.irq));
1467 vgic_irq_clear_queued(vcpu, vlr.irq);
1468 WARN_ON(vlr.state & LR_STATE_MASK);
1470 vgic_set_lr(vcpu, lr, vlr);
1473 * If the IRQ was EOIed it was also ACKed and we we
1474 * therefore assume we can clear the soft pending
1475 * state (should it had been set) for this interrupt.
1477 * Note: if the IRQ soft pending state was set after
1478 * the IRQ was acked, it actually shouldn't be
1479 * cleared, but we have no way of knowing that unless
1480 * we start trapping ACKs when the soft-pending state
1483 vgic_dist_irq_clear_soft_pend(vcpu, vlr.irq);
1485 /* Any additional pending interrupt? */
1486 if (vgic_dist_irq_get_level(vcpu, vlr.irq)) {
1487 vgic_cpu_irq_set(vcpu, vlr.irq);
1488 level_pending = true;
1490 vgic_dist_irq_clear_pending(vcpu, vlr.irq);
1491 vgic_cpu_irq_clear(vcpu, vlr.irq);
1495 * Despite being EOIed, the LR may not have
1496 * been marked as empty.
1498 vgic_sync_lr_elrsr(vcpu, lr, vlr);
1502 if (status & INT_STATUS_UNDERFLOW)
1503 vgic_disable_underflow(vcpu);
1505 return level_pending;
1509 * Sync back the VGIC state after a guest run. The distributor lock is
1510 * needed so we don't get preempted in the middle of the state processing.
1512 static void __kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1514 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1515 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1517 unsigned long *elrsr_ptr;
1521 level_pending = vgic_process_maintenance(vcpu);
1522 elrsr = vgic_get_elrsr(vcpu);
1523 elrsr_ptr = u64_to_bitmask(&elrsr);
1525 /* Clear mappings for empty LRs */
1526 for_each_set_bit(lr, elrsr_ptr, vgic->nr_lr) {
1529 if (!test_and_clear_bit(lr, vgic_cpu->lr_used))
1532 vlr = vgic_get_lr(vcpu, lr);
1534 BUG_ON(vlr.irq >= dist->nr_irqs);
1535 vgic_cpu->vgic_irq_lr_map[vlr.irq] = LR_EMPTY;
1538 /* Check if we still have something up our sleeve... */
1539 pending = find_first_zero_bit(elrsr_ptr, vgic->nr_lr);
1540 if (level_pending || pending < vgic->nr_lr)
1541 set_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1544 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu)
1546 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1548 if (!irqchip_in_kernel(vcpu->kvm))
1551 spin_lock(&dist->lock);
1552 __kvm_vgic_flush_hwstate(vcpu);
1553 spin_unlock(&dist->lock);
1556 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu)
1558 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1560 if (!irqchip_in_kernel(vcpu->kvm))
1563 spin_lock(&dist->lock);
1564 __kvm_vgic_sync_hwstate(vcpu);
1565 spin_unlock(&dist->lock);
1568 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
1570 struct vgic_dist *dist = &vcpu->kvm->arch.vgic;
1572 if (!irqchip_in_kernel(vcpu->kvm))
1575 return test_bit(vcpu->vcpu_id, dist->irq_pending_on_cpu);
1578 static void vgic_kick_vcpus(struct kvm *kvm)
1580 struct kvm_vcpu *vcpu;
1584 * We've injected an interrupt, time to find out who deserves
1587 kvm_for_each_vcpu(c, vcpu, kvm) {
1588 if (kvm_vgic_vcpu_pending_irq(vcpu))
1589 kvm_vcpu_kick(vcpu);
1593 static int vgic_validate_injection(struct kvm_vcpu *vcpu, int irq, int level)
1595 int edge_triggered = vgic_irq_is_edge(vcpu, irq);
1598 * Only inject an interrupt if:
1599 * - edge triggered and we have a rising edge
1600 * - level triggered and we change level
1602 if (edge_triggered) {
1603 int state = vgic_dist_irq_is_pending(vcpu, irq);
1604 return level > state;
1606 int state = vgic_dist_irq_get_level(vcpu, irq);
1607 return level != state;
1611 static int vgic_update_irq_pending(struct kvm *kvm, int cpuid,
1612 unsigned int irq_num, bool level)
1614 struct vgic_dist *dist = &kvm->arch.vgic;
1615 struct kvm_vcpu *vcpu;
1616 int edge_triggered, level_triggered;
1620 spin_lock(&dist->lock);
1622 vcpu = kvm_get_vcpu(kvm, cpuid);
1623 edge_triggered = vgic_irq_is_edge(vcpu, irq_num);
1624 level_triggered = !edge_triggered;
1626 if (!vgic_validate_injection(vcpu, irq_num, level)) {
1631 if (irq_num >= VGIC_NR_PRIVATE_IRQS) {
1632 cpuid = dist->irq_spi_cpu[irq_num - VGIC_NR_PRIVATE_IRQS];
1633 vcpu = kvm_get_vcpu(kvm, cpuid);
1636 kvm_debug("Inject IRQ%d level %d CPU%d\n", irq_num, level, cpuid);
1639 if (level_triggered)
1640 vgic_dist_irq_set_level(vcpu, irq_num);
1641 vgic_dist_irq_set_pending(vcpu, irq_num);
1643 if (level_triggered) {
1644 vgic_dist_irq_clear_level(vcpu, irq_num);
1645 if (!vgic_dist_irq_soft_pend(vcpu, irq_num))
1646 vgic_dist_irq_clear_pending(vcpu, irq_num);
1653 enabled = vgic_irq_is_enabled(vcpu, irq_num);
1660 if (!vgic_can_sample_irq(vcpu, irq_num)) {
1662 * Level interrupt in progress, will be picked up
1670 vgic_cpu_irq_set(vcpu, irq_num);
1671 set_bit(cpuid, dist->irq_pending_on_cpu);
1675 spin_unlock(&dist->lock);
1677 return ret ? cpuid : -EINVAL;
1681 * kvm_vgic_inject_irq - Inject an IRQ from a device to the vgic
1682 * @kvm: The VM structure pointer
1683 * @cpuid: The CPU for PPIs
1684 * @irq_num: The IRQ number that is assigned to the device
1685 * @level: Edge-triggered: true: to trigger the interrupt
1686 * false: to ignore the call
1687 * Level-sensitive true: activates an interrupt
1688 * false: deactivates an interrupt
1690 * The GIC is not concerned with devices being active-LOW or active-HIGH for
1691 * level-sensitive interrupts. You can think of the level parameter as 1
1692 * being HIGH and 0 being LOW and all devices being active-HIGH.
1694 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
1700 if (unlikely(!vgic_initialized(kvm))) {
1701 mutex_lock(&kvm->lock);
1702 ret = vgic_init(kvm);
1703 mutex_unlock(&kvm->lock);
1709 vcpu_id = vgic_update_irq_pending(kvm, cpuid, irq_num, level);
1711 /* kick the specified vcpu */
1712 kvm_vcpu_kick(kvm_get_vcpu(kvm, vcpu_id));
1719 static irqreturn_t vgic_maintenance_handler(int irq, void *data)
1722 * We cannot rely on the vgic maintenance interrupt to be
1723 * delivered synchronously. This means we can only use it to
1724 * exit the VM, and we perform the handling of EOIed
1725 * interrupts on the exit path (see vgic_process_maintenance).
1730 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
1732 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1734 kfree(vgic_cpu->pending_shared);
1735 kfree(vgic_cpu->vgic_irq_lr_map);
1736 vgic_cpu->pending_shared = NULL;
1737 vgic_cpu->vgic_irq_lr_map = NULL;
1740 static int vgic_vcpu_init_maps(struct kvm_vcpu *vcpu, int nr_irqs)
1742 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
1744 int sz = (nr_irqs - VGIC_NR_PRIVATE_IRQS) / 8;
1745 vgic_cpu->pending_shared = kzalloc(sz, GFP_KERNEL);
1746 vgic_cpu->vgic_irq_lr_map = kmalloc(nr_irqs, GFP_KERNEL);
1748 if (!vgic_cpu->pending_shared || !vgic_cpu->vgic_irq_lr_map) {
1749 kvm_vgic_vcpu_destroy(vcpu);
1753 memset(vgic_cpu->vgic_irq_lr_map, LR_EMPTY, nr_irqs);
1756 * Store the number of LRs per vcpu, so we don't have to go
1757 * all the way to the distributor structure to find out. Only
1758 * assembly code should use this one.
1760 vgic_cpu->nr_lr = vgic->nr_lr;
1765 void kvm_vgic_destroy(struct kvm *kvm)
1767 struct vgic_dist *dist = &kvm->arch.vgic;
1768 struct kvm_vcpu *vcpu;
1771 kvm_for_each_vcpu(i, vcpu, kvm)
1772 kvm_vgic_vcpu_destroy(vcpu);
1774 vgic_free_bitmap(&dist->irq_enabled);
1775 vgic_free_bitmap(&dist->irq_level);
1776 vgic_free_bitmap(&dist->irq_pending);
1777 vgic_free_bitmap(&dist->irq_soft_pend);
1778 vgic_free_bitmap(&dist->irq_queued);
1779 vgic_free_bitmap(&dist->irq_cfg);
1780 vgic_free_bytemap(&dist->irq_priority);
1781 if (dist->irq_spi_target) {
1782 for (i = 0; i < dist->nr_cpus; i++)
1783 vgic_free_bitmap(&dist->irq_spi_target[i]);
1785 kfree(dist->irq_sgi_sources);
1786 kfree(dist->irq_spi_cpu);
1787 kfree(dist->irq_spi_target);
1788 kfree(dist->irq_pending_on_cpu);
1789 dist->irq_sgi_sources = NULL;
1790 dist->irq_spi_cpu = NULL;
1791 dist->irq_spi_target = NULL;
1792 dist->irq_pending_on_cpu = NULL;
1797 * Allocate and initialize the various data structures. Must be called
1798 * with kvm->lock held!
1800 static int vgic_init(struct kvm *kvm)
1802 struct vgic_dist *dist = &kvm->arch.vgic;
1803 struct kvm_vcpu *vcpu;
1804 int nr_cpus, nr_irqs;
1805 int ret, i, vcpu_id;
1807 if (vgic_initialized(kvm))
1810 nr_cpus = dist->nr_cpus = atomic_read(&kvm->online_vcpus);
1811 if (!nr_cpus) /* No vcpus? Can't be good... */
1815 * If nobody configured the number of interrupts, use the
1819 dist->nr_irqs = VGIC_NR_IRQS_LEGACY;
1821 nr_irqs = dist->nr_irqs;
1823 ret = vgic_init_bitmap(&dist->irq_enabled, nr_cpus, nr_irqs);
1824 ret |= vgic_init_bitmap(&dist->irq_level, nr_cpus, nr_irqs);
1825 ret |= vgic_init_bitmap(&dist->irq_pending, nr_cpus, nr_irqs);
1826 ret |= vgic_init_bitmap(&dist->irq_soft_pend, nr_cpus, nr_irqs);
1827 ret |= vgic_init_bitmap(&dist->irq_queued, nr_cpus, nr_irqs);
1828 ret |= vgic_init_bitmap(&dist->irq_cfg, nr_cpus, nr_irqs);
1829 ret |= vgic_init_bytemap(&dist->irq_priority, nr_cpus, nr_irqs);
1834 dist->irq_sgi_sources = kzalloc(nr_cpus * VGIC_NR_SGIS, GFP_KERNEL);
1835 dist->irq_spi_cpu = kzalloc(nr_irqs - VGIC_NR_PRIVATE_IRQS, GFP_KERNEL);
1836 dist->irq_spi_target = kzalloc(sizeof(*dist->irq_spi_target) * nr_cpus,
1838 dist->irq_pending_on_cpu = kzalloc(BITS_TO_LONGS(nr_cpus) * sizeof(long),
1840 if (!dist->irq_sgi_sources ||
1841 !dist->irq_spi_cpu ||
1842 !dist->irq_spi_target ||
1843 !dist->irq_pending_on_cpu) {
1848 for (i = 0; i < nr_cpus; i++)
1849 ret |= vgic_init_bitmap(&dist->irq_spi_target[i],
1855 for (i = VGIC_NR_PRIVATE_IRQS; i < dist->nr_irqs; i += 4)
1856 vgic_set_target_reg(kvm, 0, i);
1858 kvm_for_each_vcpu(vcpu_id, vcpu, kvm) {
1859 ret = vgic_vcpu_init_maps(vcpu, nr_irqs);
1861 kvm_err("VGIC: Failed to allocate vcpu memory\n");
1865 for (i = 0; i < dist->nr_irqs; i++) {
1866 if (i < VGIC_NR_PPIS)
1867 vgic_bitmap_set_irq_val(&dist->irq_enabled,
1868 vcpu->vcpu_id, i, 1);
1869 if (i < VGIC_NR_PRIVATE_IRQS)
1870 vgic_bitmap_set_irq_val(&dist->irq_cfg,
1880 kvm_vgic_destroy(kvm);
1886 * kvm_vgic_map_resources - Configure global VGIC state before running any VCPUs
1887 * @kvm: pointer to the kvm struct
1889 * Map the virtual CPU interface into the VM before running any VCPUs. We
1890 * can't do this at creation time, because user space must first set the
1891 * virtual CPU interface address in the guest physical address space.
1893 int kvm_vgic_map_resources(struct kvm *kvm)
1897 if (!irqchip_in_kernel(kvm))
1900 mutex_lock(&kvm->lock);
1902 if (vgic_ready(kvm))
1905 if (IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_dist_base) ||
1906 IS_VGIC_ADDR_UNDEF(kvm->arch.vgic.vgic_cpu_base)) {
1907 kvm_err("Need to set vgic cpu and dist addresses first\n");
1913 * Initialize the vgic if this hasn't already been done on demand by
1914 * accessing the vgic state from userspace.
1916 ret = vgic_init(kvm);
1918 kvm_err("Unable to allocate maps\n");
1922 ret = kvm_phys_addr_ioremap(kvm, kvm->arch.vgic.vgic_cpu_base,
1923 vgic->vcpu_base, KVM_VGIC_V2_CPU_SIZE,
1926 kvm_err("Unable to remap VGIC CPU to VCPU\n");
1930 kvm->arch.vgic.ready = true;
1933 kvm_vgic_destroy(kvm);
1934 mutex_unlock(&kvm->lock);
1938 int kvm_vgic_create(struct kvm *kvm)
1940 int i, vcpu_lock_idx = -1, ret;
1941 struct kvm_vcpu *vcpu;
1943 mutex_lock(&kvm->lock);
1945 if (kvm->arch.vgic.vctrl_base) {
1951 * Any time a vcpu is run, vcpu_load is called which tries to grab the
1952 * vcpu->mutex. By grabbing the vcpu->mutex of all VCPUs we ensure
1953 * that no other VCPUs are run while we create the vgic.
1956 kvm_for_each_vcpu(i, vcpu, kvm) {
1957 if (!mutex_trylock(&vcpu->mutex))
1962 kvm_for_each_vcpu(i, vcpu, kvm) {
1963 if (vcpu->arch.has_run_once)
1968 spin_lock_init(&kvm->arch.vgic.lock);
1969 kvm->arch.vgic.in_kernel = true;
1970 kvm->arch.vgic.vctrl_base = vgic->vctrl_base;
1971 kvm->arch.vgic.vgic_dist_base = VGIC_ADDR_UNDEF;
1972 kvm->arch.vgic.vgic_cpu_base = VGIC_ADDR_UNDEF;
1975 for (; vcpu_lock_idx >= 0; vcpu_lock_idx--) {
1976 vcpu = kvm_get_vcpu(kvm, vcpu_lock_idx);
1977 mutex_unlock(&vcpu->mutex);
1981 mutex_unlock(&kvm->lock);
1985 static int vgic_ioaddr_overlap(struct kvm *kvm)
1987 phys_addr_t dist = kvm->arch.vgic.vgic_dist_base;
1988 phys_addr_t cpu = kvm->arch.vgic.vgic_cpu_base;
1990 if (IS_VGIC_ADDR_UNDEF(dist) || IS_VGIC_ADDR_UNDEF(cpu))
1992 if ((dist <= cpu && dist + KVM_VGIC_V2_DIST_SIZE > cpu) ||
1993 (cpu <= dist && cpu + KVM_VGIC_V2_CPU_SIZE > dist))
1998 static int vgic_ioaddr_assign(struct kvm *kvm, phys_addr_t *ioaddr,
1999 phys_addr_t addr, phys_addr_t size)
2003 if (addr & ~KVM_PHYS_MASK)
2006 if (addr & (SZ_4K - 1))
2009 if (!IS_VGIC_ADDR_UNDEF(*ioaddr))
2011 if (addr + size < addr)
2015 ret = vgic_ioaddr_overlap(kvm);
2017 *ioaddr = VGIC_ADDR_UNDEF;
2023 * kvm_vgic_addr - set or get vgic VM base addresses
2024 * @kvm: pointer to the vm struct
2025 * @type: the VGIC addr type, one of KVM_VGIC_V2_ADDR_TYPE_XXX
2026 * @addr: pointer to address value
2027 * @write: if true set the address in the VM address space, if false read the
2030 * Set or get the vgic base addresses for the distributor and the virtual CPU
2031 * interface in the VM physical address space. These addresses are properties
2032 * of the emulated core/SoC and therefore user space initially knows this
2035 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
2038 struct vgic_dist *vgic = &kvm->arch.vgic;
2040 mutex_lock(&kvm->lock);
2042 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2044 r = vgic_ioaddr_assign(kvm, &vgic->vgic_dist_base,
2045 *addr, KVM_VGIC_V2_DIST_SIZE);
2047 *addr = vgic->vgic_dist_base;
2050 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2052 r = vgic_ioaddr_assign(kvm, &vgic->vgic_cpu_base,
2053 *addr, KVM_VGIC_V2_CPU_SIZE);
2055 *addr = vgic->vgic_cpu_base;
2062 mutex_unlock(&kvm->lock);
2066 static bool handle_cpu_mmio_misc(struct kvm_vcpu *vcpu,
2067 struct kvm_exit_mmio *mmio, phys_addr_t offset)
2069 bool updated = false;
2070 struct vgic_vmcr vmcr;
2074 vgic_get_vmcr(vcpu, &vmcr);
2076 switch (offset & ~0x3) {
2078 vmcr_field = &vmcr.ctlr;
2080 case GIC_CPU_PRIMASK:
2081 vmcr_field = &vmcr.pmr;
2083 case GIC_CPU_BINPOINT:
2084 vmcr_field = &vmcr.bpr;
2086 case GIC_CPU_ALIAS_BINPOINT:
2087 vmcr_field = &vmcr.abpr;
2093 if (!mmio->is_write) {
2095 mmio_data_write(mmio, ~0, reg);
2097 reg = mmio_data_read(mmio, ~0);
2098 if (reg != *vmcr_field) {
2100 vgic_set_vmcr(vcpu, &vmcr);
2107 static bool handle_mmio_abpr(struct kvm_vcpu *vcpu,
2108 struct kvm_exit_mmio *mmio, phys_addr_t offset)
2110 return handle_cpu_mmio_misc(vcpu, mmio, GIC_CPU_ALIAS_BINPOINT);
2113 static bool handle_cpu_mmio_ident(struct kvm_vcpu *vcpu,
2114 struct kvm_exit_mmio *mmio,
2123 reg = (PRODUCT_ID_KVM << 20) |
2124 (GICC_ARCH_VERSION_V2 << 16) |
2125 (IMPLEMENTER_ARM << 0);
2126 mmio_data_write(mmio, ~0, reg);
2131 * CPU Interface Register accesses - these are not accessed by the VM, but by
2132 * user space for saving and restoring VGIC state.
2134 static const struct mmio_range vgic_cpu_ranges[] = {
2136 .base = GIC_CPU_CTRL,
2138 .handle_mmio = handle_cpu_mmio_misc,
2141 .base = GIC_CPU_ALIAS_BINPOINT,
2143 .handle_mmio = handle_mmio_abpr,
2146 .base = GIC_CPU_ACTIVEPRIO,
2148 .handle_mmio = handle_mmio_raz_wi,
2151 .base = GIC_CPU_IDENT,
2153 .handle_mmio = handle_cpu_mmio_ident,
2157 static int vgic_attr_regs_access(struct kvm_device *dev,
2158 struct kvm_device_attr *attr,
2159 u32 *reg, bool is_write)
2161 const struct mmio_range *r = NULL, *ranges;
2164 struct kvm_vcpu *vcpu, *tmp_vcpu;
2165 struct vgic_dist *vgic;
2166 struct kvm_exit_mmio mmio;
2168 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2169 cpuid = (attr->attr & KVM_DEV_ARM_VGIC_CPUID_MASK) >>
2170 KVM_DEV_ARM_VGIC_CPUID_SHIFT;
2172 mutex_lock(&dev->kvm->lock);
2174 ret = vgic_init(dev->kvm);
2178 if (cpuid >= atomic_read(&dev->kvm->online_vcpus)) {
2183 vcpu = kvm_get_vcpu(dev->kvm, cpuid);
2184 vgic = &dev->kvm->arch.vgic;
2187 mmio.is_write = is_write;
2189 mmio_data_write(&mmio, ~0, *reg);
2190 switch (attr->group) {
2191 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2192 mmio.phys_addr = vgic->vgic_dist_base + offset;
2193 ranges = vgic_dist_ranges;
2195 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2196 mmio.phys_addr = vgic->vgic_cpu_base + offset;
2197 ranges = vgic_cpu_ranges;
2202 r = find_matching_range(ranges, &mmio, offset);
2204 if (unlikely(!r || !r->handle_mmio)) {
2210 spin_lock(&vgic->lock);
2213 * Ensure that no other VCPU is running by checking the vcpu->cpu
2214 * field. If no other VPCUs are running we can safely access the VGIC
2215 * state, because even if another VPU is run after this point, that
2216 * VCPU will not touch the vgic state, because it will block on
2217 * getting the vgic->lock in kvm_vgic_sync_hwstate().
2219 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm) {
2220 if (unlikely(tmp_vcpu->cpu != -1)) {
2222 goto out_vgic_unlock;
2227 * Move all pending IRQs from the LRs on all VCPUs so the pending
2228 * state can be properly represented in the register state accessible
2231 kvm_for_each_vcpu(c, tmp_vcpu, dev->kvm)
2232 vgic_unqueue_irqs(tmp_vcpu);
2235 r->handle_mmio(vcpu, &mmio, offset);
2238 *reg = mmio_data_read(&mmio, ~0);
2242 spin_unlock(&vgic->lock);
2244 mutex_unlock(&dev->kvm->lock);
2248 static int vgic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2252 switch (attr->group) {
2253 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2254 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2256 unsigned long type = (unsigned long)attr->attr;
2258 if (copy_from_user(&addr, uaddr, sizeof(addr)))
2261 r = kvm_vgic_addr(dev->kvm, type, &addr, true);
2262 return (r == -ENODEV) ? -ENXIO : r;
2265 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2266 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2267 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2270 if (get_user(reg, uaddr))
2273 return vgic_attr_regs_access(dev, attr, ®, true);
2275 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2276 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2280 if (get_user(val, uaddr))
2285 * - at least 32 SPIs on top of the 16 SGIs and 16 PPIs
2286 * - at most 1024 interrupts
2287 * - a multiple of 32 interrupts
2289 if (val < (VGIC_NR_PRIVATE_IRQS + 32) ||
2290 val > VGIC_MAX_IRQS ||
2294 mutex_lock(&dev->kvm->lock);
2296 if (vgic_ready(dev->kvm) || dev->kvm->arch.vgic.nr_irqs)
2299 dev->kvm->arch.vgic.nr_irqs = val;
2301 mutex_unlock(&dev->kvm->lock);
2311 static int vgic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2315 switch (attr->group) {
2316 case KVM_DEV_ARM_VGIC_GRP_ADDR: {
2317 u64 __user *uaddr = (u64 __user *)(long)attr->addr;
2319 unsigned long type = (unsigned long)attr->attr;
2321 r = kvm_vgic_addr(dev->kvm, type, &addr, false);
2323 return (r == -ENODEV) ? -ENXIO : r;
2325 if (copy_to_user(uaddr, &addr, sizeof(addr)))
2330 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2331 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS: {
2332 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2335 r = vgic_attr_regs_access(dev, attr, ®, false);
2338 r = put_user(reg, uaddr);
2341 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS: {
2342 u32 __user *uaddr = (u32 __user *)(long)attr->addr;
2343 r = put_user(dev->kvm->arch.vgic.nr_irqs, uaddr);
2352 static int vgic_has_attr_regs(const struct mmio_range *ranges,
2355 struct kvm_exit_mmio dev_attr_mmio;
2357 dev_attr_mmio.len = 4;
2358 if (find_matching_range(ranges, &dev_attr_mmio, offset))
2364 static int vgic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
2368 switch (attr->group) {
2369 case KVM_DEV_ARM_VGIC_GRP_ADDR:
2370 switch (attr->attr) {
2371 case KVM_VGIC_V2_ADDR_TYPE_DIST:
2372 case KVM_VGIC_V2_ADDR_TYPE_CPU:
2376 case KVM_DEV_ARM_VGIC_GRP_DIST_REGS:
2377 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2378 return vgic_has_attr_regs(vgic_dist_ranges, offset);
2379 case KVM_DEV_ARM_VGIC_GRP_CPU_REGS:
2380 offset = attr->attr & KVM_DEV_ARM_VGIC_OFFSET_MASK;
2381 return vgic_has_attr_regs(vgic_cpu_ranges, offset);
2382 case KVM_DEV_ARM_VGIC_GRP_NR_IRQS:
2388 static void vgic_destroy(struct kvm_device *dev)
2393 static int vgic_create(struct kvm_device *dev, u32 type)
2395 return kvm_vgic_create(dev->kvm);
2398 static struct kvm_device_ops kvm_arm_vgic_v2_ops = {
2399 .name = "kvm-arm-vgic",
2400 .create = vgic_create,
2401 .destroy = vgic_destroy,
2402 .set_attr = vgic_set_attr,
2403 .get_attr = vgic_get_attr,
2404 .has_attr = vgic_has_attr,
2407 static void vgic_init_maintenance_interrupt(void *info)
2409 enable_percpu_irq(vgic->maint_irq, 0);
2412 static int vgic_cpu_notify(struct notifier_block *self,
2413 unsigned long action, void *cpu)
2417 case CPU_STARTING_FROZEN:
2418 vgic_init_maintenance_interrupt(NULL);
2421 case CPU_DYING_FROZEN:
2422 disable_percpu_irq(vgic->maint_irq);
2429 static struct notifier_block vgic_cpu_nb = {
2430 .notifier_call = vgic_cpu_notify,
2433 static const struct of_device_id vgic_ids[] = {
2434 { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
2435 { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
2439 int kvm_vgic_hyp_init(void)
2441 const struct of_device_id *matched_id;
2442 const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
2443 const struct vgic_params **);
2444 struct device_node *vgic_node;
2447 vgic_node = of_find_matching_node_and_match(NULL,
2448 vgic_ids, &matched_id);
2450 kvm_err("error: no compatible GIC node found\n");
2454 vgic_probe = matched_id->data;
2455 ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
2459 ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
2460 "vgic", kvm_get_running_vcpus());
2462 kvm_err("Cannot register interrupt %d\n", vgic->maint_irq);
2466 ret = __register_cpu_notifier(&vgic_cpu_nb);
2468 kvm_err("Cannot register vgic CPU notifier\n");
2472 /* Callback into for arch code for setup */
2473 vgic_arch_setup(vgic);
2475 on_each_cpu(vgic_init_maintenance_interrupt, NULL, 1);
2477 return kvm_register_device_ops(&kvm_arm_vgic_v2_ops,
2478 KVM_DEV_TYPE_ARM_VGIC_V2);
2481 free_percpu_irq(vgic->maint_irq, kvm_get_running_vcpus());