virt/kvm/arm/vgic/vgic-mmio.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * VGIC MMIO handling functions
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/bsearch.h>
   8 #include <linux/kvm.h>
   9 #include <linux/kvm_host.h>
  10 #include <kvm/iodev.h>
  11 #include <kvm/arm_arch_timer.h>
  12 #include <kvm/arm_vgic.h>
  13
  14 #include "vgic.h"
  15 #include "vgic-mmio.h"
  16
  17 unsigned long vgic_mmio_read_raz(struct kvm_vcpu *vcpu,
  18                                  gpa_t addr, unsigned int len)
  19 {
  20         return 0;
  21 }
  22
  23 unsigned long vgic_mmio_read_rao(struct kvm_vcpu *vcpu,
  24                                  gpa_t addr, unsigned int len)
  25 {
  26         return -1UL;
  27 }
  28
  29 void vgic_mmio_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  30                         unsigned int len, unsigned long val)
  31 {
  32         /* Ignore */
  33 }
  34
  35 int vgic_mmio_uaccess_write_wi(struct kvm_vcpu *vcpu, gpa_t addr,
  36                                unsigned int len, unsigned long val)
  37 {
  38         /* Ignore */
  39         return 0;
  40 }
  41
  42 unsigned long vgic_mmio_read_group(struct kvm_vcpu *vcpu,
  43                                    gpa_t addr, unsigned int len)
  44 {
  45         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  46         u32 value = 0;
  47         int i;
  48
  49         /* Loop over all IRQs affected by this read */
  50         for (i = 0; i < len * 8; i++) {
  51                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  52
  53                 if (irq->group)
  54                         value |= BIT(i);
  55
  56                 vgic_put_irq(vcpu->kvm, irq);
  57         }
  58
  59         return value;
  60 }
  61
  62 void vgic_mmio_write_group(struct kvm_vcpu *vcpu, gpa_t addr,
  63                            unsigned int len, unsigned long val)
  64 {
  65         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  66         int i;
  67         unsigned long flags;
  68
  69         for (i = 0; i < len * 8; i++) {
  70                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  71
  72                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
  73                 irq->group = !!(val & BIT(i));
  74                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
  75
  76                 vgic_put_irq(vcpu->kvm, irq);
  77         }
  78 }
  79
  80 /*
  81  * Read accesses to both GICD_ICENABLER and GICD_ISENABLER return the value
  82  * of the enabled bit, so there is only one function for both here.
  83  */
  84 unsigned long vgic_mmio_read_enable(struct kvm_vcpu *vcpu,
  85                                     gpa_t addr, unsigned int len)
  86 {
  87         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
  88         u32 value = 0;
  89         int i;
  90
  91         /* Loop over all IRQs affected by this read */
  92         for (i = 0; i < len * 8; i++) {
  93                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
  94
  95                 if (irq->enabled)
  96                         value |= (1U << i);
  97
  98                 vgic_put_irq(vcpu->kvm, irq);
  99         }
 100
 101         return value;
 102 }
 103
 104 void vgic_mmio_write_senable(struct kvm_vcpu *vcpu,
 105                              gpa_t addr, unsigned int len,
 106                              unsigned long val)
 107 {
 108         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 109         int i;
 110         unsigned long flags;
 111
 112         for_each_set_bit(i, &val, len * 8) {
 113                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 114
 115                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 116                 if (vgic_irq_is_mapped_level(irq)) {
 117                         bool was_high = irq->line_level;
 118
 119                         /*
 120                          * We need to update the state of the interrupt because
 121                          * the guest might have changed the state of the device
 122                          * while the interrupt was disabled at the VGIC level.
 123                          */
 124                         irq->line_level = vgic_get_phys_line_level(irq);
 125                         /*
 126                          * Deactivate the physical interrupt so the GIC will let
 127                          * us know when it is asserted again.
 128                          */
 129                         if (!irq->active && was_high && !irq->line_level)
 130                                 vgic_irq_set_phys_active(irq, false);
 131                 }
 132                 irq->enabled = true;
 133                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 134
 135                 vgic_put_irq(vcpu->kvm, irq);
 136         }
 137 }
 138
 139 void vgic_mmio_write_cenable(struct kvm_vcpu *vcpu,
 140                              gpa_t addr, unsigned int len,
 141                              unsigned long val)
 142 {
 143         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 144         int i;
 145         unsigned long flags;
 146
 147         for_each_set_bit(i, &val, len * 8) {
 148                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 149
 150                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 151
 152                 irq->enabled = false;
 153
 154                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 155                 vgic_put_irq(vcpu->kvm, irq);
 156         }
 157 }
 158
 159 unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
 160                                      gpa_t addr, unsigned int len)
 161 {
 162         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 163         u32 value = 0;
 164         int i;
 165
 166         /* Loop over all IRQs affected by this read */
 167         for (i = 0; i < len * 8; i++) {
 168                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 169                 unsigned long flags;
 170
 171                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 172                 if (irq_is_pending(irq))
 173                         value |= (1U << i);
 174                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 175
 176                 vgic_put_irq(vcpu->kvm, irq);
 177         }
 178
 179         return value;
 180 }
 181
 182 /*
 183  * This function will return the VCPU that performed the MMIO access and
 184  * trapped from within the VM, and will return NULL if this is a userspace
 185  * access.
 186  *
 187  * We can disable preemption locally around accessing the per-CPU variable,
 188  * and use the resolved vcpu pointer after enabling preemption again, because
 189  * even if the current thread is migrated to another CPU, reading the per-CPU
 190  * value later will give us the same value as we update the per-CPU variable
 191  * in the preempt notifier handlers.
 192  */
 193 static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
 194 {
 195         struct kvm_vcpu *vcpu;
 196
 197         preempt_disable();
 198         vcpu = kvm_arm_get_running_vcpu();
 199         preempt_enable();
 200         return vcpu;
 201 }
 202
 203 /* Must be called with irq->irq_lock held */
 204 static void vgic_hw_irq_spending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 205                                  bool is_uaccess)
 206 {
 207         if (is_uaccess)
 208                 return;
 209
 210         irq->pending_latch = true;
 211         vgic_irq_set_phys_active(irq, true);
 212 }
 213
 214 void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
 215                               gpa_t addr, unsigned int len,
 216                               unsigned long val)
 217 {
 218         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 219         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 220         int i;
 221         unsigned long flags;
 222
 223         for_each_set_bit(i, &val, len * 8) {
 224                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 225
 226                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 227                 if (irq->hw)
 228                         vgic_hw_irq_spending(vcpu, irq, is_uaccess);
 229                 else
 230                         irq->pending_latch = true;
 231                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 232                 vgic_put_irq(vcpu->kvm, irq);
 233         }
 234 }
 235
 236 /* Must be called with irq->irq_lock held */
 237 static void vgic_hw_irq_cpending(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 238                                  bool is_uaccess)
 239 {
 240         if (is_uaccess)
 241                 return;
 242
 243         irq->pending_latch = false;
 244
 245         /*
 246          * We don't want the guest to effectively mask the physical
 247          * interrupt by doing a write to SPENDR followed by a write to
 248          * CPENDR for HW interrupts, so we clear the active state on
 249          * the physical side if the virtual interrupt is not active.
 250          * This may lead to taking an additional interrupt on the
 251          * host, but that should not be a problem as the worst that
 252          * can happen is an additional vgic injection.  We also clear
 253          * the pending state to maintain proper semantics for edge HW
 254          * interrupts.
 255          */
 256         vgic_irq_set_phys_pending(irq, false);
 257         if (!irq->active)
 258                 vgic_irq_set_phys_active(irq, false);
 259 }
 260
 261 void vgic_mmio_write_cpending(struct kvm_vcpu *vcpu,
 262                               gpa_t addr, unsigned int len,
 263                               unsigned long val)
 264 {
 265         bool is_uaccess = !vgic_get_mmio_requester_vcpu();
 266         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 267         int i;
 268         unsigned long flags;
 269
 270         for_each_set_bit(i, &val, len * 8) {
 271                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 272
 273                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 274
 275                 if (irq->hw)
 276                         vgic_hw_irq_cpending(vcpu, irq, is_uaccess);
 277                 else
 278                         irq->pending_latch = false;
 279
 280                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 281                 vgic_put_irq(vcpu->kvm, irq);
 282         }
 283 }
 284
 285 unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
 286                                     gpa_t addr, unsigned int len)
 287 {
 288         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 289         u32 value = 0;
 290         int i;
 291
 292         /* Loop over all IRQs affected by this read */
 293         for (i = 0; i < len * 8; i++) {
 294                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 295
 296                 if (irq->active)
 297                         value |= (1U << i);
 298
 299                 vgic_put_irq(vcpu->kvm, irq);
 300         }
 301
 302         return value;
 303 }
 304
 305 /* Must be called with irq->irq_lock held */
 306 static void vgic_hw_irq_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 307                                       bool active, bool is_uaccess)
 308 {
 309         if (is_uaccess)
 310                 return;
 311
 312         irq->active = active;
 313         vgic_irq_set_phys_active(irq, active);
 314 }
 315
 316 static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
 317                                     bool active)
 318 {
 319         unsigned long flags;
 320         struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
 321
 322         raw_spin_lock_irqsave(&irq->irq_lock, flags);
 323
 324         if (irq->hw) {
 325                 vgic_hw_irq_change_active(vcpu, irq, active, !requester_vcpu);
 326         } else {
 327                 u32 model = vcpu->kvm->arch.vgic.vgic_model;
 328                 u8 active_source;
 329
 330                 irq->active = active;
 331
 332                 /*
 333                  * The GICv2 architecture indicates that the source CPUID for
 334                  * an SGI should be provided during an EOI which implies that
 335                  * the active state is stored somewhere, but at the same time
 336                  * this state is not architecturally exposed anywhere and we
 337                  * have no way of knowing the right source.
 338                  *
 339                  * This may lead to a VCPU not being able to receive
 340                  * additional instances of a particular SGI after migration
 341                  * for a GICv2 VM on some GIC implementations.  Oh well.
 342                  */
 343                 active_source = (requester_vcpu) ? requester_vcpu->vcpu_id : 0;
 344
 345                 if (model == KVM_DEV_TYPE_ARM_VGIC_V2 &&
 346                     active && vgic_irq_is_sgi(irq->intid))
 347                         irq->active_source = active_source;
 348         }
 349
 350         if (irq->active)
 351                 vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 352         else
 353                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 354 }
 355
 356 /*
 357  * If we are fiddling with an IRQ's active state, we have to make sure the IRQ
 358  * is not queued on some running VCPU's LRs, because then the change to the
 359  * active state can be overwritten when the VCPU's state is synced coming back
 360  * from the guest.
 361  *
 362  * For shared interrupts, we have to stop all the VCPUs because interrupts can
 363  * be migrated while we don't hold the IRQ locks and we don't want to be
 364  * chasing moving targets.
 365  *
 366  * For private interrupts we don't have to do anything because userspace
 367  * accesses to the VGIC state already require all VCPUs to be stopped, and
 368  * only the VCPU itself can modify its private interrupts active state, which
 369  * guarantees that the VCPU is not running.
 370  */
 371 static void vgic_change_active_prepare(struct kvm_vcpu *vcpu, u32 intid)
 372 {
 373         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 374             intid > VGIC_NR_PRIVATE_IRQS)
 375                 kvm_arm_halt_guest(vcpu->kvm);
 376 }
 377
 378 /* See vgic_change_active_prepare */
 379 static void vgic_change_active_finish(struct kvm_vcpu *vcpu, u32 intid)
 380 {
 381         if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3 ||
 382             intid > VGIC_NR_PRIVATE_IRQS)
 383                 kvm_arm_resume_guest(vcpu->kvm);
 384 }
 385
 386 static void __vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 387                                       gpa_t addr, unsigned int len,
 388                                       unsigned long val)
 389 {
 390         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 391         int i;
 392
 393         for_each_set_bit(i, &val, len * 8) {
 394                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 395                 vgic_mmio_change_active(vcpu, irq, false);
 396                 vgic_put_irq(vcpu->kvm, irq);
 397         }
 398 }
 399
 400 void vgic_mmio_write_cactive(struct kvm_vcpu *vcpu,
 401                              gpa_t addr, unsigned int len,
 402                              unsigned long val)
 403 {
 404         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 405
 406         mutex_lock(&vcpu->kvm->lock);
 407         vgic_change_active_prepare(vcpu, intid);
 408
 409         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 410
 411         vgic_change_active_finish(vcpu, intid);
 412         mutex_unlock(&vcpu->kvm->lock);
 413 }
 414
 415 int vgic_mmio_uaccess_write_cactive(struct kvm_vcpu *vcpu,
 416                                      gpa_t addr, unsigned int len,
 417                                      unsigned long val)
 418 {
 419         __vgic_mmio_write_cactive(vcpu, addr, len, val);
 420         return 0;
 421 }
 422
 423 static void __vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 424                                       gpa_t addr, unsigned int len,
 425                                       unsigned long val)
 426 {
 427         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 428         int i;
 429
 430         for_each_set_bit(i, &val, len * 8) {
 431                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 432                 vgic_mmio_change_active(vcpu, irq, true);
 433                 vgic_put_irq(vcpu->kvm, irq);
 434         }
 435 }
 436
 437 void vgic_mmio_write_sactive(struct kvm_vcpu *vcpu,
 438                              gpa_t addr, unsigned int len,
 439                              unsigned long val)
 440 {
 441         u32 intid = VGIC_ADDR_TO_INTID(addr, 1);
 442
 443         mutex_lock(&vcpu->kvm->lock);
 444         vgic_change_active_prepare(vcpu, intid);
 445
 446         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 447
 448         vgic_change_active_finish(vcpu, intid);
 449         mutex_unlock(&vcpu->kvm->lock);
 450 }
 451
 452 int vgic_mmio_uaccess_write_sactive(struct kvm_vcpu *vcpu,
 453                                      gpa_t addr, unsigned int len,
 454                                      unsigned long val)
 455 {
 456         __vgic_mmio_write_sactive(vcpu, addr, len, val);
 457         return 0;
 458 }
 459
 460 unsigned long vgic_mmio_read_priority(struct kvm_vcpu *vcpu,
 461                                       gpa_t addr, unsigned int len)
 462 {
 463         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 464         int i;
 465         u64 val = 0;
 466
 467         for (i = 0; i < len; i++) {
 468                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 469
 470                 val |= (u64)irq->priority << (i * 8);
 471
 472                 vgic_put_irq(vcpu->kvm, irq);
 473         }
 474
 475         return val;
 476 }
 477
 478 /*
 479  * We currently don't handle changing the priority of an interrupt that
 480  * is already pending on a VCPU. If there is a need for this, we would
 481  * need to make this VCPU exit and re-evaluate the priorities, potentially
 482  * leading to this interrupt getting presented now to the guest (if it has
 483  * been masked by the priority mask before).
 484  */
 485 void vgic_mmio_write_priority(struct kvm_vcpu *vcpu,
 486                               gpa_t addr, unsigned int len,
 487                               unsigned long val)
 488 {
 489         u32 intid = VGIC_ADDR_TO_INTID(addr, 8);
 490         int i;
 491         unsigned long flags;
 492
 493         for (i = 0; i < len; i++) {
 494                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 495
 496                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 497                 /* Narrow the priority range to what we actually support */
 498                 irq->priority = (val >> (i * 8)) & GENMASK(7, 8 - VGIC_PRI_BITS);
 499                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 500
 501                 vgic_put_irq(vcpu->kvm, irq);
 502         }
 503 }
 504
 505 unsigned long vgic_mmio_read_config(struct kvm_vcpu *vcpu,
 506                                     gpa_t addr, unsigned int len)
 507 {
 508         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 509         u32 value = 0;
 510         int i;
 511
 512         for (i = 0; i < len * 4; i++) {
 513                 struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 514
 515                 if (irq->config == VGIC_CONFIG_EDGE)
 516                         value |= (2U << (i * 2));
 517
 518                 vgic_put_irq(vcpu->kvm, irq);
 519         }
 520
 521         return value;
 522 }
 523
 524 void vgic_mmio_write_config(struct kvm_vcpu *vcpu,
 525                             gpa_t addr, unsigned int len,
 526                             unsigned long val)
 527 {
 528         u32 intid = VGIC_ADDR_TO_INTID(addr, 2);
 529         int i;
 530         unsigned long flags;
 531
 532         for (i = 0; i < len * 4; i++) {
 533                 struct vgic_irq *irq;
 534
 535                 /*
 536                  * The configuration cannot be changed for SGIs in general,
 537                  * for PPIs this is IMPLEMENTATION DEFINED. The arch timer
 538                  * code relies on PPIs being level triggered, so we also
 539                  * make them read-only here.
 540                  */
 541                 if (intid + i < VGIC_NR_PRIVATE_IRQS)
 542                         continue;
 543
 544                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 545                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 546
 547                 if (test_bit(i * 2 + 1, &val))
 548                         irq->config = VGIC_CONFIG_EDGE;
 549                 else
 550                         irq->config = VGIC_CONFIG_LEVEL;
 551
 552                 raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 553                 vgic_put_irq(vcpu->kvm, irq);
 554         }
 555 }
 556
 557 u64 vgic_read_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid)
 558 {
 559         int i;
 560         u64 val = 0;
 561         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 562
 563         for (i = 0; i < 32; i++) {
 564                 struct vgic_irq *irq;
 565
 566                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 567                         continue;
 568
 569                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 570                 if (irq->config == VGIC_CONFIG_LEVEL && irq->line_level)
 571                         val |= (1U << i);
 572
 573                 vgic_put_irq(vcpu->kvm, irq);
 574         }
 575
 576         return val;
 577 }
 578
 579 void vgic_write_irq_line_level_info(struct kvm_vcpu *vcpu, u32 intid,
 580                                     const u64 val)
 581 {
 582         int i;
 583         int nr_irqs = vcpu->kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 584         unsigned long flags;
 585
 586         for (i = 0; i < 32; i++) {
 587                 struct vgic_irq *irq;
 588                 bool new_level;
 589
 590                 if ((intid + i) < VGIC_NR_SGIS || (intid + i) >= nr_irqs)
 591                         continue;
 592
 593                 irq = vgic_get_irq(vcpu->kvm, vcpu, intid + i);
 594
 595                 /*
 596                  * Line level is set irrespective of irq type
 597                  * (level or edge) to avoid dependency that VM should
 598                  * restore irq config before line level.
 599                  */
 600                 new_level = !!(val & (1U << i));
 601                 raw_spin_lock_irqsave(&irq->irq_lock, flags);
 602                 irq->line_level = new_level;
 603                 if (new_level)
 604                         vgic_queue_irq_unlock(vcpu->kvm, irq, flags);
 605                 else
 606                         raw_spin_unlock_irqrestore(&irq->irq_lock, flags);
 607
 608                 vgic_put_irq(vcpu->kvm, irq);
 609         }
 610 }
 611
 612 static int match_region(const void *key, const void *elt)
 613 {
 614         const unsigned int offset = (unsigned long)key;
 615         const struct vgic_register_region *region = elt;
 616
 617         if (offset < region->reg_offset)
 618                 return -1;
 619
 620         if (offset >= region->reg_offset + region->len)
 621                 return 1;
 622
 623         return 0;
 624 }
 625
 626 const struct vgic_register_region *
 627 vgic_find_mmio_region(const struct vgic_register_region *regions,
 628                       int nr_regions, unsigned int offset)
 629 {
 630         return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
 631                        sizeof(regions[0]), match_region);
 632 }
 633
 634 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 635 {
 636         if (kvm_vgic_global_state.type == VGIC_V2)
 637                 vgic_v2_set_vmcr(vcpu, vmcr);
 638         else
 639                 vgic_v3_set_vmcr(vcpu, vmcr);
 640 }
 641
 642 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
 643 {
 644         if (kvm_vgic_global_state.type == VGIC_V2)
 645                 vgic_v2_get_vmcr(vcpu, vmcr);
 646         else
 647                 vgic_v3_get_vmcr(vcpu, vmcr);
 648 }
 649
 650 /*
 651  * kvm_mmio_read_buf() returns a value in a format where it can be converted
 652  * to a byte array and be directly observed as the guest wanted it to appear
 653  * in memory if it had done the store itself, which is LE for the GIC, as the
 654  * guest knows the GIC is always LE.
 655  *
 656  * We convert this value to the CPUs native format to deal with it as a data
 657  * value.
 658  */
 659 unsigned long vgic_data_mmio_bus_to_host(const void *val, unsigned int len)
 660 {
 661         unsigned long data = kvm_mmio_read_buf(val, len);
 662
 663         switch (len) {
 664         case 1:
 665                 return data;
 666         case 2:
 667                 return le16_to_cpu(data);
 668         case 4:
 669                 return le32_to_cpu(data);
 670         default:
 671                 return le64_to_cpu(data);
 672         }
 673 }
 674
 675 /*
 676  * kvm_mmio_write_buf() expects a value in a format such that if converted to
 677  * a byte array it is observed as the guest would see it if it could perform
 678  * the load directly.  Since the GIC is LE, and the guest knows this, the
 679  * guest expects a value in little endian format.
 680  *
 681  * We convert the data value from the CPUs native format to LE so that the
 682  * value is returned in the proper format.
 683  */
 684 void vgic_data_host_to_mmio_bus(void *buf, unsigned int len,
 685                                 unsigned long data)
 686 {
 687         switch (len) {
 688         case 1:
 689                 break;
 690         case 2:
 691                 data = cpu_to_le16(data);
 692                 break;
 693         case 4:
 694                 data = cpu_to_le32(data);
 695                 break;
 696         default:
 697                 data = cpu_to_le64(data);
 698         }
 699
 700         kvm_mmio_write_buf(buf, len, data);
 701 }
 702
 703 static
 704 struct vgic_io_device *kvm_to_vgic_iodev(const struct kvm_io_device *dev)
 705 {
 706         return container_of(dev, struct vgic_io_device, dev);
 707 }
 708
 709 static bool check_region(const struct kvm *kvm,
 710                          const struct vgic_register_region *region,
 711                          gpa_t addr, int len)
 712 {
 713         int flags, nr_irqs = kvm->arch.vgic.nr_spis + VGIC_NR_PRIVATE_IRQS;
 714
 715         switch (len) {
 716         case sizeof(u8):
 717                 flags = VGIC_ACCESS_8bit;
 718                 break;
 719         case sizeof(u32):
 720                 flags = VGIC_ACCESS_32bit;
 721                 break;
 722         case sizeof(u64):
 723                 flags = VGIC_ACCESS_64bit;
 724                 break;
 725         default:
 726                 return false;
 727         }
 728
 729         if ((region->access_flags & flags) && IS_ALIGNED(addr, len)) {
 730                 if (!region->bits_per_irq)
 731                         return true;
 732
 733                 /* Do we access a non-allocated IRQ? */
 734                 return VGIC_ADDR_TO_INTID(addr, region->bits_per_irq) < nr_irqs;
 735         }
 736
 737         return false;
 738 }
 739
 740 const struct vgic_register_region *
 741 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 742                      gpa_t addr, int len)
 743 {
 744         const struct vgic_register_region *region;
 745
 746         region = vgic_find_mmio_region(iodev->regions, iodev->nr_regions,
 747                                        addr - iodev->base_addr);
 748         if (!region || !check_region(vcpu->kvm, region, addr, len))
 749                 return NULL;
 750
 751         return region;
 752 }
 753
 754 static int vgic_uaccess_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 755                              gpa_t addr, u32 *val)
 756 {
 757         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 758         const struct vgic_register_region *region;
 759         struct kvm_vcpu *r_vcpu;
 760
 761         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 762         if (!region) {
 763                 *val = 0;
 764                 return 0;
 765         }
 766
 767         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 768         if (region->uaccess_read)
 769                 *val = region->uaccess_read(r_vcpu, addr, sizeof(u32));
 770         else
 771                 *val = region->read(r_vcpu, addr, sizeof(u32));
 772
 773         return 0;
 774 }
 775
 776 static int vgic_uaccess_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 777                               gpa_t addr, const u32 *val)
 778 {
 779         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 780         const struct vgic_register_region *region;
 781         struct kvm_vcpu *r_vcpu;
 782
 783         region = vgic_get_mmio_region(vcpu, iodev, addr, sizeof(u32));
 784         if (!region)
 785                 return 0;
 786
 787         r_vcpu = iodev->redist_vcpu ? iodev->redist_vcpu : vcpu;
 788         if (region->uaccess_write)
 789                 return region->uaccess_write(r_vcpu, addr, sizeof(u32), *val);
 790
 791         region->write(r_vcpu, addr, sizeof(u32), *val);
 792         return 0;
 793 }
 794
 795 /*
 796  * Userland access to VGIC registers.
 797  */
 798 int vgic_uaccess(struct kvm_vcpu *vcpu, struct vgic_io_device *dev,
 799                  bool is_write, int offset, u32 *val)
 800 {
 801         if (is_write)
 802                 return vgic_uaccess_write(vcpu, &dev->dev, offset, val);
 803         else
 804                 return vgic_uaccess_read(vcpu, &dev->dev, offset, val);
 805 }
 806
 807 static int dispatch_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 808                               gpa_t addr, int len, void *val)
 809 {
 810         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 811         const struct vgic_register_region *region;
 812         unsigned long data = 0;
 813
 814         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 815         if (!region) {
 816                 memset(val, 0, len);
 817                 return 0;
 818         }
 819
 820         switch (iodev->iodev_type) {
 821         case IODEV_CPUIF:
 822                 data = region->read(vcpu, addr, len);
 823                 break;
 824         case IODEV_DIST:
 825                 data = region->read(vcpu, addr, len);
 826                 break;
 827         case IODEV_REDIST:
 828                 data = region->read(iodev->redist_vcpu, addr, len);
 829                 break;
 830         case IODEV_ITS:
 831                 data = region->its_read(vcpu->kvm, iodev->its, addr, len);
 832                 break;
 833         }
 834
 835         vgic_data_host_to_mmio_bus(val, len, data);
 836         return 0;
 837 }
 838
 839 static int dispatch_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *dev,
 840                                gpa_t addr, int len, const void *val)
 841 {
 842         struct vgic_io_device *iodev = kvm_to_vgic_iodev(dev);
 843         const struct vgic_register_region *region;
 844         unsigned long data = vgic_data_mmio_bus_to_host(val, len);
 845
 846         region = vgic_get_mmio_region(vcpu, iodev, addr, len);
 847         if (!region)
 848                 return 0;
 849
 850         switch (iodev->iodev_type) {
 851         case IODEV_CPUIF:
 852                 region->write(vcpu, addr, len, data);
 853                 break;
 854         case IODEV_DIST:
 855                 region->write(vcpu, addr, len, data);
 856                 break;
 857         case IODEV_REDIST:
 858                 region->write(iodev->redist_vcpu, addr, len, data);
 859                 break;
 860         case IODEV_ITS:
 861                 region->its_write(vcpu->kvm, iodev->its, addr, len, data);
 862                 break;
 863         }
 864
 865         return 0;
 866 }
 867
 868 struct kvm_io_device_ops kvm_io_gic_ops = {
 869         .read = dispatch_mmio_read,
 870         .write = dispatch_mmio_write,
 871 };
 872
 873 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 874                              enum vgic_type type)
 875 {
 876         struct vgic_io_device *io_device = &kvm->arch.vgic.dist_iodev;
 877         int ret = 0;
 878         unsigned int len;
 879
 880         switch (type) {
 881         case VGIC_V2:
 882                 len = vgic_v2_init_dist_iodev(io_device);
 883                 break;
 884         case VGIC_V3:
 885                 len = vgic_v3_init_dist_iodev(io_device);
 886                 break;
 887         default:
 888                 BUG_ON(1);
 889         }
 890
 891         io_device->base_addr = dist_base_address;
 892         io_device->iodev_type = IODEV_DIST;
 893         io_device->redist_vcpu = NULL;
 894
 895         mutex_lock(&kvm->slots_lock);
 896         ret = kvm_io_bus_register_dev(kvm, KVM_MMIO_BUS, dist_base_address,
 897                                       len, &io_device->dev);
 898         mutex_unlock(&kvm->slots_lock);
 899
 900         return ret;
 901 }