tools/testing/selftests/kvm/x86_64/amx_test.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * amx tests
   4  *
   5  * Copyright (C) 2021, Intel, Inc.
   6  *
   7  * Tests for amx #NM exception and save/restore.
   8  */
   9
  10 #define _GNU_SOURCE /* for program_invocation_short_name */
  11 #include <fcntl.h>
  12 #include <stdio.h>
  13 #include <stdlib.h>
  14 #include <string.h>
  15 #include <sys/ioctl.h>
  16 #include <sys/syscall.h>
  17
  18 #include "test_util.h"
  19
  20 #include "kvm_util.h"
  21 #include "processor.h"
  22 #include "vmx.h"
  23
  24 #ifndef __x86_64__
  25 # error This test is 64-bit only
  26 #endif
  27
  28 #define NUM_TILES                       8
  29 #define TILE_SIZE                       1024
  30 #define XSAVE_SIZE                      ((NUM_TILES * TILE_SIZE) + PAGE_SIZE)
  31
  32 /* Tile configuration associated: */
  33 #define PALETTE_TABLE_INDEX             1
  34 #define MAX_TILES                       16
  35 #define RESERVED_BYTES                  14
  36
  37 #define XFEATURE_XTILECFG               17
  38 #define XFEATURE_XTILEDATA              18
  39 #define XFEATURE_MASK_XTILECFG          (1 << XFEATURE_XTILECFG)
  40 #define XFEATURE_MASK_XTILEDATA         (1 << XFEATURE_XTILEDATA)
  41 #define XFEATURE_MASK_XTILE             (XFEATURE_MASK_XTILECFG | XFEATURE_MASK_XTILEDATA)
  42
  43 #define XSAVE_HDR_OFFSET                512
  44
  45 struct tile_config {
  46         u8  palette_id;
  47         u8  start_row;
  48         u8  reserved[RESERVED_BYTES];
  49         u16 colsb[MAX_TILES];
  50         u8  rows[MAX_TILES];
  51 };
  52
  53 struct tile_data {
  54         u8 data[NUM_TILES * TILE_SIZE];
  55 };
  56
  57 struct xtile_info {
  58         u16 bytes_per_tile;
  59         u16 bytes_per_row;
  60         u16 max_names;
  61         u16 max_rows;
  62         u32 xsave_offset;
  63         u32 xsave_size;
  64 };
  65
  66 static struct xtile_info xtile;
  67
  68 static inline void __ldtilecfg(void *cfg)
  69 {
  70         asm volatile(".byte 0xc4,0xe2,0x78,0x49,0x00"
  71                      : : "a"(cfg));
  72 }
  73
  74 static inline void __tileloadd(void *tile)
  75 {
  76         asm volatile(".byte 0xc4,0xe2,0x7b,0x4b,0x04,0x10"
  77                      : : "a"(tile), "d"(0));
  78 }
  79
  80 static inline void __tilerelease(void)
  81 {
  82         asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0" ::);
  83 }
  84
  85 static inline void __xsavec(struct xstate *xstate, uint64_t rfbm)
  86 {
  87         uint32_t rfbm_lo = rfbm;
  88         uint32_t rfbm_hi = rfbm >> 32;
  89
  90         asm volatile("xsavec (%%rdi)"
  91                      : : "D" (xstate), "a" (rfbm_lo), "d" (rfbm_hi)
  92                      : "memory");
  93 }
  94
  95 static void check_xtile_info(void)
  96 {
  97         GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0));
  98         GUEST_ASSERT(this_cpu_property(X86_PROPERTY_XSTATE_MAX_SIZE_XCR0) <= XSAVE_SIZE);
  99
 100         xtile.xsave_offset = this_cpu_property(X86_PROPERTY_XSTATE_TILE_OFFSET);
 101         GUEST_ASSERT(xtile.xsave_offset == 2816);
 102         xtile.xsave_size = this_cpu_property(X86_PROPERTY_XSTATE_TILE_SIZE);
 103         GUEST_ASSERT(xtile.xsave_size == 8192);
 104         GUEST_ASSERT(sizeof(struct tile_data) >= xtile.xsave_size);
 105
 106         GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_AMX_MAX_PALETTE_TABLES));
 107         GUEST_ASSERT(this_cpu_property(X86_PROPERTY_AMX_MAX_PALETTE_TABLES) >=
 108                      PALETTE_TABLE_INDEX);
 109
 110         GUEST_ASSERT(this_cpu_has_p(X86_PROPERTY_AMX_NR_TILE_REGS));
 111         xtile.max_names = this_cpu_property(X86_PROPERTY_AMX_NR_TILE_REGS);
 112         GUEST_ASSERT(xtile.max_names == 8);
 113         xtile.bytes_per_tile = this_cpu_property(X86_PROPERTY_AMX_BYTES_PER_TILE);
 114         GUEST_ASSERT(xtile.bytes_per_tile == 1024);
 115         xtile.bytes_per_row = this_cpu_property(X86_PROPERTY_AMX_BYTES_PER_ROW);
 116         GUEST_ASSERT(xtile.bytes_per_row == 64);
 117         xtile.max_rows = this_cpu_property(X86_PROPERTY_AMX_MAX_ROWS);
 118         GUEST_ASSERT(xtile.max_rows == 16);
 119 }
 120
 121 static void set_tilecfg(struct tile_config *cfg)
 122 {
 123         int i;
 124
 125         /* Only palette id 1 */
 126         cfg->palette_id = 1;
 127         for (i = 0; i < xtile.max_names; i++) {
 128                 cfg->colsb[i] = xtile.bytes_per_row;
 129                 cfg->rows[i] = xtile.max_rows;
 130         }
 131 }
 132
 133 static void init_regs(void)
 134 {
 135         uint64_t cr4, xcr0;
 136
 137         GUEST_ASSERT(this_cpu_has(X86_FEATURE_XSAVE));
 138
 139         /* turn on CR4.OSXSAVE */
 140         cr4 = get_cr4();
 141         cr4 |= X86_CR4_OSXSAVE;
 142         set_cr4(cr4);
 143         GUEST_ASSERT(this_cpu_has(X86_FEATURE_OSXSAVE));
 144
 145         xcr0 = xgetbv(0);
 146         xcr0 |= XFEATURE_MASK_XTILE;
 147         xsetbv(0x0, xcr0);
 148         GUEST_ASSERT((xgetbv(0) & XFEATURE_MASK_XTILE) == XFEATURE_MASK_XTILE);
 149 }
 150
 151 static void __attribute__((__flatten__)) guest_code(struct tile_config *amx_cfg,
 152                                                     struct tile_data *tiledata,
 153                                                     struct xstate *xstate)
 154 {
 155         init_regs();
 156         check_xtile_info();
 157         GUEST_SYNC(1);
 158
 159         /* xfd=0, enable amx */
 160         wrmsr(MSR_IA32_XFD, 0);
 161         GUEST_SYNC(2);
 162         GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == 0);
 163         set_tilecfg(amx_cfg);
 164         __ldtilecfg(amx_cfg);
 165         GUEST_SYNC(3);
 166         /* Check save/restore when trap to userspace */
 167         __tileloadd(tiledata);
 168         GUEST_SYNC(4);
 169         __tilerelease();
 170         GUEST_SYNC(5);
 171         /*
 172          * After XSAVEC, XTILEDATA is cleared in the xstate_bv but is set in
 173          * the xcomp_bv.
 174          */
 175         xstate->header.xstate_bv = XFEATURE_MASK_XTILEDATA;
 176         __xsavec(xstate, XFEATURE_MASK_XTILEDATA);
 177         GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILEDATA));
 178         GUEST_ASSERT(xstate->header.xcomp_bv & XFEATURE_MASK_XTILEDATA);
 179
 180         /* xfd=0x40000, disable amx tiledata */
 181         wrmsr(MSR_IA32_XFD, XFEATURE_MASK_XTILEDATA);
 182
 183         /*
 184          * XTILEDATA is cleared in xstate_bv but set in xcomp_bv, this property
 185          * remains the same even when amx tiledata is disabled by IA32_XFD.
 186          */
 187         xstate->header.xstate_bv = XFEATURE_MASK_XTILEDATA;
 188         __xsavec(xstate, XFEATURE_MASK_XTILEDATA);
 189         GUEST_ASSERT(!(xstate->header.xstate_bv & XFEATURE_MASK_XTILEDATA));
 190         GUEST_ASSERT((xstate->header.xcomp_bv & XFEATURE_MASK_XTILEDATA));
 191
 192         GUEST_SYNC(6);
 193         GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
 194         set_tilecfg(amx_cfg);
 195         __ldtilecfg(amx_cfg);
 196         /* Trigger #NM exception */
 197         __tileloadd(tiledata);
 198         GUEST_SYNC(10);
 199
 200         GUEST_DONE();
 201 }
 202
 203 void guest_nm_handler(struct ex_regs *regs)
 204 {
 205         /* Check if #NM is triggered by XFEATURE_MASK_XTILEDATA */
 206         GUEST_SYNC(7);
 207         GUEST_ASSERT(!(get_cr0() & X86_CR0_TS));
 208         GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
 209         GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
 210         GUEST_SYNC(8);
 211         GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILEDATA);
 212         GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILEDATA);
 213         /* Clear xfd_err */
 214         wrmsr(MSR_IA32_XFD_ERR, 0);
 215         /* xfd=0, enable amx */
 216         wrmsr(MSR_IA32_XFD, 0);
 217         GUEST_SYNC(9);
 218 }
 219
 220 int main(int argc, char *argv[])
 221 {
 222         struct kvm_regs regs1, regs2;
 223         struct kvm_vcpu *vcpu;
 224         struct kvm_vm *vm;
 225         struct kvm_x86_state *state;
 226         int xsave_restore_size;
 227         vm_vaddr_t amx_cfg, tiledata, xstate;
 228         struct ucall uc;
 229         u32 amx_offset;
 230         int stage, ret;
 231
 232         /*
 233          * Note, all off-by-default features must be enabled before anything
 234          * caches KVM_GET_SUPPORTED_CPUID, e.g. before using kvm_cpu_has().
 235          */
 236         vm_xsave_require_permission(XSTATE_XTILE_DATA_BIT);
 237
 238         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XFD));
 239         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XSAVE));
 240         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_AMX_TILE));
 241         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XTILECFG));
 242         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XTILEDATA));
 243         TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_XTILEDATA_XFD));
 244
 245         /* Create VM */
 246         vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 247
 248         TEST_ASSERT(kvm_cpu_has_p(X86_PROPERTY_XSTATE_MAX_SIZE),
 249                     "KVM should enumerate max XSAVE size when XSAVE is supported");
 250         xsave_restore_size = kvm_cpu_property(X86_PROPERTY_XSTATE_MAX_SIZE);
 251
 252         vcpu_regs_get(vcpu, &regs1);
 253
 254         /* Register #NM handler */
 255         vm_init_descriptor_tables(vm);
 256         vcpu_init_descriptor_tables(vcpu);
 257         vm_install_exception_handler(vm, NM_VECTOR, guest_nm_handler);
 258
 259         /* amx cfg for guest_code */
 260         amx_cfg = vm_vaddr_alloc_page(vm);
 261         memset(addr_gva2hva(vm, amx_cfg), 0x0, getpagesize());
 262
 263         /* amx tiledata for guest_code */
 264         tiledata = vm_vaddr_alloc_pages(vm, 2);
 265         memset(addr_gva2hva(vm, tiledata), rand() | 1, 2 * getpagesize());
 266
 267         /* XSAVE state for guest_code */
 268         xstate = vm_vaddr_alloc_pages(vm, DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE));
 269         memset(addr_gva2hva(vm, xstate), 0, PAGE_SIZE * DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE));
 270         vcpu_args_set(vcpu, 3, amx_cfg, tiledata, xstate);
 271
 272         for (stage = 1; ; stage++) {
 273                 vcpu_run(vcpu);
 274                 TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_IO);
 275
 276                 switch (get_ucall(vcpu, &uc)) {
 277                 case UCALL_ABORT:
 278                         REPORT_GUEST_ASSERT(uc);
 279                         /* NOT REACHED */
 280                 case UCALL_SYNC:
 281                         switch (uc.args[1]) {
 282                         case 1:
 283                         case 2:
 284                         case 3:
 285                         case 5:
 286                         case 6:
 287                         case 7:
 288                         case 8:
 289                                 fprintf(stderr, "GUEST_SYNC(%ld)\n", uc.args[1]);
 290                                 break;
 291                         case 4:
 292                         case 10:
 293                                 fprintf(stderr,
 294                                 "GUEST_SYNC(%ld), check save/restore status\n", uc.args[1]);
 295
 296                                 /* Compacted mode, get amx offset by xsave area
 297                                  * size subtract 8K amx size.
 298                                  */
 299                                 amx_offset = xsave_restore_size - NUM_TILES*TILE_SIZE;
 300                                 state = vcpu_save_state(vcpu);
 301                                 void *amx_start = (void *)state->xsave + amx_offset;
 302                                 void *tiles_data = (void *)addr_gva2hva(vm, tiledata);
 303                                 /* Only check TMM0 register, 1 tile */
 304                                 ret = memcmp(amx_start, tiles_data, TILE_SIZE);
 305                                 TEST_ASSERT(ret == 0, "memcmp failed, ret=%d\n", ret);
 306                                 kvm_x86_state_cleanup(state);
 307                                 break;
 308                         case 9:
 309                                 fprintf(stderr,
 310                                 "GUEST_SYNC(%ld), #NM exception and enable amx\n", uc.args[1]);
 311                                 break;
 312                         }
 313                         break;
 314                 case UCALL_DONE:
 315                         fprintf(stderr, "UCALL_DONE\n");
 316                         goto done;
 317                 default:
 318                         TEST_FAIL("Unknown ucall %lu", uc.cmd);
 319                 }
 320
 321                 state = vcpu_save_state(vcpu);
 322                 memset(&regs1, 0, sizeof(regs1));
 323                 vcpu_regs_get(vcpu, &regs1);
 324
 325                 kvm_vm_release(vm);
 326
 327                 /* Restore state in a new VM.  */
 328                 vcpu = vm_recreate_with_one_vcpu(vm);
 329                 vcpu_load_state(vcpu, state);
 330                 kvm_x86_state_cleanup(state);
 331
 332                 memset(&regs2, 0, sizeof(regs2));
 333                 vcpu_regs_get(vcpu, &regs2);
 334                 TEST_ASSERT(!memcmp(&regs1, &regs2, sizeof(regs2)),
 335                             "Unexpected register values after vcpu_load_state; rdi: %lx rsi: %lx",
 336                             (ulong) regs2.rdi, (ulong) regs2.rsi);
 337         }
 338 done:
 339         kvm_vm_free(vm);
 340 }