1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * tools/testing/selftests/kvm/include/x86_64/processor.h
5 * Copyright (C) 2018, Google LLC.
8 #ifndef SELFTEST_KVM_PROCESSOR_H
9 #define SELFTEST_KVM_PROCESSOR_H
15 #include <asm/msr-index.h>
16 #include <asm/prctl.h>
18 #include <linux/kvm_para.h>
19 #include <linux/stringify.h>
21 #include "../kvm_util.h"
23 extern bool host_cpu_is_intel;
24 extern bool host_cpu_is_amd;
26 enum vm_guest_x86_subtype {
32 /* Forced emulation prefix, used to invoke the emulator unconditionally. */
33 #define KVM_FEP "ud2; .byte 'k', 'v', 'm';"
35 #define NMI_VECTOR 0x02
37 #define X86_EFLAGS_FIXED (1u << 1)
39 #define X86_CR4_VME (1ul << 0)
40 #define X86_CR4_PVI (1ul << 1)
41 #define X86_CR4_TSD (1ul << 2)
42 #define X86_CR4_DE (1ul << 3)
43 #define X86_CR4_PSE (1ul << 4)
44 #define X86_CR4_PAE (1ul << 5)
45 #define X86_CR4_MCE (1ul << 6)
46 #define X86_CR4_PGE (1ul << 7)
47 #define X86_CR4_PCE (1ul << 8)
48 #define X86_CR4_OSFXSR (1ul << 9)
49 #define X86_CR4_OSXMMEXCPT (1ul << 10)
50 #define X86_CR4_UMIP (1ul << 11)
51 #define X86_CR4_LA57 (1ul << 12)
52 #define X86_CR4_VMXE (1ul << 13)
53 #define X86_CR4_SMXE (1ul << 14)
54 #define X86_CR4_FSGSBASE (1ul << 16)
55 #define X86_CR4_PCIDE (1ul << 17)
56 #define X86_CR4_OSXSAVE (1ul << 18)
57 #define X86_CR4_SMEP (1ul << 20)
58 #define X86_CR4_SMAP (1ul << 21)
59 #define X86_CR4_PKE (1ul << 22)
61 struct xstate_header {
65 } __attribute__((packed));
69 struct xstate_header header;
70 u8 extended_state_area[0];
71 } __attribute__ ((packed, aligned (64)));
73 #define XFEATURE_MASK_FP BIT_ULL(0)
74 #define XFEATURE_MASK_SSE BIT_ULL(1)
75 #define XFEATURE_MASK_YMM BIT_ULL(2)
76 #define XFEATURE_MASK_BNDREGS BIT_ULL(3)
77 #define XFEATURE_MASK_BNDCSR BIT_ULL(4)
78 #define XFEATURE_MASK_OPMASK BIT_ULL(5)
79 #define XFEATURE_MASK_ZMM_Hi256 BIT_ULL(6)
80 #define XFEATURE_MASK_Hi16_ZMM BIT_ULL(7)
81 #define XFEATURE_MASK_PT BIT_ULL(8)
82 #define XFEATURE_MASK_PKRU BIT_ULL(9)
83 #define XFEATURE_MASK_PASID BIT_ULL(10)
84 #define XFEATURE_MASK_CET_USER BIT_ULL(11)
85 #define XFEATURE_MASK_CET_KERNEL BIT_ULL(12)
86 #define XFEATURE_MASK_LBR BIT_ULL(15)
87 #define XFEATURE_MASK_XTILE_CFG BIT_ULL(17)
88 #define XFEATURE_MASK_XTILE_DATA BIT_ULL(18)
90 #define XFEATURE_MASK_AVX512 (XFEATURE_MASK_OPMASK | \
91 XFEATURE_MASK_ZMM_Hi256 | \
92 XFEATURE_MASK_Hi16_ZMM)
93 #define XFEATURE_MASK_XTILE (XFEATURE_MASK_XTILE_DATA | \
94 XFEATURE_MASK_XTILE_CFG)
96 /* Note, these are ordered alphabetically to match kvm_cpuid_entry2. Eww. */
97 enum cpuid_output_regs {
105 * Pack the information into a 64-bit value so that each X86_FEATURE_XXX can be
106 * passed by value with no overhead.
108 struct kvm_x86_cpu_feature {
114 #define KVM_X86_CPU_FEATURE(fn, idx, gpr, __bit) \
116 struct kvm_x86_cpu_feature feature = { \
119 .reg = KVM_CPUID_##gpr, \
123 kvm_static_assert((fn & 0xc0000000) == 0 || \
124 (fn & 0xc0000000) == 0x40000000 || \
125 (fn & 0xc0000000) == 0x80000000 || \
126 (fn & 0xc0000000) == 0xc0000000); \
127 kvm_static_assert(idx < BIT(sizeof(feature.index) * BITS_PER_BYTE)); \
132 * Basic Leafs, a.k.a. Intel defined
134 #define X86_FEATURE_MWAIT KVM_X86_CPU_FEATURE(0x1, 0, ECX, 3)
135 #define X86_FEATURE_VMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 5)
136 #define X86_FEATURE_SMX KVM_X86_CPU_FEATURE(0x1, 0, ECX, 6)
137 #define X86_FEATURE_PDCM KVM_X86_CPU_FEATURE(0x1, 0, ECX, 15)
138 #define X86_FEATURE_PCID KVM_X86_CPU_FEATURE(0x1, 0, ECX, 17)
139 #define X86_FEATURE_X2APIC KVM_X86_CPU_FEATURE(0x1, 0, ECX, 21)
140 #define X86_FEATURE_MOVBE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 22)
141 #define X86_FEATURE_TSC_DEADLINE_TIMER KVM_X86_CPU_FEATURE(0x1, 0, ECX, 24)
142 #define X86_FEATURE_XSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 26)
143 #define X86_FEATURE_OSXSAVE KVM_X86_CPU_FEATURE(0x1, 0, ECX, 27)
144 #define X86_FEATURE_RDRAND KVM_X86_CPU_FEATURE(0x1, 0, ECX, 30)
145 #define X86_FEATURE_HYPERVISOR KVM_X86_CPU_FEATURE(0x1, 0, ECX, 31)
146 #define X86_FEATURE_PAE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 6)
147 #define X86_FEATURE_MCE KVM_X86_CPU_FEATURE(0x1, 0, EDX, 7)
148 #define X86_FEATURE_APIC KVM_X86_CPU_FEATURE(0x1, 0, EDX, 9)
149 #define X86_FEATURE_CLFLUSH KVM_X86_CPU_FEATURE(0x1, 0, EDX, 19)
150 #define X86_FEATURE_XMM KVM_X86_CPU_FEATURE(0x1, 0, EDX, 25)
151 #define X86_FEATURE_XMM2 KVM_X86_CPU_FEATURE(0x1, 0, EDX, 26)
152 #define X86_FEATURE_FSGSBASE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 0)
153 #define X86_FEATURE_TSC_ADJUST KVM_X86_CPU_FEATURE(0x7, 0, EBX, 1)
154 #define X86_FEATURE_SGX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 2)
155 #define X86_FEATURE_HLE KVM_X86_CPU_FEATURE(0x7, 0, EBX, 4)
156 #define X86_FEATURE_SMEP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 7)
157 #define X86_FEATURE_INVPCID KVM_X86_CPU_FEATURE(0x7, 0, EBX, 10)
158 #define X86_FEATURE_RTM KVM_X86_CPU_FEATURE(0x7, 0, EBX, 11)
159 #define X86_FEATURE_MPX KVM_X86_CPU_FEATURE(0x7, 0, EBX, 14)
160 #define X86_FEATURE_SMAP KVM_X86_CPU_FEATURE(0x7, 0, EBX, 20)
161 #define X86_FEATURE_PCOMMIT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 22)
162 #define X86_FEATURE_CLFLUSHOPT KVM_X86_CPU_FEATURE(0x7, 0, EBX, 23)
163 #define X86_FEATURE_CLWB KVM_X86_CPU_FEATURE(0x7, 0, EBX, 24)
164 #define X86_FEATURE_UMIP KVM_X86_CPU_FEATURE(0x7, 0, ECX, 2)
165 #define X86_FEATURE_PKU KVM_X86_CPU_FEATURE(0x7, 0, ECX, 3)
166 #define X86_FEATURE_OSPKE KVM_X86_CPU_FEATURE(0x7, 0, ECX, 4)
167 #define X86_FEATURE_LA57 KVM_X86_CPU_FEATURE(0x7, 0, ECX, 16)
168 #define X86_FEATURE_RDPID KVM_X86_CPU_FEATURE(0x7, 0, ECX, 22)
169 #define X86_FEATURE_SGX_LC KVM_X86_CPU_FEATURE(0x7, 0, ECX, 30)
170 #define X86_FEATURE_SHSTK KVM_X86_CPU_FEATURE(0x7, 0, ECX, 7)
171 #define X86_FEATURE_IBT KVM_X86_CPU_FEATURE(0x7, 0, EDX, 20)
172 #define X86_FEATURE_AMX_TILE KVM_X86_CPU_FEATURE(0x7, 0, EDX, 24)
173 #define X86_FEATURE_SPEC_CTRL KVM_X86_CPU_FEATURE(0x7, 0, EDX, 26)
174 #define X86_FEATURE_ARCH_CAPABILITIES KVM_X86_CPU_FEATURE(0x7, 0, EDX, 29)
175 #define X86_FEATURE_PKS KVM_X86_CPU_FEATURE(0x7, 0, ECX, 31)
176 #define X86_FEATURE_XTILECFG KVM_X86_CPU_FEATURE(0xD, 0, EAX, 17)
177 #define X86_FEATURE_XTILEDATA KVM_X86_CPU_FEATURE(0xD, 0, EAX, 18)
178 #define X86_FEATURE_XSAVES KVM_X86_CPU_FEATURE(0xD, 1, EAX, 3)
179 #define X86_FEATURE_XFD KVM_X86_CPU_FEATURE(0xD, 1, EAX, 4)
180 #define X86_FEATURE_XTILEDATA_XFD KVM_X86_CPU_FEATURE(0xD, 18, ECX, 2)
183 * Extended Leafs, a.k.a. AMD defined
185 #define X86_FEATURE_SVM KVM_X86_CPU_FEATURE(0x80000001, 0, ECX, 2)
186 #define X86_FEATURE_NX KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 20)
187 #define X86_FEATURE_GBPAGES KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 26)
188 #define X86_FEATURE_RDTSCP KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 27)
189 #define X86_FEATURE_LM KVM_X86_CPU_FEATURE(0x80000001, 0, EDX, 29)
190 #define X86_FEATURE_INVTSC KVM_X86_CPU_FEATURE(0x80000007, 0, EDX, 8)
191 #define X86_FEATURE_RDPRU KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 4)
192 #define X86_FEATURE_AMD_IBPB KVM_X86_CPU_FEATURE(0x80000008, 0, EBX, 12)
193 #define X86_FEATURE_NPT KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 0)
194 #define X86_FEATURE_LBRV KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 1)
195 #define X86_FEATURE_NRIPS KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 3)
196 #define X86_FEATURE_TSCRATEMSR KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 4)
197 #define X86_FEATURE_PAUSEFILTER KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 10)
198 #define X86_FEATURE_PFTHRESHOLD KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 12)
199 #define X86_FEATURE_VGIF KVM_X86_CPU_FEATURE(0x8000000A, 0, EDX, 16)
200 #define X86_FEATURE_SEV KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 1)
201 #define X86_FEATURE_SEV_ES KVM_X86_CPU_FEATURE(0x8000001F, 0, EAX, 3)
204 * KVM defined paravirt features.
206 #define X86_FEATURE_KVM_CLOCKSOURCE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 0)
207 #define X86_FEATURE_KVM_NOP_IO_DELAY KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 1)
208 #define X86_FEATURE_KVM_MMU_OP KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 2)
209 #define X86_FEATURE_KVM_CLOCKSOURCE2 KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 3)
210 #define X86_FEATURE_KVM_ASYNC_PF KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 4)
211 #define X86_FEATURE_KVM_STEAL_TIME KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 5)
212 #define X86_FEATURE_KVM_PV_EOI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 6)
213 #define X86_FEATURE_KVM_PV_UNHALT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 7)
214 /* Bit 8 apparently isn't used?!?! */
215 #define X86_FEATURE_KVM_PV_TLB_FLUSH KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 9)
216 #define X86_FEATURE_KVM_ASYNC_PF_VMEXIT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 10)
217 #define X86_FEATURE_KVM_PV_SEND_IPI KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 11)
218 #define X86_FEATURE_KVM_POLL_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 12)
219 #define X86_FEATURE_KVM_PV_SCHED_YIELD KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 13)
220 #define X86_FEATURE_KVM_ASYNC_PF_INT KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 14)
221 #define X86_FEATURE_KVM_MSI_EXT_DEST_ID KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 15)
222 #define X86_FEATURE_KVM_HC_MAP_GPA_RANGE KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 16)
223 #define X86_FEATURE_KVM_MIGRATION_CONTROL KVM_X86_CPU_FEATURE(0x40000001, 0, EAX, 17)
226 * Same idea as X86_FEATURE_XXX, but X86_PROPERTY_XXX retrieves a multi-bit
227 * value/property as opposed to a single-bit feature. Again, pack the info
228 * into a 64-bit value to pass by value with no overhead.
230 struct kvm_x86_cpu_property {
237 #define KVM_X86_CPU_PROPERTY(fn, idx, gpr, low_bit, high_bit) \
239 struct kvm_x86_cpu_property property = { \
242 .reg = KVM_CPUID_##gpr, \
244 .hi_bit = high_bit, \
247 kvm_static_assert(low_bit < high_bit); \
248 kvm_static_assert((fn & 0xc0000000) == 0 || \
249 (fn & 0xc0000000) == 0x40000000 || \
250 (fn & 0xc0000000) == 0x80000000 || \
251 (fn & 0xc0000000) == 0xc0000000); \
252 kvm_static_assert(idx < BIT(sizeof(property.index) * BITS_PER_BYTE)); \
256 #define X86_PROPERTY_MAX_BASIC_LEAF KVM_X86_CPU_PROPERTY(0, 0, EAX, 0, 31)
257 #define X86_PROPERTY_PMU_VERSION KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 0, 7)
258 #define X86_PROPERTY_PMU_NR_GP_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 8, 15)
259 #define X86_PROPERTY_PMU_GP_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 16, 23)
260 #define X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH KVM_X86_CPU_PROPERTY(0xa, 0, EAX, 24, 31)
261 #define X86_PROPERTY_PMU_EVENTS_MASK KVM_X86_CPU_PROPERTY(0xa, 0, EBX, 0, 7)
262 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BITMASK KVM_X86_CPU_PROPERTY(0xa, 0, ECX, 0, 31)
263 #define X86_PROPERTY_PMU_NR_FIXED_COUNTERS KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 0, 4)
264 #define X86_PROPERTY_PMU_FIXED_COUNTERS_BIT_WIDTH KVM_X86_CPU_PROPERTY(0xa, 0, EDX, 5, 12)
266 #define X86_PROPERTY_SUPPORTED_XCR0_LO KVM_X86_CPU_PROPERTY(0xd, 0, EAX, 0, 31)
267 #define X86_PROPERTY_XSTATE_MAX_SIZE_XCR0 KVM_X86_CPU_PROPERTY(0xd, 0, EBX, 0, 31)
268 #define X86_PROPERTY_XSTATE_MAX_SIZE KVM_X86_CPU_PROPERTY(0xd, 0, ECX, 0, 31)
269 #define X86_PROPERTY_SUPPORTED_XCR0_HI KVM_X86_CPU_PROPERTY(0xd, 0, EDX, 0, 31)
271 #define X86_PROPERTY_XSTATE_TILE_SIZE KVM_X86_CPU_PROPERTY(0xd, 18, EAX, 0, 31)
272 #define X86_PROPERTY_XSTATE_TILE_OFFSET KVM_X86_CPU_PROPERTY(0xd, 18, EBX, 0, 31)
273 #define X86_PROPERTY_AMX_MAX_PALETTE_TABLES KVM_X86_CPU_PROPERTY(0x1d, 0, EAX, 0, 31)
274 #define X86_PROPERTY_AMX_TOTAL_TILE_BYTES KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 0, 15)
275 #define X86_PROPERTY_AMX_BYTES_PER_TILE KVM_X86_CPU_PROPERTY(0x1d, 1, EAX, 16, 31)
276 #define X86_PROPERTY_AMX_BYTES_PER_ROW KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 0, 15)
277 #define X86_PROPERTY_AMX_NR_TILE_REGS KVM_X86_CPU_PROPERTY(0x1d, 1, EBX, 16, 31)
278 #define X86_PROPERTY_AMX_MAX_ROWS KVM_X86_CPU_PROPERTY(0x1d, 1, ECX, 0, 15)
280 #define X86_PROPERTY_MAX_KVM_LEAF KVM_X86_CPU_PROPERTY(0x40000000, 0, EAX, 0, 31)
282 #define X86_PROPERTY_MAX_EXT_LEAF KVM_X86_CPU_PROPERTY(0x80000000, 0, EAX, 0, 31)
283 #define X86_PROPERTY_MAX_PHY_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 0, 7)
284 #define X86_PROPERTY_MAX_VIRT_ADDR KVM_X86_CPU_PROPERTY(0x80000008, 0, EAX, 8, 15)
285 #define X86_PROPERTY_SEV_C_BIT KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 0, 5)
286 #define X86_PROPERTY_PHYS_ADDR_REDUCTION KVM_X86_CPU_PROPERTY(0x8000001F, 0, EBX, 6, 11)
288 #define X86_PROPERTY_MAX_CENTAUR_LEAF KVM_X86_CPU_PROPERTY(0xC0000000, 0, EAX, 0, 31)
291 * Intel's architectural PMU events are bizarre. They have a "feature" bit
292 * that indicates the feature is _not_ supported, and a property that states
293 * the length of the bit mask of unsupported features. A feature is supported
294 * if the size of the bit mask is larger than the "unavailable" bit, and said
295 * bit is not set. Fixed counters also bizarre enumeration, but inverted from
296 * arch events for general purpose counters. Fixed counters are supported if a
297 * feature flag is set **OR** the total number of fixed counters is greater
298 * than index of the counter.
300 * Wrap the events for general purpose and fixed counters to simplify checking
301 * whether or not a given architectural event is supported.
303 struct kvm_x86_pmu_feature {
304 struct kvm_x86_cpu_feature f;
306 #define KVM_X86_PMU_FEATURE(__reg, __bit) \
308 struct kvm_x86_pmu_feature feature = { \
309 .f = KVM_X86_CPU_FEATURE(0xa, 0, __reg, __bit), \
312 kvm_static_assert(KVM_CPUID_##__reg == KVM_CPUID_EBX || \
313 KVM_CPUID_##__reg == KVM_CPUID_ECX); \
317 #define X86_PMU_FEATURE_CPU_CYCLES KVM_X86_PMU_FEATURE(EBX, 0)
318 #define X86_PMU_FEATURE_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 1)
319 #define X86_PMU_FEATURE_REFERENCE_CYCLES KVM_X86_PMU_FEATURE(EBX, 2)
320 #define X86_PMU_FEATURE_LLC_REFERENCES KVM_X86_PMU_FEATURE(EBX, 3)
321 #define X86_PMU_FEATURE_LLC_MISSES KVM_X86_PMU_FEATURE(EBX, 4)
322 #define X86_PMU_FEATURE_BRANCH_INSNS_RETIRED KVM_X86_PMU_FEATURE(EBX, 5)
323 #define X86_PMU_FEATURE_BRANCHES_MISPREDICTED KVM_X86_PMU_FEATURE(EBX, 6)
324 #define X86_PMU_FEATURE_TOPDOWN_SLOTS KVM_X86_PMU_FEATURE(EBX, 7)
326 #define X86_PMU_FEATURE_INSNS_RETIRED_FIXED KVM_X86_PMU_FEATURE(ECX, 0)
327 #define X86_PMU_FEATURE_CPU_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 1)
328 #define X86_PMU_FEATURE_REFERENCE_TSC_CYCLES_FIXED KVM_X86_PMU_FEATURE(ECX, 2)
329 #define X86_PMU_FEATURE_TOPDOWN_SLOTS_FIXED KVM_X86_PMU_FEATURE(ECX, 3)
331 static inline unsigned int x86_family(unsigned int eax)
335 x86 = (eax >> 8) & 0xf;
338 x86 += (eax >> 20) & 0xff;
343 static inline unsigned int x86_model(unsigned int eax)
345 return ((eax >> 12) & 0xf0) | ((eax >> 4) & 0x0f);
348 /* Page table bitfield declarations */
349 #define PTE_PRESENT_MASK BIT_ULL(0)
350 #define PTE_WRITABLE_MASK BIT_ULL(1)
351 #define PTE_USER_MASK BIT_ULL(2)
352 #define PTE_ACCESSED_MASK BIT_ULL(5)
353 #define PTE_DIRTY_MASK BIT_ULL(6)
354 #define PTE_LARGE_MASK BIT_ULL(7)
355 #define PTE_GLOBAL_MASK BIT_ULL(8)
356 #define PTE_NX_MASK BIT_ULL(63)
358 #define PHYSICAL_PAGE_MASK GENMASK_ULL(51, 12)
360 #define PAGE_SHIFT 12
361 #define PAGE_SIZE (1ULL << PAGE_SHIFT)
362 #define PAGE_MASK (~(PAGE_SIZE-1) & PHYSICAL_PAGE_MASK)
364 #define HUGEPAGE_SHIFT(x) (PAGE_SHIFT + (((x) - 1) * 9))
365 #define HUGEPAGE_SIZE(x) (1UL << HUGEPAGE_SHIFT(x))
366 #define HUGEPAGE_MASK(x) (~(HUGEPAGE_SIZE(x) - 1) & PHYSICAL_PAGE_MASK)
368 #define PTE_GET_PA(pte) ((pte) & PHYSICAL_PAGE_MASK)
369 #define PTE_GET_PFN(pte) (PTE_GET_PA(pte) >> PAGE_SHIFT)
371 /* General Registers in 64-Bit Mode */
394 unsigned base1:8, type:4, s:1, dpl:2, p:1;
395 unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
398 } __attribute__((packed));
403 } __attribute__((packed));
405 struct kvm_x86_state {
406 struct kvm_xsave *xsave;
407 struct kvm_vcpu_events events;
408 struct kvm_mp_state mp_state;
409 struct kvm_regs regs;
410 struct kvm_xcrs xcrs;
411 struct kvm_sregs sregs;
412 struct kvm_debugregs debugregs;
414 struct kvm_nested_state nested;
417 struct kvm_msrs msrs;
420 static inline uint64_t get_desc64_base(const struct desc64 *desc)
422 return ((uint64_t)desc->base3 << 32) |
423 (desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
426 static inline uint64_t rdtsc(void)
431 * The lfence is to wait (on Intel CPUs) until all previous
432 * instructions have been executed. If software requires RDTSC to be
433 * executed prior to execution of any subsequent instruction, it can
434 * execute LFENCE immediately after RDTSC
436 __asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
437 tsc_val = ((uint64_t)edx) << 32 | eax;
441 static inline uint64_t rdtscp(uint32_t *aux)
445 __asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
446 return ((uint64_t)edx) << 32 | eax;
449 static inline uint64_t rdmsr(uint32_t msr)
453 __asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
455 return a | ((uint64_t) d << 32);
458 static inline void wrmsr(uint32_t msr, uint64_t value)
461 uint32_t d = value >> 32;
463 __asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
467 static inline uint16_t inw(uint16_t port)
471 __asm__ __volatile__("in %%dx, %%ax"
472 : /* output */ "=a" (tmp)
473 : /* input */ "d" (port));
478 static inline uint16_t get_es(void)
482 __asm__ __volatile__("mov %%es, %[es]"
483 : /* output */ [es]"=rm"(es));
487 static inline uint16_t get_cs(void)
491 __asm__ __volatile__("mov %%cs, %[cs]"
492 : /* output */ [cs]"=rm"(cs));
496 static inline uint16_t get_ss(void)
500 __asm__ __volatile__("mov %%ss, %[ss]"
501 : /* output */ [ss]"=rm"(ss));
505 static inline uint16_t get_ds(void)
509 __asm__ __volatile__("mov %%ds, %[ds]"
510 : /* output */ [ds]"=rm"(ds));
514 static inline uint16_t get_fs(void)
518 __asm__ __volatile__("mov %%fs, %[fs]"
519 : /* output */ [fs]"=rm"(fs));
523 static inline uint16_t get_gs(void)
527 __asm__ __volatile__("mov %%gs, %[gs]"
528 : /* output */ [gs]"=rm"(gs));
532 static inline uint16_t get_tr(void)
536 __asm__ __volatile__("str %[tr]"
537 : /* output */ [tr]"=rm"(tr));
541 static inline uint64_t get_cr0(void)
545 __asm__ __volatile__("mov %%cr0, %[cr0]"
546 : /* output */ [cr0]"=r"(cr0));
550 static inline uint64_t get_cr3(void)
554 __asm__ __volatile__("mov %%cr3, %[cr3]"
555 : /* output */ [cr3]"=r"(cr3));
559 static inline uint64_t get_cr4(void)
563 __asm__ __volatile__("mov %%cr4, %[cr4]"
564 : /* output */ [cr4]"=r"(cr4));
568 static inline void set_cr4(uint64_t val)
570 __asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
573 static inline u64 xgetbv(u32 index)
577 __asm__ __volatile__("xgetbv;"
578 : "=a" (eax), "=d" (edx)
580 return eax | ((u64)edx << 32);
583 static inline void xsetbv(u32 index, u64 value)
586 u32 edx = value >> 32;
588 __asm__ __volatile__("xsetbv" :: "a" (eax), "d" (edx), "c" (index));
591 static inline void wrpkru(u32 pkru)
593 /* Note, ECX and EDX are architecturally required to be '0'. */
594 asm volatile(".byte 0x0f,0x01,0xef\n\t"
595 : : "a" (pkru), "c"(0), "d"(0));
598 static inline struct desc_ptr get_gdt(void)
601 __asm__ __volatile__("sgdt %[gdt]"
602 : /* output */ [gdt]"=m"(gdt));
606 static inline struct desc_ptr get_idt(void)
609 __asm__ __volatile__("sidt %[idt]"
610 : /* output */ [idt]"=m"(idt));
614 static inline void outl(uint16_t port, uint32_t value)
616 __asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
619 static inline void __cpuid(uint32_t function, uint32_t index,
620 uint32_t *eax, uint32_t *ebx,
621 uint32_t *ecx, uint32_t *edx)
631 : "0" (*eax), "2" (*ecx)
635 static inline void cpuid(uint32_t function,
636 uint32_t *eax, uint32_t *ebx,
637 uint32_t *ecx, uint32_t *edx)
639 return __cpuid(function, 0, eax, ebx, ecx, edx);
642 static inline uint32_t this_cpu_fms(void)
644 uint32_t eax, ebx, ecx, edx;
646 cpuid(1, &eax, &ebx, &ecx, &edx);
650 static inline uint32_t this_cpu_family(void)
652 return x86_family(this_cpu_fms());
655 static inline uint32_t this_cpu_model(void)
657 return x86_model(this_cpu_fms());
660 static inline bool this_cpu_vendor_string_is(const char *vendor)
662 const uint32_t *chunk = (const uint32_t *)vendor;
663 uint32_t eax, ebx, ecx, edx;
665 cpuid(0, &eax, &ebx, &ecx, &edx);
666 return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]);
669 static inline bool this_cpu_is_intel(void)
671 return this_cpu_vendor_string_is("GenuineIntel");
675 * Exclude early K5 samples with a vendor string of "AMDisbetter!"
677 static inline bool this_cpu_is_amd(void)
679 return this_cpu_vendor_string_is("AuthenticAMD");
682 static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index,
683 uint8_t reg, uint8_t lo, uint8_t hi)
687 __cpuid(function, index,
688 &gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX],
689 &gprs[KVM_CPUID_ECX], &gprs[KVM_CPUID_EDX]);
691 return (gprs[reg] & GENMASK(hi, lo)) >> lo;
694 static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature)
696 return __this_cpu_has(feature.function, feature.index,
697 feature.reg, feature.bit, feature.bit);
700 static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property)
702 return __this_cpu_has(property.function, property.index,
703 property.reg, property.lo_bit, property.hi_bit);
706 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property)
710 switch (property.function & 0xc0000000) {
712 max_leaf = this_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
715 max_leaf = this_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
718 max_leaf = this_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
721 max_leaf = this_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
723 return max_leaf >= property.function;
726 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature)
730 if (feature.f.reg == KVM_CPUID_EBX) {
731 nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
732 return nr_bits > feature.f.bit && !this_cpu_has(feature.f);
735 GUEST_ASSERT(feature.f.reg == KVM_CPUID_ECX);
736 nr_bits = this_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
737 return nr_bits > feature.f.bit || this_cpu_has(feature.f);
740 static __always_inline uint64_t this_cpu_supported_xcr0(void)
742 if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
745 return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
746 ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
749 typedef u32 __attribute__((vector_size(16))) sse128_t;
750 #define __sse128_u union { sse128_t vec; u64 as_u64[2]; u32 as_u32[4]; }
751 #define sse128_lo(x) ({ __sse128_u t; t.vec = x; t.as_u64[0]; })
752 #define sse128_hi(x) ({ __sse128_u t; t.vec = x; t.as_u64[1]; })
754 static inline void read_sse_reg(int reg, sse128_t *data)
758 asm("movdqa %%xmm0, %0" : "=m"(*data));
761 asm("movdqa %%xmm1, %0" : "=m"(*data));
764 asm("movdqa %%xmm2, %0" : "=m"(*data));
767 asm("movdqa %%xmm3, %0" : "=m"(*data));
770 asm("movdqa %%xmm4, %0" : "=m"(*data));
773 asm("movdqa %%xmm5, %0" : "=m"(*data));
776 asm("movdqa %%xmm6, %0" : "=m"(*data));
779 asm("movdqa %%xmm7, %0" : "=m"(*data));
786 static inline void write_sse_reg(int reg, const sse128_t *data)
790 asm("movdqa %0, %%xmm0" : : "m"(*data));
793 asm("movdqa %0, %%xmm1" : : "m"(*data));
796 asm("movdqa %0, %%xmm2" : : "m"(*data));
799 asm("movdqa %0, %%xmm3" : : "m"(*data));
802 asm("movdqa %0, %%xmm4" : : "m"(*data));
805 asm("movdqa %0, %%xmm5" : : "m"(*data));
808 asm("movdqa %0, %%xmm6" : : "m"(*data));
811 asm("movdqa %0, %%xmm7" : : "m"(*data));
818 static inline void cpu_relax(void)
820 asm volatile("rep; nop" ::: "memory");
824 __asm__ __volatile__( \
829 __asm__ __volatile__( \
833 struct kvm_x86_state *vcpu_save_state(struct kvm_vcpu *vcpu);
834 void vcpu_load_state(struct kvm_vcpu *vcpu, struct kvm_x86_state *state);
835 void kvm_x86_state_cleanup(struct kvm_x86_state *state);
837 const struct kvm_msr_list *kvm_get_msr_index_list(void);
838 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void);
839 bool kvm_msr_is_in_save_restore_list(uint32_t msr_index);
840 uint64_t kvm_get_feature_msr(uint64_t msr_index);
842 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu,
843 struct kvm_msrs *msrs)
845 int r = __vcpu_ioctl(vcpu, KVM_GET_MSRS, msrs);
847 TEST_ASSERT(r == msrs->nmsrs,
848 "KVM_GET_MSRS failed, r: %i (failed on MSR %x)",
849 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index);
851 static inline void vcpu_msrs_set(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs)
853 int r = __vcpu_ioctl(vcpu, KVM_SET_MSRS, msrs);
855 TEST_ASSERT(r == msrs->nmsrs,
856 "KVM_SET_MSRS failed, r: %i (failed on MSR %x)",
857 r, r < 0 || r >= msrs->nmsrs ? -1 : msrs->entries[r].index);
859 static inline void vcpu_debugregs_get(struct kvm_vcpu *vcpu,
860 struct kvm_debugregs *debugregs)
862 vcpu_ioctl(vcpu, KVM_GET_DEBUGREGS, debugregs);
864 static inline void vcpu_debugregs_set(struct kvm_vcpu *vcpu,
865 struct kvm_debugregs *debugregs)
867 vcpu_ioctl(vcpu, KVM_SET_DEBUGREGS, debugregs);
869 static inline void vcpu_xsave_get(struct kvm_vcpu *vcpu,
870 struct kvm_xsave *xsave)
872 vcpu_ioctl(vcpu, KVM_GET_XSAVE, xsave);
874 static inline void vcpu_xsave2_get(struct kvm_vcpu *vcpu,
875 struct kvm_xsave *xsave)
877 vcpu_ioctl(vcpu, KVM_GET_XSAVE2, xsave);
879 static inline void vcpu_xsave_set(struct kvm_vcpu *vcpu,
880 struct kvm_xsave *xsave)
882 vcpu_ioctl(vcpu, KVM_SET_XSAVE, xsave);
884 static inline void vcpu_xcrs_get(struct kvm_vcpu *vcpu,
885 struct kvm_xcrs *xcrs)
887 vcpu_ioctl(vcpu, KVM_GET_XCRS, xcrs);
889 static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs)
891 vcpu_ioctl(vcpu, KVM_SET_XCRS, xcrs);
894 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
895 uint32_t function, uint32_t index);
896 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
897 const struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
898 const struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vcpu *vcpu);
900 static inline uint32_t kvm_cpu_fms(void)
902 return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax;
905 static inline uint32_t kvm_cpu_family(void)
907 return x86_family(kvm_cpu_fms());
910 static inline uint32_t kvm_cpu_model(void)
912 return x86_model(kvm_cpu_fms());
915 bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid,
916 struct kvm_x86_cpu_feature feature);
918 static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature)
920 return kvm_cpuid_has(kvm_get_supported_cpuid(), feature);
923 uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
924 struct kvm_x86_cpu_property property);
926 static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property)
928 return kvm_cpuid_property(kvm_get_supported_cpuid(), property);
931 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property)
935 switch (property.function & 0xc0000000) {
937 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_BASIC_LEAF);
940 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_KVM_LEAF);
943 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_EXT_LEAF);
946 max_leaf = kvm_cpu_property(X86_PROPERTY_MAX_CENTAUR_LEAF);
948 return max_leaf >= property.function;
951 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature)
955 if (feature.f.reg == KVM_CPUID_EBX) {
956 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
957 return nr_bits > feature.f.bit && !kvm_cpu_has(feature.f);
960 TEST_ASSERT_EQ(feature.f.reg, KVM_CPUID_ECX);
961 nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
962 return nr_bits > feature.f.bit || kvm_cpu_has(feature.f);
965 static __always_inline uint64_t kvm_cpu_supported_xcr0(void)
967 if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
970 return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
971 ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
974 static inline size_t kvm_cpuid2_size(int nr_entries)
976 return sizeof(struct kvm_cpuid2) +
977 sizeof(struct kvm_cpuid_entry2) * nr_entries;
981 * Allocate a "struct kvm_cpuid2* instance, with the 0-length arrary of
982 * entries sized to hold @nr_entries. The caller is responsible for freeing
985 static inline struct kvm_cpuid2 *allocate_kvm_cpuid2(int nr_entries)
987 struct kvm_cpuid2 *cpuid;
989 cpuid = malloc(kvm_cpuid2_size(nr_entries));
990 TEST_ASSERT(cpuid, "-ENOMEM when allocating kvm_cpuid2");
992 cpuid->nent = nr_entries;
997 void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid);
998 void vcpu_set_hv_cpuid(struct kvm_vcpu *vcpu);
1000 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
1004 return (struct kvm_cpuid_entry2 *)get_cpuid_entry(vcpu->cpuid,
1008 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
1011 return __vcpu_get_cpuid_entry(vcpu, function, 0);
1014 static inline int __vcpu_set_cpuid(struct kvm_vcpu *vcpu)
1018 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first");
1019 r = __vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid);
1023 /* On success, refresh the cache to pick up adjustments made by KVM. */
1024 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid);
1028 static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu)
1030 TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first");
1031 vcpu_ioctl(vcpu, KVM_SET_CPUID2, vcpu->cpuid);
1033 /* Refresh the cache to pick up adjustments made by KVM. */
1034 vcpu_ioctl(vcpu, KVM_GET_CPUID2, vcpu->cpuid);
1037 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu,
1038 struct kvm_x86_cpu_property property,
1041 void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function);
1042 void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu,
1043 struct kvm_x86_cpu_feature feature,
1046 static inline void vcpu_set_cpuid_feature(struct kvm_vcpu *vcpu,
1047 struct kvm_x86_cpu_feature feature)
1049 vcpu_set_or_clear_cpuid_feature(vcpu, feature, true);
1053 static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu,
1054 struct kvm_x86_cpu_feature feature)
1056 vcpu_set_or_clear_cpuid_feature(vcpu, feature, false);
1059 uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index);
1060 int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value);
1063 * Assert on an MSR access(es) and pretty print the MSR name when possible.
1064 * Note, the caller provides the stringified name so that the name of macro is
1065 * printed, not the value the macro resolves to (due to macro expansion).
1067 #define TEST_ASSERT_MSR(cond, fmt, msr, str, args...) \
1069 if (__builtin_constant_p(msr)) { \
1070 TEST_ASSERT(cond, fmt, str, args); \
1071 } else if (!(cond)) { \
1074 snprintf(buf, sizeof(buf), "MSR 0x%x", msr); \
1075 TEST_ASSERT(cond, fmt, buf, args); \
1080 * Returns true if KVM should return the last written value when reading an MSR
1081 * from userspace, e.g. the MSR isn't a command MSR, doesn't emulate state that
1082 * is changing, etc. This is NOT an exhaustive list! The intent is to filter
1083 * out MSRs that are not durable _and_ that a selftest wants to write.
1085 static inline bool is_durable_msr(uint32_t msr)
1087 return msr != MSR_IA32_TSC;
1090 #define vcpu_set_msr(vcpu, msr, val) \
1092 uint64_t r, v = val; \
1094 TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1, \
1095 "KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v); \
1096 if (!is_durable_msr(msr)) \
1098 r = vcpu_get_msr(vcpu, msr); \
1099 TEST_ASSERT_MSR(r == v, "Set %s to '0x%lx', got back '0x%lx'", msr, #msr, v, r);\
1102 void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
1103 void kvm_init_vm_address_properties(struct kvm_vm *vm);
1104 bool vm_is_unrestricted_guest(struct kvm_vm *vm);
1107 uint64_t rax, rcx, rdx, rbx;
1108 uint64_t rbp, rsi, rdi;
1109 uint64_t r8, r9, r10, r11;
1110 uint64_t r12, r13, r14, r15;
1112 uint64_t error_code;
1128 uint32_t offset2; uint32_t reserved;
1131 void vm_init_descriptor_tables(struct kvm_vm *vm);
1132 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu);
1133 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
1134 void (*handler)(struct ex_regs *));
1136 /* If a toddler were to say "abracadabra". */
1137 #define KVM_EXCEPTION_MAGIC 0xabacadabaULL
1140 * KVM selftest exception fixup uses registers to coordinate with the exception
1141 * handler, versus the kernel's in-memory tables and KVM-Unit-Tests's in-memory
1142 * per-CPU data. Using only registers avoids having to map memory into the
1143 * guest, doesn't require a valid, stable GS.base, and reduces the risk of
1144 * for recursive faults when accessing memory in the handler. The downside to
1145 * using registers is that it restricts what registers can be used by the actual
1146 * instruction. But, selftests are 64-bit only, making register* pressure a
1147 * minor concern. Use r9-r11 as they are volatile, i.e. don't need to be saved
1148 * by the callee, and except for r11 are not implicit parameters to any
1149 * instructions. Ideally, fixup would use r8-r10 and thus avoid implicit
1150 * parameters entirely, but Hyper-V's hypercall ABI uses r8 and testing Hyper-V
1151 * is higher priority than testing non-faulting SYSCALL/SYSRET.
1153 * Note, the fixup handler deliberately does not handle #DE, i.e. the vector
1154 * is guaranteed to be non-zero on fault.
1159 * r11 = new RIP on fault
1162 * r9 = exception vector (non-zero)
1165 #define __KVM_ASM_SAFE(insn, fep) \
1166 "mov $" __stringify(KVM_EXCEPTION_MAGIC) ", %%r9\n\t" \
1167 "lea 1f(%%rip), %%r10\n\t" \
1168 "lea 2f(%%rip), %%r11\n\t" \
1169 fep "1: " insn "\n\t" \
1170 "xor %%r9, %%r9\n\t" \
1172 "mov %%r9b, %[vector]\n\t" \
1173 "mov %%r10, %[error_code]\n\t"
1175 #define KVM_ASM_SAFE(insn) __KVM_ASM_SAFE(insn, "")
1176 #define KVM_ASM_SAFE_FEP(insn) __KVM_ASM_SAFE(insn, KVM_FEP)
1178 #define KVM_ASM_SAFE_OUTPUTS(v, ec) [vector] "=qm"(v), [error_code] "=rm"(ec)
1179 #define KVM_ASM_SAFE_CLOBBERS "r9", "r10", "r11"
1181 #define kvm_asm_safe(insn, inputs...) \
1183 uint64_t ign_error_code; \
1186 asm volatile(KVM_ASM_SAFE(insn) \
1187 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \
1189 : KVM_ASM_SAFE_CLOBBERS); \
1193 #define kvm_asm_safe_ec(insn, error_code, inputs...) \
1197 asm volatile(KVM_ASM_SAFE(insn) \
1198 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \
1200 : KVM_ASM_SAFE_CLOBBERS); \
1204 #define kvm_asm_safe_fep(insn, inputs...) \
1206 uint64_t ign_error_code; \
1209 asm volatile(KVM_ASM_SAFE(insn) \
1210 : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code) \
1212 : KVM_ASM_SAFE_CLOBBERS); \
1216 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...) \
1220 asm volatile(KVM_ASM_SAFE_FEP(insn) \
1221 : KVM_ASM_SAFE_OUTPUTS(vector, error_code) \
1223 : KVM_ASM_SAFE_CLOBBERS); \
1227 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \
1228 static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val) \
1230 uint64_t error_code; \
1234 asm volatile(KVM_ASM_SAFE##_FEP(#insn) \
1235 : "=a"(a), "=d"(d), \
1236 KVM_ASM_SAFE_OUTPUTS(vector, error_code) \
1238 : KVM_ASM_SAFE_CLOBBERS); \
1240 *val = (uint64_t)a | ((uint64_t)d << 32); \
1245 * Generate {insn}_safe() and {insn}_safe_fep() helpers for instructions that
1246 * use ECX as in input index, and EDX:EAX as a 64-bit output.
1248 #define BUILD_READ_U64_SAFE_HELPERS(insn) \
1249 BUILD_READ_U64_SAFE_HELPER(insn, , ) \
1250 BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP) \
1252 BUILD_READ_U64_SAFE_HELPERS(rdmsr)
1253 BUILD_READ_U64_SAFE_HELPERS(rdpmc)
1254 BUILD_READ_U64_SAFE_HELPERS(xgetbv)
1256 static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val)
1258 return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr));
1261 static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value)
1264 u32 edx = value >> 32;
1266 return kvm_asm_safe("xsetbv", "a" (eax), "d" (edx), "c" (index));
1269 bool kvm_is_tdp_enabled(void);
1271 static inline bool kvm_is_pmu_enabled(void)
1273 return get_kvm_param_bool("enable_pmu");
1276 static inline bool kvm_is_forced_emulation_enabled(void)
1278 return !!get_kvm_param_integer("force_emulation_prefix");
1281 uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr,
1283 uint64_t *vm_get_page_table_entry(struct kvm_vm *vm, uint64_t vaddr);
1285 uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
1287 uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
1288 void xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
1290 static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa,
1291 uint64_t size, uint64_t flags)
1293 return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0);
1296 static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size,
1299 uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags);
1304 void __vm_xsave_require_permission(uint64_t xfeature, const char *name);
1306 #define vm_xsave_require_permission(xfeature) \
1307 __vm_xsave_require_permission(xfeature, #xfeature)
1318 #define PG_LEVEL_SHIFT(_level) ((_level - 1) * 9 + 12)
1319 #define PG_LEVEL_SIZE(_level) (1ull << PG_LEVEL_SHIFT(_level))
1321 #define PG_SIZE_4K PG_LEVEL_SIZE(PG_LEVEL_4K)
1322 #define PG_SIZE_2M PG_LEVEL_SIZE(PG_LEVEL_2M)
1323 #define PG_SIZE_1G PG_LEVEL_SIZE(PG_LEVEL_1G)
1325 void __virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr, int level);
1326 void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
1327 uint64_t nr_bytes, int level);
1330 * Basic CPU control in CR0
1332 #define X86_CR0_PE (1UL<<0) /* Protection Enable */
1333 #define X86_CR0_MP (1UL<<1) /* Monitor Coprocessor */
1334 #define X86_CR0_EM (1UL<<2) /* Emulation */
1335 #define X86_CR0_TS (1UL<<3) /* Task Switched */
1336 #define X86_CR0_ET (1UL<<4) /* Extension Type */
1337 #define X86_CR0_NE (1UL<<5) /* Numeric Error */
1338 #define X86_CR0_WP (1UL<<16) /* Write Protect */
1339 #define X86_CR0_AM (1UL<<18) /* Alignment Mask */
1340 #define X86_CR0_NW (1UL<<29) /* Not Write-through */
1341 #define X86_CR0_CD (1UL<<30) /* Cache Disable */
1342 #define X86_CR0_PG (1UL<<31) /* Paging */
1344 #define PFERR_PRESENT_BIT 0
1345 #define PFERR_WRITE_BIT 1
1346 #define PFERR_USER_BIT 2
1347 #define PFERR_RSVD_BIT 3
1348 #define PFERR_FETCH_BIT 4
1349 #define PFERR_PK_BIT 5
1350 #define PFERR_SGX_BIT 15
1351 #define PFERR_GUEST_FINAL_BIT 32
1352 #define PFERR_GUEST_PAGE_BIT 33
1353 #define PFERR_IMPLICIT_ACCESS_BIT 48
1355 #define PFERR_PRESENT_MASK BIT(PFERR_PRESENT_BIT)
1356 #define PFERR_WRITE_MASK BIT(PFERR_WRITE_BIT)
1357 #define PFERR_USER_MASK BIT(PFERR_USER_BIT)
1358 #define PFERR_RSVD_MASK BIT(PFERR_RSVD_BIT)
1359 #define PFERR_FETCH_MASK BIT(PFERR_FETCH_BIT)
1360 #define PFERR_PK_MASK BIT(PFERR_PK_BIT)
1361 #define PFERR_SGX_MASK BIT(PFERR_SGX_BIT)
1362 #define PFERR_GUEST_FINAL_MASK BIT_ULL(PFERR_GUEST_FINAL_BIT)
1363 #define PFERR_GUEST_PAGE_MASK BIT_ULL(PFERR_GUEST_PAGE_BIT)
1364 #define PFERR_IMPLICIT_ACCESS BIT_ULL(PFERR_IMPLICIT_ACCESS_BIT)
1366 bool sys_clocksource_is_based_on_tsc(void);
1368 #endif /* SELFTEST_KVM_PROCESSOR_H */