2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24 #include INTEL_FAMILY_HEADER
29 #include <sys/types.h>
32 #include <sys/resource.h>
44 #include <linux/capability.h>
47 char *proc_stat = "/proc/stat";
50 struct timespec interval_ts = {5, 0};
52 unsigned int rapl_joules;
53 unsigned int summary_only;
54 unsigned int dump_only;
55 unsigned int do_nhm_cstates;
56 unsigned int do_snb_cstates;
57 unsigned int do_knl_cstates;
62 unsigned int do_c8_c9_c10;
63 unsigned int do_skl_residency;
64 unsigned int do_slm_cstates;
65 unsigned int use_c1_residency_msr;
66 unsigned int has_aperf;
68 unsigned int do_irtl_snb;
69 unsigned int do_irtl_hsw;
70 unsigned int units = 1000000; /* MHz etc */
71 unsigned int genuine_intel;
72 unsigned int has_invariant_tsc;
73 unsigned int do_nhm_platform_info;
74 unsigned int aperf_mperf_multiplier = 1;
79 unsigned int has_base_hz;
80 double tsc_tweak = 1.0;
81 unsigned int show_pkg;
82 unsigned int show_core;
83 unsigned int show_cpu;
84 unsigned int show_pkg_only;
85 unsigned int show_core_only;
86 char *output_buffer, *outp;
90 unsigned int do_gfx_rc6_ms;
91 unsigned long long gfx_cur_rc6_ms;
92 unsigned int do_gfx_mhz;
93 unsigned int gfx_cur_mhz;
94 unsigned int tcc_activation_temp;
95 unsigned int tcc_activation_temp_override;
96 double rapl_power_units, rapl_time_units;
97 double rapl_dram_energy_units, rapl_energy_units;
98 double rapl_joule_counter_range;
99 unsigned int do_core_perf_limit_reasons;
100 unsigned int do_gfx_perf_limit_reasons;
101 unsigned int do_ring_perf_limit_reasons;
102 unsigned int crystal_hz;
103 unsigned long long tsc_hz;
105 double discover_bclk(unsigned int family, unsigned int model);
106 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
107 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
108 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
109 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
110 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
111 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
113 #define RAPL_PKG (1 << 0)
114 /* 0x610 MSR_PKG_POWER_LIMIT */
115 /* 0x611 MSR_PKG_ENERGY_STATUS */
116 #define RAPL_PKG_PERF_STATUS (1 << 1)
117 /* 0x613 MSR_PKG_PERF_STATUS */
118 #define RAPL_PKG_POWER_INFO (1 << 2)
119 /* 0x614 MSR_PKG_POWER_INFO */
121 #define RAPL_DRAM (1 << 3)
122 /* 0x618 MSR_DRAM_POWER_LIMIT */
123 /* 0x619 MSR_DRAM_ENERGY_STATUS */
124 #define RAPL_DRAM_PERF_STATUS (1 << 4)
125 /* 0x61b MSR_DRAM_PERF_STATUS */
126 #define RAPL_DRAM_POWER_INFO (1 << 5)
127 /* 0x61c MSR_DRAM_POWER_INFO */
129 #define RAPL_CORES_POWER_LIMIT (1 << 6)
130 /* 0x638 MSR_PP0_POWER_LIMIT */
131 #define RAPL_CORE_POLICY (1 << 7)
132 /* 0x63a MSR_PP0_POLICY */
134 #define RAPL_GFX (1 << 8)
135 /* 0x640 MSR_PP1_POWER_LIMIT */
136 /* 0x641 MSR_PP1_ENERGY_STATUS */
137 /* 0x642 MSR_PP1_POLICY */
139 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
140 /* 0x639 MSR_PP0_ENERGY_STATUS */
141 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
142 #define TJMAX_DEFAULT 100
144 #define MAX(a, b) ((a) > (b) ? (a) : (b))
147 * buffer size used by sscanf() for added column names
148 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
150 #define NAME_BYTES 20
155 cpu_set_t *cpu_present_set, *cpu_affinity_set;
156 size_t cpu_present_setsize, cpu_affinity_setsize;
159 unsigned long long tsc;
160 unsigned long long aperf;
161 unsigned long long mperf;
162 unsigned long long c1;
163 unsigned int irq_count;
164 unsigned int smi_count;
167 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
168 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
169 unsigned long long counter[1];
170 } *thread_even, *thread_odd;
173 unsigned long long c3;
174 unsigned long long c6;
175 unsigned long long c7;
176 unsigned int core_temp_c;
177 unsigned int core_id;
178 unsigned long long counter[1];
179 } *core_even, *core_odd;
182 unsigned long long pc2;
183 unsigned long long pc3;
184 unsigned long long pc6;
185 unsigned long long pc7;
186 unsigned long long pc8;
187 unsigned long long pc9;
188 unsigned long long pc10;
189 unsigned long long pkg_wtd_core_c0;
190 unsigned long long pkg_any_core_c0;
191 unsigned long long pkg_any_gfxe_c0;
192 unsigned long long pkg_both_core_gfxe_c0;
193 long long gfx_rc6_ms;
194 unsigned int gfx_mhz;
195 unsigned int package_id;
196 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
197 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
198 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
199 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
200 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
201 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
202 unsigned int pkg_temp_c;
203 unsigned long long counter[1];
204 } *package_even, *package_odd;
206 #define ODD_COUNTERS thread_odd, core_odd, package_odd
207 #define EVEN_COUNTERS thread_even, core_even, package_even
209 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
210 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
211 topo.num_threads_per_core + \
212 (core_no) * topo.num_threads_per_core + (thread_no))
213 #define GET_CORE(core_base, core_no, pkg_no) \
214 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
215 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
217 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
218 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS};
219 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
222 unsigned int msr_num;
223 char name[NAME_BYTES];
225 enum counter_type type;
226 enum counter_format format;
227 struct msr_counter *next;
230 struct sys_counters {
231 unsigned int thread_counter_bytes;
232 unsigned int core_counter_bytes;
233 unsigned int package_counter_bytes;
234 struct msr_counter *tp;
235 struct msr_counter *cp;
236 struct msr_counter *pp;
239 struct system_summary {
240 struct thread_data threads;
241 struct core_data cores;
242 struct pkg_data packages;
251 int num_cores_per_pkg;
252 int num_threads_per_core;
255 struct timeval tv_even, tv_odd, tv_delta;
257 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
258 int *irqs_per_cpu; /* indexed by cpu_num */
260 void setup_all_buffers(void);
262 int cpu_is_not_present(int cpu)
264 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
267 * run func(thread, core, package) in topology order
268 * skip non-present cpus
271 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
272 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
274 int retval, pkg_no, core_no, thread_no;
276 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
277 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
278 for (thread_no = 0; thread_no <
279 topo.num_threads_per_core; ++thread_no) {
280 struct thread_data *t;
284 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
286 if (cpu_is_not_present(t->cpu_id))
289 c = GET_CORE(core_base, core_no, pkg_no);
290 p = GET_PKG(pkg_base, pkg_no);
292 retval = func(t, c, p);
301 int cpu_migrate(int cpu)
303 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
304 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
305 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
310 int get_msr_fd(int cpu)
320 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
321 fd = open(pathname, O_RDONLY);
323 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
330 int get_msr(int cpu, off_t offset, unsigned long long *msr)
334 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
336 if (retval != sizeof *msr)
337 err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset);
343 * Example Format w/ field column widths:
345 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 ThreadC CoreTmp CoreCnt PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt PkgCnt
346 * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678
349 void print_header(void)
351 struct msr_counter *mp;
354 outp += sprintf(outp, "\tPackage");
356 outp += sprintf(outp, "\tCore");
358 outp += sprintf(outp, "\tCPU");
360 outp += sprintf(outp, "\tAvg_MHz");
362 outp += sprintf(outp, "\tBusy%%");
364 outp += sprintf(outp, "\tBzy_MHz");
365 outp += sprintf(outp, "\tTSC_MHz");
371 outp += sprintf(outp, "\tIRQ");
373 outp += sprintf(outp, "\tSMI");
376 outp += sprintf(outp, "\tCPU%%c1");
377 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
378 outp += sprintf(outp, "\tCPU%%c3");
380 outp += sprintf(outp, "\tCPU%%c6");
382 outp += sprintf(outp, "\tCPU%%c7");
384 for (mp = sys.tp; mp; mp = mp->next) {
385 if (mp->format == FORMAT_RAW) {
387 outp += sprintf(outp, "\t%18.18s", mp->name);
389 outp += sprintf(outp, "\t%10.10s", mp->name);
391 outp += sprintf(outp, "\t%-7.7s", mp->name);
396 outp += sprintf(outp, "\tCoreTmp");
398 for (mp = sys.cp; mp; mp = mp->next) {
399 if (mp->format == FORMAT_RAW) {
401 outp += sprintf(outp, "\t%18.18s", mp->name);
403 outp += sprintf(outp, "\t%10.10s", mp->name);
405 outp += sprintf(outp, "\t%-7.7s", mp->name);
410 outp += sprintf(outp, "\tPkgTmp");
413 outp += sprintf(outp, "\tGFX%%rc6");
416 outp += sprintf(outp, "\tGFXMHz");
418 if (do_skl_residency) {
419 outp += sprintf(outp, "\tTotl%%C0");
420 outp += sprintf(outp, "\tAny%%C0");
421 outp += sprintf(outp, "\tGFX%%C0");
422 outp += sprintf(outp, "\tCPUGFX%%");
426 outp += sprintf(outp, "\tPkg%%pc2");
428 outp += sprintf(outp, "\tPkg%%pc3");
430 outp += sprintf(outp, "\tPkg%%pc6");
432 outp += sprintf(outp, "\tPkg%%pc7");
434 outp += sprintf(outp, "\tPkg%%pc8");
435 outp += sprintf(outp, "\tPkg%%pc9");
436 outp += sprintf(outp, "\tPk%%pc10");
439 if (do_rapl && !rapl_joules) {
440 if (do_rapl & RAPL_PKG)
441 outp += sprintf(outp, "\tPkgWatt");
442 if (do_rapl & RAPL_CORES_ENERGY_STATUS)
443 outp += sprintf(outp, "\tCorWatt");
444 if (do_rapl & RAPL_GFX)
445 outp += sprintf(outp, "\tGFXWatt");
446 if (do_rapl & RAPL_DRAM)
447 outp += sprintf(outp, "\tRAMWatt");
448 if (do_rapl & RAPL_PKG_PERF_STATUS)
449 outp += sprintf(outp, "\tPKG_%%");
450 if (do_rapl & RAPL_DRAM_PERF_STATUS)
451 outp += sprintf(outp, "\tRAM_%%");
452 } else if (do_rapl && rapl_joules) {
453 if (do_rapl & RAPL_PKG)
454 outp += sprintf(outp, "\tPkg_J");
455 if (do_rapl & RAPL_CORES_ENERGY_STATUS)
456 outp += sprintf(outp, "\tCor_J");
457 if (do_rapl & RAPL_GFX)
458 outp += sprintf(outp, "\tGFX_J");
459 if (do_rapl & RAPL_DRAM)
460 outp += sprintf(outp, "\tRAM_J");
461 if (do_rapl & RAPL_PKG_PERF_STATUS)
462 outp += sprintf(outp, "\tPKG_%%");
463 if (do_rapl & RAPL_DRAM_PERF_STATUS)
464 outp += sprintf(outp, "\tRAM_%%");
466 for (mp = sys.pp; mp; mp = mp->next) {
467 if (mp->format == FORMAT_RAW) {
469 outp += sprintf(outp, "\t%18.18s", mp->name);
471 outp += sprintf(outp, "\t%10.10s", mp->name);
473 outp += sprintf(outp, "\t%-7.7s", mp->name);
478 outp += sprintf(outp, "\n");
481 int dump_counters(struct thread_data *t, struct core_data *c,
485 struct msr_counter *mp;
487 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
490 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
491 t->cpu_id, t->flags);
492 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
493 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
494 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
495 outp += sprintf(outp, "c1: %016llX\n", t->c1);
498 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
500 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
502 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
503 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
504 i, mp->msr_num, t->counter[i]);
509 outp += sprintf(outp, "core: %d\n", c->core_id);
510 outp += sprintf(outp, "c3: %016llX\n", c->c3);
511 outp += sprintf(outp, "c6: %016llX\n", c->c6);
512 outp += sprintf(outp, "c7: %016llX\n", c->c7);
513 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
515 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
516 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
517 i, mp->msr_num, c->counter[i]);
522 outp += sprintf(outp, "package: %d\n", p->package_id);
524 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
525 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
526 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
527 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
529 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
531 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
533 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
535 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
536 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
537 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
538 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
539 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
540 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
541 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
542 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
543 outp += sprintf(outp, "Throttle PKG: %0X\n",
544 p->rapl_pkg_perf_status);
545 outp += sprintf(outp, "Throttle RAM: %0X\n",
546 p->rapl_dram_perf_status);
547 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
549 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
550 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
551 i, mp->msr_num, p->counter[i]);
555 outp += sprintf(outp, "\n");
561 * column formatting convention & formats
563 int format_counters(struct thread_data *t, struct core_data *c,
566 double interval_float;
569 struct msr_counter *mp;
571 /* if showing only 1st thread in core and this isn't one, bail out */
572 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
575 /* if showing only 1st thread in pkg and this isn't one, bail out */
576 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
579 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
581 /* topo columns, print blanks on 1st (average) line */
582 if (t == &average.threads) {
584 outp += sprintf(outp, "\t-");
586 outp += sprintf(outp, "\t-");
588 outp += sprintf(outp, "\t-");
592 outp += sprintf(outp, "\t%d", p->package_id);
594 outp += sprintf(outp, "\t-");
598 outp += sprintf(outp, "\t%d", c->core_id);
600 outp += sprintf(outp, "\t-");
603 outp += sprintf(outp, "\t%d", t->cpu_id);
608 outp += sprintf(outp, "\t%.0f",
609 1.0 / units * t->aperf / interval_float);
613 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
618 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
620 outp += sprintf(outp, "\t%.0f",
621 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
625 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
632 outp += sprintf(outp, "\t%d", t->irq_count);
636 outp += sprintf(outp, "\t%d", t->smi_count);
639 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
641 /* print per-core data only for 1st thread in core */
642 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
645 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
646 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
648 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
650 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
652 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
653 if (mp->format == FORMAT_RAW) {
655 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]);
657 outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
658 } else if (mp->format == FORMAT_DELTA) {
659 outp += sprintf(outp, "\t%8lld", t->counter[i]);
660 } else if (mp->format == FORMAT_PERCENT) {
661 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc);
667 outp += sprintf(outp, "\t%d", c->core_temp_c);
669 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
670 if (mp->format == FORMAT_RAW) {
672 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]);
674 outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
675 } else if (mp->format == FORMAT_DELTA) {
676 outp += sprintf(outp, "\t%8lld", c->counter[i]);
677 } else if (mp->format == FORMAT_PERCENT) {
678 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc);
682 /* print per-package data only for 1st core in package */
683 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
688 outp += sprintf(outp, "\t%d", p->pkg_temp_c);
692 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
693 outp += sprintf(outp, "\t**.**");
695 outp += sprintf(outp, "\t%.2f",
696 p->gfx_rc6_ms / 10.0 / interval_float);
702 outp += sprintf(outp, "\t%d", p->gfx_mhz);
704 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
705 if (do_skl_residency) {
706 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
707 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
708 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
709 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
713 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc);
715 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc);
717 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc);
719 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc);
721 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc);
722 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc);
723 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc);
727 * If measurement interval exceeds minimum RAPL Joule Counter range,
728 * indicate that results are suspect by printing "**" in fraction place.
730 if (interval_float < rapl_joule_counter_range)
735 if (do_rapl && !rapl_joules) {
736 if (do_rapl & RAPL_PKG)
737 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
738 if (do_rapl & RAPL_CORES_ENERGY_STATUS)
739 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
740 if (do_rapl & RAPL_GFX)
741 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
742 if (do_rapl & RAPL_DRAM)
743 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
744 if (do_rapl & RAPL_PKG_PERF_STATUS)
745 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
746 if (do_rapl & RAPL_DRAM_PERF_STATUS)
747 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
748 } else if (do_rapl && rapl_joules) {
749 if (do_rapl & RAPL_PKG)
750 outp += sprintf(outp, fmt8,
751 p->energy_pkg * rapl_energy_units);
752 if (do_rapl & RAPL_CORES)
753 outp += sprintf(outp, fmt8,
754 p->energy_cores * rapl_energy_units);
755 if (do_rapl & RAPL_GFX)
756 outp += sprintf(outp, fmt8,
757 p->energy_gfx * rapl_energy_units);
758 if (do_rapl & RAPL_DRAM)
759 outp += sprintf(outp, fmt8,
760 p->energy_dram * rapl_dram_energy_units);
761 if (do_rapl & RAPL_PKG_PERF_STATUS)
762 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
763 if (do_rapl & RAPL_DRAM_PERF_STATUS)
764 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
766 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
767 if (mp->format == FORMAT_RAW) {
769 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]);
771 outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
772 } else if (mp->format == FORMAT_DELTA) {
773 outp += sprintf(outp, "\t%8lld", p->counter[i]);
774 } else if (mp->format == FORMAT_PERCENT) {
775 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc);
780 outp += sprintf(outp, "\n");
785 void flush_output_stdout(void)
794 fputs(output_buffer, filep);
797 outp = output_buffer;
799 void flush_output_stderr(void)
801 fputs(output_buffer, outf);
803 outp = output_buffer;
805 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
809 if (!printed || !summary_only)
812 if (topo.num_cpus > 1)
813 format_counters(&average.threads, &average.cores,
821 for_all_cpus(format_counters, t, c, p);
824 #define DELTA_WRAP32(new, old) \
828 old = 0x100000000 + new - old; \
832 delta_package(struct pkg_data *new, struct pkg_data *old)
835 struct msr_counter *mp;
837 if (do_skl_residency) {
838 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
839 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
840 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
841 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
843 old->pc2 = new->pc2 - old->pc2;
845 old->pc3 = new->pc3 - old->pc3;
847 old->pc6 = new->pc6 - old->pc6;
849 old->pc7 = new->pc7 - old->pc7;
850 old->pc8 = new->pc8 - old->pc8;
851 old->pc9 = new->pc9 - old->pc9;
852 old->pc10 = new->pc10 - old->pc10;
853 old->pkg_temp_c = new->pkg_temp_c;
855 /* flag an error when rc6 counter resets/wraps */
856 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
857 old->gfx_rc6_ms = -1;
859 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
861 old->gfx_mhz = new->gfx_mhz;
863 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
864 DELTA_WRAP32(new->energy_cores, old->energy_cores);
865 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
866 DELTA_WRAP32(new->energy_dram, old->energy_dram);
867 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
868 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
870 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
871 if (mp->format == FORMAT_RAW)
872 old->counter[i] = new->counter[i];
874 old->counter[i] = new->counter[i] - old->counter[i];
881 delta_core(struct core_data *new, struct core_data *old)
884 struct msr_counter *mp;
886 old->c3 = new->c3 - old->c3;
887 old->c6 = new->c6 - old->c6;
888 old->c7 = new->c7 - old->c7;
889 old->core_temp_c = new->core_temp_c;
891 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
892 if (mp->format == FORMAT_RAW)
893 old->counter[i] = new->counter[i];
895 old->counter[i] = new->counter[i] - old->counter[i];
903 delta_thread(struct thread_data *new, struct thread_data *old,
904 struct core_data *core_delta)
907 struct msr_counter *mp;
909 old->tsc = new->tsc - old->tsc;
911 /* check for TSC < 1 Mcycles over interval */
912 if (old->tsc < (1000 * 1000))
913 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
914 "You can disable all c-states by booting with \"idle=poll\"\n"
915 "or just the deep ones with \"processor.max_cstate=1\"");
917 old->c1 = new->c1 - old->c1;
920 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
921 old->aperf = new->aperf - old->aperf;
922 old->mperf = new->mperf - old->mperf;
929 if (use_c1_residency_msr) {
931 * Some models have a dedicated C1 residency MSR,
932 * which should be more accurate than the derivation below.
936 * As counter collection is not atomic,
937 * it is possible for mperf's non-halted cycles + idle states
938 * to exceed TSC's all cycles: show c1 = 0% in that case.
940 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
943 /* normal case, derive c1 */
944 old->c1 = old->tsc - old->mperf - core_delta->c3
945 - core_delta->c6 - core_delta->c7;
949 if (old->mperf == 0) {
951 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
952 old->mperf = 1; /* divide by 0 protection */
956 old->irq_count = new->irq_count - old->irq_count;
959 old->smi_count = new->smi_count - old->smi_count;
961 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
962 if (mp->format == FORMAT_RAW)
963 old->counter[i] = new->counter[i];
965 old->counter[i] = new->counter[i] - old->counter[i];
970 int delta_cpu(struct thread_data *t, struct core_data *c,
971 struct pkg_data *p, struct thread_data *t2,
972 struct core_data *c2, struct pkg_data *p2)
976 /* calculate core delta only for 1st thread in core */
977 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
980 /* always calculate thread delta */
981 retval = delta_thread(t, t2, c2); /* c2 is core delta */
985 /* calculate package delta only for 1st core in package */
986 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
987 retval = delta_package(p, p2);
992 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
995 struct msr_counter *mp;
1005 /* tells format_counters to dump all fields from this set */
1006 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1013 p->pkg_wtd_core_c0 = 0;
1014 p->pkg_any_core_c0 = 0;
1015 p->pkg_any_gfxe_c0 = 0;
1016 p->pkg_both_core_gfxe_c0 = 0;
1031 p->energy_cores = 0;
1033 p->rapl_pkg_perf_status = 0;
1034 p->rapl_dram_perf_status = 0;
1040 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1043 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1046 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1049 int sum_counters(struct thread_data *t, struct core_data *c,
1053 struct msr_counter *mp;
1055 average.threads.tsc += t->tsc;
1056 average.threads.aperf += t->aperf;
1057 average.threads.mperf += t->mperf;
1058 average.threads.c1 += t->c1;
1060 average.threads.irq_count += t->irq_count;
1061 average.threads.smi_count += t->smi_count;
1063 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1064 if (mp->format == FORMAT_RAW)
1066 average.threads.counter[i] += t->counter[i];
1069 /* sum per-core values only for 1st thread in core */
1070 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1073 average.cores.c3 += c->c3;
1074 average.cores.c6 += c->c6;
1075 average.cores.c7 += c->c7;
1077 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1079 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1080 if (mp->format == FORMAT_RAW)
1082 average.cores.counter[i] += c->counter[i];
1085 /* sum per-pkg values only for 1st core in pkg */
1086 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1089 if (do_skl_residency) {
1090 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1091 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1092 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1093 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1096 average.packages.pc2 += p->pc2;
1098 average.packages.pc3 += p->pc3;
1100 average.packages.pc6 += p->pc6;
1102 average.packages.pc7 += p->pc7;
1103 average.packages.pc8 += p->pc8;
1104 average.packages.pc9 += p->pc9;
1105 average.packages.pc10 += p->pc10;
1107 average.packages.energy_pkg += p->energy_pkg;
1108 average.packages.energy_dram += p->energy_dram;
1109 average.packages.energy_cores += p->energy_cores;
1110 average.packages.energy_gfx += p->energy_gfx;
1112 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1113 average.packages.gfx_mhz = p->gfx_mhz;
1115 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1117 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1118 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1120 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1121 if (mp->format == FORMAT_RAW)
1123 average.packages.counter[i] += p->counter[i];
1128 * sum the counters for all cpus in the system
1129 * compute the weighted average
1131 void compute_average(struct thread_data *t, struct core_data *c,
1135 struct msr_counter *mp;
1137 clear_counters(&average.threads, &average.cores, &average.packages);
1139 for_all_cpus(sum_counters, t, c, p);
1141 average.threads.tsc /= topo.num_cpus;
1142 average.threads.aperf /= topo.num_cpus;
1143 average.threads.mperf /= topo.num_cpus;
1144 average.threads.c1 /= topo.num_cpus;
1146 average.cores.c3 /= topo.num_cores;
1147 average.cores.c6 /= topo.num_cores;
1148 average.cores.c7 /= topo.num_cores;
1150 if (do_skl_residency) {
1151 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1152 average.packages.pkg_any_core_c0 /= topo.num_packages;
1153 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1154 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1157 average.packages.pc2 /= topo.num_packages;
1159 average.packages.pc3 /= topo.num_packages;
1161 average.packages.pc6 /= topo.num_packages;
1163 average.packages.pc7 /= topo.num_packages;
1165 average.packages.pc8 /= topo.num_packages;
1166 average.packages.pc9 /= topo.num_packages;
1167 average.packages.pc10 /= topo.num_packages;
1169 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1170 if (mp->format == FORMAT_RAW)
1172 average.threads.counter[i] /= topo.num_cpus;
1174 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1175 if (mp->format == FORMAT_RAW)
1177 average.cores.counter[i] /= topo.num_cores;
1179 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1180 if (mp->format == FORMAT_RAW)
1182 average.packages.counter[i] /= topo.num_packages;
1186 static unsigned long long rdtsc(void)
1188 unsigned int low, high;
1190 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1192 return low | ((unsigned long long)high) << 32;
1198 * acquire and record local counters for that cpu
1200 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1202 int cpu = t->cpu_id;
1203 unsigned long long msr;
1204 int aperf_mperf_retry_count = 0;
1205 struct msr_counter *mp;
1208 if (cpu_migrate(cpu)) {
1209 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
1214 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1217 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1220 * The TSC, APERF and MPERF must be read together for
1221 * APERF/MPERF and MPERF/TSC to give accurate results.
1223 * Unfortunately, APERF and MPERF are read by
1224 * individual system call, so delays may occur
1225 * between them. If the time to read them
1226 * varies by a large amount, we re-read them.
1230 * This initial dummy APERF read has been seen to
1231 * reduce jitter in the subsequent reads.
1234 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1237 t->tsc = rdtsc(); /* re-read close to APERF */
1239 tsc_before = t->tsc;
1241 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1244 tsc_between = rdtsc();
1246 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
1249 tsc_after = rdtsc();
1251 aperf_time = tsc_between - tsc_before;
1252 mperf_time = tsc_after - tsc_between;
1255 * If the system call latency to read APERF and MPERF
1256 * differ by more than 2x, then try again.
1258 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1259 aperf_mperf_retry_count++;
1260 if (aperf_mperf_retry_count < 5)
1263 warnx("cpu%d jitter %lld %lld",
1264 cpu, aperf_time, mperf_time);
1266 aperf_mperf_retry_count = 0;
1268 t->aperf = t->aperf * aperf_mperf_multiplier;
1269 t->mperf = t->mperf * aperf_mperf_multiplier;
1273 t->irq_count = irqs_per_cpu[cpu];
1275 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1277 t->smi_count = msr & 0xFFFFFFFF;
1280 if (use_c1_residency_msr) {
1281 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1285 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1286 if (get_msr(cpu, mp->msr_num, &t->counter[i]))
1291 /* collect core counters only for 1st thread in core */
1292 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1295 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) {
1296 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1300 if (do_nhm_cstates && !do_knl_cstates) {
1301 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1303 } else if (do_knl_cstates) {
1304 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1309 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1313 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1315 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1318 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1319 if (get_msr(cpu, mp->msr_num, &c->counter[i]))
1323 /* collect package counters only for 1st core in package */
1324 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1327 if (do_skl_residency) {
1328 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1330 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1332 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1334 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1338 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1341 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1344 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1347 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1350 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1352 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1354 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1357 if (do_rapl & RAPL_PKG) {
1358 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1360 p->energy_pkg = msr & 0xFFFFFFFF;
1362 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
1363 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1365 p->energy_cores = msr & 0xFFFFFFFF;
1367 if (do_rapl & RAPL_DRAM) {
1368 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1370 p->energy_dram = msr & 0xFFFFFFFF;
1372 if (do_rapl & RAPL_GFX) {
1373 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1375 p->energy_gfx = msr & 0xFFFFFFFF;
1377 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1378 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1380 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1382 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1383 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1385 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1388 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1390 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1394 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1397 p->gfx_mhz = gfx_cur_mhz;
1399 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1400 if (get_msr(cpu, mp->msr_num, &p->counter[i]))
1408 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1409 * If you change the values, note they are used both in comparisons
1410 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1413 #define PCLUKN 0 /* Unknown */
1414 #define PCLRSV 1 /* Reserved */
1415 #define PCL__0 2 /* PC0 */
1416 #define PCL__1 3 /* PC1 */
1417 #define PCL__2 4 /* PC2 */
1418 #define PCL__3 5 /* PC3 */
1419 #define PCL__4 6 /* PC4 */
1420 #define PCL__6 7 /* PC6 */
1421 #define PCL_6N 8 /* PC6 No Retention */
1422 #define PCL_6R 9 /* PC6 Retention */
1423 #define PCL__7 10 /* PC7 */
1424 #define PCL_7S 11 /* PC7 Shrink */
1425 #define PCL__8 12 /* PC8 */
1426 #define PCL__9 13 /* PC9 */
1427 #define PCLUNL 14 /* Unlimited */
1429 int pkg_cstate_limit = PCLUKN;
1430 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1431 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1433 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1434 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1435 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1436 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1437 int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1438 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1439 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1440 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1444 calculate_tsc_tweak()
1446 tsc_tweak = base_hz / tsc_hz;
1450 dump_nhm_platform_info(void)
1452 unsigned long long msr;
1455 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1457 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1459 ratio = (msr >> 40) & 0xFF;
1460 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n",
1461 ratio, bclk, ratio * bclk);
1463 ratio = (msr >> 8) & 0xFF;
1464 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n",
1465 ratio, bclk, ratio * bclk);
1467 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
1468 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
1469 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
1475 dump_hsw_turbo_ratio_limits(void)
1477 unsigned long long msr;
1480 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
1482 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
1484 ratio = (msr >> 8) & 0xFF;
1486 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n",
1487 ratio, bclk, ratio * bclk);
1489 ratio = (msr >> 0) & 0xFF;
1491 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n",
1492 ratio, bclk, ratio * bclk);
1497 dump_ivt_turbo_ratio_limits(void)
1499 unsigned long long msr;
1502 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
1504 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
1506 ratio = (msr >> 56) & 0xFF;
1508 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n",
1509 ratio, bclk, ratio * bclk);
1511 ratio = (msr >> 48) & 0xFF;
1513 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n",
1514 ratio, bclk, ratio * bclk);
1516 ratio = (msr >> 40) & 0xFF;
1518 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n",
1519 ratio, bclk, ratio * bclk);
1521 ratio = (msr >> 32) & 0xFF;
1523 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n",
1524 ratio, bclk, ratio * bclk);
1526 ratio = (msr >> 24) & 0xFF;
1528 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n",
1529 ratio, bclk, ratio * bclk);
1531 ratio = (msr >> 16) & 0xFF;
1533 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n",
1534 ratio, bclk, ratio * bclk);
1536 ratio = (msr >> 8) & 0xFF;
1538 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n",
1539 ratio, bclk, ratio * bclk);
1541 ratio = (msr >> 0) & 0xFF;
1543 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n",
1544 ratio, bclk, ratio * bclk);
1549 dump_nhm_turbo_ratio_limits(void)
1551 unsigned long long msr;
1554 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1556 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
1558 ratio = (msr >> 56) & 0xFF;
1560 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n",
1561 ratio, bclk, ratio * bclk);
1563 ratio = (msr >> 48) & 0xFF;
1565 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n",
1566 ratio, bclk, ratio * bclk);
1568 ratio = (msr >> 40) & 0xFF;
1570 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n",
1571 ratio, bclk, ratio * bclk);
1573 ratio = (msr >> 32) & 0xFF;
1575 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n",
1576 ratio, bclk, ratio * bclk);
1578 ratio = (msr >> 24) & 0xFF;
1580 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n",
1581 ratio, bclk, ratio * bclk);
1583 ratio = (msr >> 16) & 0xFF;
1585 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n",
1586 ratio, bclk, ratio * bclk);
1588 ratio = (msr >> 8) & 0xFF;
1590 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n",
1591 ratio, bclk, ratio * bclk);
1593 ratio = (msr >> 0) & 0xFF;
1595 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n",
1596 ratio, bclk, ratio * bclk);
1601 dump_knl_turbo_ratio_limits(void)
1603 const unsigned int buckets_no = 7;
1605 unsigned long long msr;
1606 int delta_cores, delta_ratio;
1608 unsigned int cores[buckets_no];
1609 unsigned int ratio[buckets_no];
1611 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1613 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
1617 * Turbo encoding in KNL is as follows:
1619 * [7:1] -- Base value of number of active cores of bucket 1.
1620 * [15:8] -- Base value of freq ratio of bucket 1.
1621 * [20:16] -- +ve delta of number of active cores of bucket 2.
1622 * i.e. active cores of bucket 2 =
1623 * active cores of bucket 1 + delta
1624 * [23:21] -- Negative delta of freq ratio of bucket 2.
1625 * i.e. freq ratio of bucket 2 =
1626 * freq ratio of bucket 1 - delta
1627 * [28:24]-- +ve delta of number of active cores of bucket 3.
1628 * [31:29]-- -ve delta of freq ratio of bucket 3.
1629 * [36:32]-- +ve delta of number of active cores of bucket 4.
1630 * [39:37]-- -ve delta of freq ratio of bucket 4.
1631 * [44:40]-- +ve delta of number of active cores of bucket 5.
1632 * [47:45]-- -ve delta of freq ratio of bucket 5.
1633 * [52:48]-- +ve delta of number of active cores of bucket 6.
1634 * [55:53]-- -ve delta of freq ratio of bucket 6.
1635 * [60:56]-- +ve delta of number of active cores of bucket 7.
1636 * [63:61]-- -ve delta of freq ratio of bucket 7.
1640 cores[b_nr] = (msr & 0xFF) >> 1;
1641 ratio[b_nr] = (msr >> 8) & 0xFF;
1643 for (i = 16; i < 64; i += 8) {
1644 delta_cores = (msr >> i) & 0x1F;
1645 delta_ratio = (msr >> (i + 5)) & 0x7;
1647 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1648 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1652 for (i = buckets_no - 1; i >= 0; i--)
1653 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
1655 "%d * %.0f = %.0f MHz max turbo %d active cores\n",
1656 ratio[i], bclk, ratio[i] * bclk, cores[i]);
1660 dump_nhm_cst_cfg(void)
1662 unsigned long long msr;
1664 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1666 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1667 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1669 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr);
1671 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
1672 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1673 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1674 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1675 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1676 (msr & (1 << 15)) ? "" : "UN",
1677 (unsigned int)msr & 0xF,
1678 pkg_cstate_limit_strings[pkg_cstate_limit]);
1683 dump_config_tdp(void)
1685 unsigned long long msr;
1687 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
1688 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
1689 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
1691 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
1692 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
1694 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1695 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1696 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1697 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
1699 fprintf(outf, ")\n");
1701 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
1702 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
1704 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1705 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1706 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1707 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
1709 fprintf(outf, ")\n");
1711 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
1712 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
1714 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1715 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1716 fprintf(outf, ")\n");
1718 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
1719 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
1720 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
1721 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1722 fprintf(outf, ")\n");
1725 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1727 void print_irtl(void)
1729 unsigned long long msr;
1731 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
1732 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
1733 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1734 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1736 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
1737 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
1738 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1739 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1741 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
1742 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
1743 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1744 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1749 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
1750 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
1751 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1752 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1754 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
1755 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
1756 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1757 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1759 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
1760 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
1761 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1762 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1765 void free_fd_percpu(void)
1769 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
1770 if (fd_percpu[i] != 0)
1771 close(fd_percpu[i]);
1777 void free_all_buffers(void)
1779 CPU_FREE(cpu_present_set);
1780 cpu_present_set = NULL;
1781 cpu_present_setsize = 0;
1783 CPU_FREE(cpu_affinity_set);
1784 cpu_affinity_set = NULL;
1785 cpu_affinity_setsize = 0;
1793 package_even = NULL;
1803 free(output_buffer);
1804 output_buffer = NULL;
1809 free(irq_column_2_cpu);
1814 * Open a file, and exit on failure
1816 FILE *fopen_or_die(const char *path, const char *mode)
1818 FILE *filep = fopen(path, mode);
1820 err(1, "%s: open failed", path);
1825 * Parse a file containing a single int.
1827 int parse_int_file(const char *fmt, ...)
1830 char path[PATH_MAX];
1834 va_start(args, fmt);
1835 vsnprintf(path, sizeof(path), fmt, args);
1837 filep = fopen_or_die(path, "r");
1838 if (fscanf(filep, "%d", &value) != 1)
1839 err(1, "%s: failed to parse number from file", path);
1845 * get_cpu_position_in_core(cpu)
1846 * return the position of the CPU among its HT siblings in the core
1847 * return -1 if the sibling is not in list
1849 int get_cpu_position_in_core(int cpu)
1858 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
1860 filep = fopen(path, "r");
1861 if (filep == NULL) {
1866 for (i = 0; i < topo.num_threads_per_core; i++) {
1867 fscanf(filep, "%d", &this_cpu);
1868 if (this_cpu == cpu) {
1873 /* Account for no separator after last thread*/
1874 if (i != (topo.num_threads_per_core - 1))
1875 fscanf(filep, "%c", &character);
1883 * cpu_is_first_core_in_package(cpu)
1884 * return 1 if given CPU is 1st core in package
1886 int cpu_is_first_core_in_package(int cpu)
1888 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
1891 int get_physical_package_id(int cpu)
1893 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
1896 int get_core_id(int cpu)
1898 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
1901 int get_num_ht_siblings(int cpu)
1911 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
1912 filep = fopen_or_die(path, "r");
1916 * A ',' separated or '-' separated set of numbers
1917 * (eg 1-2 or 1,3,4,5)
1919 fscanf(filep, "%d%c\n", &sib1, &character);
1920 fseek(filep, 0, SEEK_SET);
1921 fgets(str, 100, filep);
1922 ch = strchr(str, character);
1923 while (ch != NULL) {
1925 ch = strchr(ch+1, character);
1933 * run func(thread, core, package) in topology order
1934 * skip non-present cpus
1937 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
1938 struct pkg_data *, struct thread_data *, struct core_data *,
1939 struct pkg_data *), struct thread_data *thread_base,
1940 struct core_data *core_base, struct pkg_data *pkg_base,
1941 struct thread_data *thread_base2, struct core_data *core_base2,
1942 struct pkg_data *pkg_base2)
1944 int retval, pkg_no, core_no, thread_no;
1946 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
1947 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
1948 for (thread_no = 0; thread_no <
1949 topo.num_threads_per_core; ++thread_no) {
1950 struct thread_data *t, *t2;
1951 struct core_data *c, *c2;
1952 struct pkg_data *p, *p2;
1954 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
1956 if (cpu_is_not_present(t->cpu_id))
1959 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
1961 c = GET_CORE(core_base, core_no, pkg_no);
1962 c2 = GET_CORE(core_base2, core_no, pkg_no);
1964 p = GET_PKG(pkg_base, pkg_no);
1965 p2 = GET_PKG(pkg_base2, pkg_no);
1967 retval = func(t, c, p, t2, c2, p2);
1977 * run func(cpu) on every cpu in /proc/stat
1978 * return max_cpu number
1980 int for_all_proc_cpus(int (func)(int))
1986 fp = fopen_or_die(proc_stat, "r");
1988 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
1990 err(1, "%s: failed to parse format", proc_stat);
1993 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
1997 retval = func(cpu_num);
2007 void re_initialize(void)
2010 setup_all_buffers();
2011 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2017 * remember the last one seen, it will be the max
2019 int count_cpus(int cpu)
2021 if (topo.max_cpu_num < cpu)
2022 topo.max_cpu_num = cpu;
2027 int mark_cpu_present(int cpu)
2029 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
2034 * snapshot_proc_interrupts()
2036 * read and record summary of /proc/interrupts
2038 * return 1 if config change requires a restart, else return 0
2040 int snapshot_proc_interrupts(void)
2046 fp = fopen_or_die("/proc/interrupts", "r");
2050 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2051 for (column = 0; column < topo.num_cpus; ++column) {
2054 retval = fscanf(fp, " CPU%d", &cpu_number);
2058 if (cpu_number > topo.max_cpu_num) {
2059 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2063 irq_column_2_cpu[column] = cpu_number;
2064 irqs_per_cpu[cpu_number] = 0;
2067 /* read /proc/interrupt count lines and sum up irqs per cpu */
2072 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2076 /* read the count per cpu */
2077 for (column = 0; column < topo.num_cpus; ++column) {
2079 int cpu_number, irq_count;
2081 retval = fscanf(fp, " %d", &irq_count);
2085 cpu_number = irq_column_2_cpu[column];
2086 irqs_per_cpu[cpu_number] += irq_count;
2090 while (getc(fp) != '\n')
2091 ; /* flush interrupt description */
2097 * snapshot_gfx_rc6_ms()
2099 * record snapshot of
2100 * /sys/class/drm/card0/power/rc6_residency_ms
2102 * return 1 if config change requires a restart, else return 0
2104 int snapshot_gfx_rc6_ms(void)
2109 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2111 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2120 * snapshot_gfx_mhz()
2122 * record snapshot of
2123 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2125 * return 1 if config change requires a restart, else return 0
2127 int snapshot_gfx_mhz(void)
2133 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2137 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2145 * snapshot /proc and /sys files
2147 * return 1 if configuration restart needed, else return 0
2149 int snapshot_proc_sysfs_files(void)
2151 if (snapshot_proc_interrupts())
2155 snapshot_gfx_rc6_ms();
2163 void turbostat_loop()
2171 snapshot_proc_sysfs_files();
2172 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2175 } else if (retval == -1) {
2176 if (restarted > 1) {
2183 gettimeofday(&tv_even, (struct timezone *)NULL);
2186 if (for_all_proc_cpus(cpu_is_not_present)) {
2190 nanosleep(&interval_ts, NULL);
2191 if (snapshot_proc_sysfs_files())
2193 retval = for_all_cpus(get_counters, ODD_COUNTERS);
2196 } else if (retval == -1) {
2200 gettimeofday(&tv_odd, (struct timezone *)NULL);
2201 timersub(&tv_odd, &tv_even, &tv_delta);
2202 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2206 compute_average(EVEN_COUNTERS);
2207 format_all_counters(EVEN_COUNTERS);
2208 flush_output_stdout();
2209 nanosleep(&interval_ts, NULL);
2210 if (snapshot_proc_sysfs_files())
2212 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2215 } else if (retval == -1) {
2219 gettimeofday(&tv_even, (struct timezone *)NULL);
2220 timersub(&tv_even, &tv_odd, &tv_delta);
2221 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2225 compute_average(ODD_COUNTERS);
2226 format_all_counters(ODD_COUNTERS);
2227 flush_output_stdout();
2231 void check_dev_msr()
2236 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2237 if (stat(pathname, &sb))
2238 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2239 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
2242 void check_permissions()
2244 struct __user_cap_header_struct cap_header_data;
2245 cap_user_header_t cap_header = &cap_header_data;
2246 struct __user_cap_data_struct cap_data_data;
2247 cap_user_data_t cap_data = &cap_data_data;
2248 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2252 /* check for CAP_SYS_RAWIO */
2253 cap_header->pid = getpid();
2254 cap_header->version = _LINUX_CAPABILITY_VERSION;
2255 if (capget(cap_header, cap_data) < 0)
2256 err(-6, "capget(2) failed");
2258 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2260 warnx("capget(CAP_SYS_RAWIO) failed,"
2261 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2264 /* test file permissions */
2265 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2266 if (euidaccess(pathname, R_OK)) {
2268 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2271 /* if all else fails, thell them to be root */
2274 warnx("... or simply run as root");
2281 * NHM adds support for additional MSRs:
2283 * MSR_SMI_COUNT 0x00000034
2285 * MSR_PLATFORM_INFO 0x000000ce
2286 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
2288 * MSR_PKG_C3_RESIDENCY 0x000003f8
2289 * MSR_PKG_C6_RESIDENCY 0x000003f9
2290 * MSR_CORE_C3_RESIDENCY 0x000003fc
2291 * MSR_CORE_C6_RESIDENCY 0x000003fd
2294 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
2296 int probe_nhm_msrs(unsigned int family, unsigned int model)
2298 unsigned long long msr;
2299 unsigned int base_ratio;
2300 int *pkg_cstate_limits;
2308 bclk = discover_bclk(family, model);
2311 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2312 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2313 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
2314 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
2315 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
2316 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2317 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2318 pkg_cstate_limits = nhm_pkg_cstate_limits;
2320 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
2321 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
2322 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2323 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2324 pkg_cstate_limits = snb_pkg_cstate_limits;
2326 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2327 case INTEL_FAM6_HASWELL_X: /* HSX */
2328 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2329 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2330 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2331 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2332 case INTEL_FAM6_BROADWELL_X: /* BDX */
2333 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2334 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2335 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2336 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2337 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2338 pkg_cstate_limits = hsw_pkg_cstate_limits;
2340 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2341 pkg_cstate_limits = skx_pkg_cstate_limits;
2343 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
2344 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
2345 pkg_cstate_limits = slv_pkg_cstate_limits;
2347 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
2348 pkg_cstate_limits = amt_pkg_cstate_limits;
2350 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
2351 case INTEL_FAM6_XEON_PHI_KNM:
2352 pkg_cstate_limits = phi_pkg_cstate_limits;
2354 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2355 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
2356 pkg_cstate_limits = bxt_pkg_cstate_limits;
2361 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
2362 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2364 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2365 base_ratio = (msr >> 8) & 0xFF;
2367 base_hz = base_ratio * bclk * 1000000;
2371 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2374 /* Nehalem compatible, but do not include turbo-ratio limit support */
2375 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2376 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2377 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
2378 case INTEL_FAM6_XEON_PHI_KNM:
2384 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2393 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2394 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2400 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2409 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2416 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2425 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2426 case INTEL_FAM6_XEON_PHI_KNM:
2432 int has_config_tdp(unsigned int family, unsigned int model)
2441 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2442 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2443 case INTEL_FAM6_HASWELL_X: /* HSX */
2444 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2445 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2446 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2447 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2448 case INTEL_FAM6_BROADWELL_X: /* BDX */
2449 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2450 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2451 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2452 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2453 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2454 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2456 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2457 case INTEL_FAM6_XEON_PHI_KNM:
2465 dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
2467 if (!do_nhm_platform_info)
2470 dump_nhm_platform_info();
2472 if (has_hsw_turbo_ratio_limit(family, model))
2473 dump_hsw_turbo_ratio_limits();
2475 if (has_ivt_turbo_ratio_limit(family, model))
2476 dump_ivt_turbo_ratio_limits();
2478 if (has_nhm_turbo_ratio_limit(family, model))
2479 dump_nhm_turbo_ratio_limits();
2481 if (has_knl_turbo_ratio_limit(family, model))
2482 dump_knl_turbo_ratio_limits();
2484 if (has_config_tdp(family, model))
2493 * Decode the ENERGY_PERF_BIAS MSR
2495 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2497 unsigned long long msr;
2506 /* EPB is per-package */
2507 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2510 if (cpu_migrate(cpu)) {
2511 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2515 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2518 switch (msr & 0xF) {
2519 case ENERGY_PERF_BIAS_PERFORMANCE:
2520 epb_string = "performance";
2522 case ENERGY_PERF_BIAS_NORMAL:
2523 epb_string = "balanced";
2525 case ENERGY_PERF_BIAS_POWERSAVE:
2526 epb_string = "powersave";
2529 epb_string = "custom";
2532 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
2538 * Decode the MSR_HWP_CAPABILITIES
2540 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2542 unsigned long long msr;
2550 /* MSR_HWP_CAPABILITIES is per-package */
2551 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2554 if (cpu_migrate(cpu)) {
2555 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2559 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2562 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
2563 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2565 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2566 if ((msr & (1 << 0)) == 0)
2569 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2572 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
2573 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2575 (unsigned int)HWP_HIGHEST_PERF(msr),
2576 (unsigned int)HWP_GUARANTEED_PERF(msr),
2577 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2578 (unsigned int)HWP_LOWEST_PERF(msr));
2580 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2583 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
2584 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2586 (unsigned int)(((msr) >> 0) & 0xff),
2587 (unsigned int)(((msr) >> 8) & 0xff),
2588 (unsigned int)(((msr) >> 16) & 0xff),
2589 (unsigned int)(((msr) >> 24) & 0xff),
2590 (unsigned int)(((msr) >> 32) & 0xff3),
2591 (unsigned int)(((msr) >> 42) & 0x1));
2594 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2597 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
2598 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2600 (unsigned int)(((msr) >> 0) & 0xff),
2601 (unsigned int)(((msr) >> 8) & 0xff),
2602 (unsigned int)(((msr) >> 16) & 0xff),
2603 (unsigned int)(((msr) >> 24) & 0xff),
2604 (unsigned int)(((msr) >> 32) & 0xff3));
2606 if (has_hwp_notify) {
2607 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2610 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
2611 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2613 ((msr) & 0x1) ? "EN" : "Dis",
2614 ((msr) & 0x2) ? "EN" : "Dis");
2616 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2619 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
2620 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2622 ((msr) & 0x1) ? "" : "No-",
2623 ((msr) & 0x2) ? "" : "No-");
2629 * print_perf_limit()
2631 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2633 unsigned long long msr;
2639 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2642 if (cpu_migrate(cpu)) {
2643 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2647 if (do_core_perf_limit_reasons) {
2648 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
2649 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2650 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
2651 (msr & 1 << 15) ? "bit15, " : "",
2652 (msr & 1 << 14) ? "bit14, " : "",
2653 (msr & 1 << 13) ? "Transitions, " : "",
2654 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2655 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2656 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2657 (msr & 1 << 9) ? "CorePwr, " : "",
2658 (msr & 1 << 8) ? "Amps, " : "",
2659 (msr & 1 << 6) ? "VR-Therm, " : "",
2660 (msr & 1 << 5) ? "Auto-HWP, " : "",
2661 (msr & 1 << 4) ? "Graphics, " : "",
2662 (msr & 1 << 2) ? "bit2, " : "",
2663 (msr & 1 << 1) ? "ThermStatus, " : "",
2664 (msr & 1 << 0) ? "PROCHOT, " : "");
2665 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
2666 (msr & 1 << 31) ? "bit31, " : "",
2667 (msr & 1 << 30) ? "bit30, " : "",
2668 (msr & 1 << 29) ? "Transitions, " : "",
2669 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2670 (msr & 1 << 27) ? "PkgPwrL2, " : "",
2671 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2672 (msr & 1 << 25) ? "CorePwr, " : "",
2673 (msr & 1 << 24) ? "Amps, " : "",
2674 (msr & 1 << 22) ? "VR-Therm, " : "",
2675 (msr & 1 << 21) ? "Auto-HWP, " : "",
2676 (msr & 1 << 20) ? "Graphics, " : "",
2677 (msr & 1 << 18) ? "bit18, " : "",
2678 (msr & 1 << 17) ? "ThermStatus, " : "",
2679 (msr & 1 << 16) ? "PROCHOT, " : "");
2682 if (do_gfx_perf_limit_reasons) {
2683 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
2684 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2685 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
2686 (msr & 1 << 0) ? "PROCHOT, " : "",
2687 (msr & 1 << 1) ? "ThermStatus, " : "",
2688 (msr & 1 << 4) ? "Graphics, " : "",
2689 (msr & 1 << 6) ? "VR-Therm, " : "",
2690 (msr & 1 << 8) ? "Amps, " : "",
2691 (msr & 1 << 9) ? "GFXPwr, " : "",
2692 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2693 (msr & 1 << 11) ? "PkgPwrL2, " : "");
2694 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
2695 (msr & 1 << 16) ? "PROCHOT, " : "",
2696 (msr & 1 << 17) ? "ThermStatus, " : "",
2697 (msr & 1 << 20) ? "Graphics, " : "",
2698 (msr & 1 << 22) ? "VR-Therm, " : "",
2699 (msr & 1 << 24) ? "Amps, " : "",
2700 (msr & 1 << 25) ? "GFXPwr, " : "",
2701 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2702 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2704 if (do_ring_perf_limit_reasons) {
2705 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
2706 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2707 fprintf(outf, " (Active: %s%s%s%s%s%s)",
2708 (msr & 1 << 0) ? "PROCHOT, " : "",
2709 (msr & 1 << 1) ? "ThermStatus, " : "",
2710 (msr & 1 << 6) ? "VR-Therm, " : "",
2711 (msr & 1 << 8) ? "Amps, " : "",
2712 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2713 (msr & 1 << 11) ? "PkgPwrL2, " : "");
2714 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
2715 (msr & 1 << 16) ? "PROCHOT, " : "",
2716 (msr & 1 << 17) ? "ThermStatus, " : "",
2717 (msr & 1 << 22) ? "VR-Therm, " : "",
2718 (msr & 1 << 24) ? "Amps, " : "",
2719 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2720 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2725 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
2726 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
2728 double get_tdp(unsigned int model)
2730 unsigned long long msr;
2732 if (do_rapl & RAPL_PKG_POWER_INFO)
2733 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
2734 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2737 case INTEL_FAM6_ATOM_SILVERMONT1:
2738 case INTEL_FAM6_ATOM_SILVERMONT2:
2746 * rapl_dram_energy_units_probe()
2747 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2750 rapl_dram_energy_units_probe(int model, double rapl_energy_units)
2752 /* only called for genuine_intel, family 6 */
2755 case INTEL_FAM6_HASWELL_X: /* HSX */
2756 case INTEL_FAM6_BROADWELL_X: /* BDX */
2757 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2758 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
2759 case INTEL_FAM6_XEON_PHI_KNM:
2760 return (rapl_dram_energy_units = 15.3 / 1000000);
2762 return (rapl_energy_units);
2770 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
2772 void rapl_probe(unsigned int family, unsigned int model)
2774 unsigned long long msr;
2775 unsigned int time_unit;
2785 case INTEL_FAM6_SANDYBRIDGE:
2786 case INTEL_FAM6_IVYBRIDGE:
2787 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2788 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2789 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2790 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2791 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2792 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
2794 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2795 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
2797 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2798 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2799 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2800 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2801 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2803 case INTEL_FAM6_HASWELL_X: /* HSX */
2804 case INTEL_FAM6_BROADWELL_X: /* BDX */
2805 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2806 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2807 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
2808 case INTEL_FAM6_XEON_PHI_KNM:
2809 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2811 case INTEL_FAM6_SANDYBRIDGE_X:
2812 case INTEL_FAM6_IVYBRIDGE_X:
2813 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
2815 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
2816 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
2817 do_rapl = RAPL_PKG | RAPL_CORES;
2819 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
2820 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
2826 /* units on package 0, verify later other packages match */
2827 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
2830 rapl_power_units = 1.0 / (1 << (msr & 0xF));
2831 if (model == INTEL_FAM6_ATOM_SILVERMONT1)
2832 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
2834 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
2836 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
2838 time_unit = msr >> 16 & 0xF;
2842 rapl_time_units = 1.0 / (1 << (time_unit));
2844 tdp = get_tdp(model);
2846 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
2848 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
2853 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
2862 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2863 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2864 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2865 do_gfx_perf_limit_reasons = 1;
2866 case INTEL_FAM6_HASWELL_X: /* HSX */
2867 do_core_perf_limit_reasons = 1;
2868 do_ring_perf_limit_reasons = 1;
2874 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2876 unsigned long long msr;
2880 if (!(do_dts || do_ptm))
2885 /* DTS is per-core, no need to print for each thread */
2886 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2889 if (cpu_migrate(cpu)) {
2890 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2894 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
2895 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2898 dts = (msr >> 16) & 0x7F;
2899 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
2900 cpu, msr, tcc_activation_temp - dts);
2903 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
2906 dts = (msr >> 16) & 0x7F;
2907 dts2 = (msr >> 8) & 0x7F;
2908 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
2909 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2915 unsigned int resolution;
2917 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2920 dts = (msr >> 16) & 0x7F;
2921 resolution = (msr >> 27) & 0xF;
2922 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
2923 cpu, msr, tcc_activation_temp - dts, resolution);
2926 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
2929 dts = (msr >> 16) & 0x7F;
2930 dts2 = (msr >> 8) & 0x7F;
2931 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
2932 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2939 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
2941 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
2943 ((msr >> 15) & 1) ? "EN" : "DIS",
2944 ((msr >> 0) & 0x7FFF) * rapl_power_units,
2945 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
2946 (((msr >> 16) & 1) ? "EN" : "DIS"));
2951 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2953 unsigned long long msr;
2959 /* RAPL counters are per package, so print only for 1st thread/package */
2960 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2964 if (cpu_migrate(cpu)) {
2965 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2969 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
2973 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
2974 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
2975 rapl_power_units, rapl_energy_units, rapl_time_units);
2977 if (do_rapl & RAPL_PKG_POWER_INFO) {
2979 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
2983 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
2985 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2986 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2987 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2988 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
2991 if (do_rapl & RAPL_PKG) {
2993 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
2996 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
2997 cpu, msr, (msr >> 63) & 1 ? "": "UN");
2999 print_power_limit_msr(cpu, msr, "PKG Limit #1");
3000 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
3002 ((msr >> 47) & 1) ? "EN" : "DIS",
3003 ((msr >> 32) & 0x7FFF) * rapl_power_units,
3004 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3005 ((msr >> 48) & 1) ? "EN" : "DIS");
3008 if (do_rapl & RAPL_DRAM_POWER_INFO) {
3009 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3012 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3014 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3015 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3016 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3017 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3019 if (do_rapl & RAPL_DRAM) {
3020 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3022 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
3023 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3025 print_power_limit_msr(cpu, msr, "DRAM Limit");
3027 if (do_rapl & RAPL_CORE_POLICY) {
3029 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3032 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
3035 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
3037 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3039 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3040 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3041 print_power_limit_msr(cpu, msr, "Cores Limit");
3044 if (do_rapl & RAPL_GFX) {
3046 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3049 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
3051 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3053 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3054 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3055 print_power_limit_msr(cpu, msr, "GFX Limit");
3062 * SNB adds support for additional MSRs:
3064 * MSR_PKG_C7_RESIDENCY 0x000003fa
3065 * MSR_CORE_C7_RESIDENCY 0x000003fe
3066 * MSR_PKG_C2_RESIDENCY 0x0000060d
3069 int has_snb_msrs(unsigned int family, unsigned int model)
3075 case INTEL_FAM6_SANDYBRIDGE:
3076 case INTEL_FAM6_SANDYBRIDGE_X:
3077 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3078 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3079 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3080 case INTEL_FAM6_HASWELL_X: /* HSW */
3081 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3082 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3083 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3084 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3085 case INTEL_FAM6_BROADWELL_X: /* BDX */
3086 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3087 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3088 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3089 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3090 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3091 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3092 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3093 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3100 * HSW adds support for additional MSRs:
3102 * MSR_PKG_C8_RESIDENCY 0x00000630
3103 * MSR_PKG_C9_RESIDENCY 0x00000631
3104 * MSR_PKG_C10_RESIDENCY 0x00000632
3106 * MSR_PKGC8_IRTL 0x00000633
3107 * MSR_PKGC9_IRTL 0x00000634
3108 * MSR_PKGC10_IRTL 0x00000635
3111 int has_hsw_msrs(unsigned int family, unsigned int model)
3117 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3118 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3119 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3120 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3121 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3122 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3123 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3130 * SKL adds support for additional MSRS:
3132 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3133 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3134 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3135 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3137 int has_skl_msrs(unsigned int family, unsigned int model)
3143 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3144 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3145 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3146 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3154 int is_slm(unsigned int family, unsigned int model)
3159 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
3160 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
3166 int is_knl(unsigned int family, unsigned int model)
3171 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3172 case INTEL_FAM6_XEON_PHI_KNM:
3178 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3180 if (is_knl(family, model))
3185 #define SLM_BCLK_FREQS 5
3186 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3188 double slm_bclk(void)
3190 unsigned long long msr = 3;
3194 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
3195 fprintf(outf, "SLM BCLK: unknown\n");
3198 if (i >= SLM_BCLK_FREQS) {
3199 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
3202 freq = slm_freq_table[i];
3204 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
3209 double discover_bclk(unsigned int family, unsigned int model)
3211 if (has_snb_msrs(family, model) || is_knl(family, model))
3213 else if (is_slm(family, model))
3220 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3221 * the Thermal Control Circuit (TCC) activates.
3222 * This is usually equal to tjMax.
3224 * Older processors do not have this MSR, so there we guess,
3225 * but also allow cmdline over-ride with -T.
3227 * Several MSR temperature values are in units of degrees-C
3228 * below this value, including the Digital Thermal Sensor (DTS),
3229 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3231 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3233 unsigned long long msr;
3234 unsigned int target_c_local;
3237 /* tcc_activation_temp is used only for dts or ptm */
3238 if (!(do_dts || do_ptm))
3241 /* this is a per-package concept */
3242 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3246 if (cpu_migrate(cpu)) {
3247 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3251 if (tcc_activation_temp_override != 0) {
3252 tcc_activation_temp = tcc_activation_temp_override;
3253 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
3254 cpu, tcc_activation_temp);
3258 /* Temperature Target MSR is Nehalem and newer only */
3259 if (!do_nhm_platform_info)
3262 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
3265 target_c_local = (msr >> 16) & 0xFF;
3268 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
3269 cpu, msr, target_c_local);
3271 if (!target_c_local)
3274 tcc_activation_temp = target_c_local;
3279 tcc_activation_temp = TJMAX_DEFAULT;
3280 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
3281 cpu, tcc_activation_temp);
3286 void decode_feature_control_msr(void)
3288 unsigned long long msr;
3290 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3291 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3293 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3294 msr & (1 << 18) ? "SGX" : "");
3297 void decode_misc_enable_msr(void)
3299 unsigned long long msr;
3301 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
3302 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
3304 msr & (1 << 3) ? "TCC" : "",
3305 msr & (1 << 16) ? "EIST" : "",
3306 msr & (1 << 18) ? "MONITOR" : "");
3310 * Decode MSR_MISC_PWR_MGMT
3312 * Decode the bits according to the Nehalem documentation
3313 * bit[0] seems to continue to have same meaning going forward
3316 void decode_misc_pwr_mgmt_msr(void)
3318 unsigned long long msr;
3320 if (!do_nhm_platform_info)
3323 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3324 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3326 msr & (1 << 0) ? "DIS" : "EN",
3327 msr & (1 << 1) ? "EN" : "DIS",
3328 msr & (1 << 8) ? "EN" : "DIS");
3331 void process_cpuid()
3333 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
3334 unsigned int fms, family, model, stepping;
3336 eax = ebx = ecx = edx = 0;
3338 __cpuid(0, max_level, ebx, ecx, edx);
3340 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3344 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
3345 (char *)&ebx, (char *)&edx, (char *)&ecx);
3347 __cpuid(1, fms, ebx, ecx, edx);
3348 family = (fms >> 8) & 0xf;
3349 model = (fms >> 4) & 0xf;
3350 stepping = fms & 0xf;
3351 if (family == 6 || family == 0xf)
3352 model += ((fms >> 16) & 0xf) << 4;
3355 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
3356 max_level, family, model, stepping, family, model, stepping);
3357 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
3358 ecx & (1 << 0) ? "SSE3" : "-",
3359 ecx & (1 << 3) ? "MONITOR" : "-",
3360 ecx & (1 << 6) ? "SMX" : "-",
3361 ecx & (1 << 7) ? "EIST" : "-",
3362 ecx & (1 << 8) ? "TM2" : "-",
3363 edx & (1 << 4) ? "TSC" : "-",
3364 edx & (1 << 5) ? "MSR" : "-",
3365 edx & (1 << 22) ? "ACPI-TM" : "-",
3366 edx & (1 << 29) ? "TM" : "-");
3369 if (!(edx & (1 << 5)))
3370 errx(1, "CPUID: no MSR");
3373 * check max extended function levels of CPUID.
3374 * This is needed to check for invariant TSC.
3375 * This check is valid for both Intel and AMD.
3377 ebx = ecx = edx = 0;
3378 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
3380 if (max_extended_level >= 0x80000007) {
3383 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3384 * this check is valid for both Intel and AMD
3386 __cpuid(0x80000007, eax, ebx, ecx, edx);
3387 has_invariant_tsc = edx & (1 << 8);
3391 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3392 * this check is valid for both Intel and AMD
3395 __cpuid(0x6, eax, ebx, ecx, edx);
3396 has_aperf = ecx & (1 << 0);
3397 do_dts = eax & (1 << 0);
3398 do_ptm = eax & (1 << 6);
3399 has_hwp = eax & (1 << 7);
3400 has_hwp_notify = eax & (1 << 8);
3401 has_hwp_activity_window = eax & (1 << 9);
3402 has_hwp_epp = eax & (1 << 10);
3403 has_hwp_pkg = eax & (1 << 11);
3404 has_epb = ecx & (1 << 3);
3407 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
3408 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3409 has_aperf ? "" : "No-",
3410 do_dts ? "" : "No-",
3411 do_ptm ? "" : "No-",
3412 has_hwp ? "" : "No-",
3413 has_hwp_notify ? "" : "No-",
3414 has_hwp_activity_window ? "" : "No-",
3415 has_hwp_epp ? "" : "No-",
3416 has_hwp_pkg ? "" : "No-",
3417 has_epb ? "" : "No-");
3420 decode_misc_enable_msr();
3422 if (max_level >= 0x7 && debug) {
3427 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
3429 has_sgx = ebx & (1 << 2);
3430 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
3433 decode_feature_control_msr();
3436 if (max_level >= 0x15) {
3437 unsigned int eax_crystal;
3438 unsigned int ebx_tsc;
3441 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3443 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
3444 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
3448 if (debug && (ebx != 0))
3449 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
3450 eax_crystal, ebx_tsc, crystal_hz);
3452 if (crystal_hz == 0)
3454 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3455 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3456 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3457 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3458 crystal_hz = 24000000; /* 24.0 MHz */
3460 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3461 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3462 crystal_hz = 25000000; /* 25.0 MHz */
3464 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3465 crystal_hz = 19200000; /* 19.2 MHz */
3472 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
3474 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
3475 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
3479 if (max_level >= 0x16) {
3480 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3483 * CPUID 16H Base MHz, Max MHz, Bus MHz
3485 base_mhz = max_mhz = bus_mhz = edx = 0;
3487 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
3489 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
3490 base_mhz, max_mhz, bus_mhz);
3494 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3496 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model);
3497 do_snb_cstates = has_snb_msrs(family, model);
3498 do_irtl_snb = has_snb_msrs(family, model);
3499 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3500 do_pc3 = (pkg_cstate_limit >= PCL__3);
3501 do_pc6 = (pkg_cstate_limit >= PCL__6);
3502 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
3503 do_c8_c9_c10 = has_hsw_msrs(family, model);
3504 do_irtl_hsw = has_hsw_msrs(family, model);
3505 do_skl_residency = has_skl_msrs(family, model);
3506 do_slm_cstates = is_slm(family, model);
3507 do_knl_cstates = is_knl(family, model);
3510 decode_misc_pwr_mgmt_msr();
3512 rapl_probe(family, model);
3513 perf_limit_reasons_probe(family, model);
3516 dump_cstate_pstate_config_info(family, model);
3518 if (has_skl_msrs(family, model))
3519 calculate_tsc_tweak();
3521 do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK);
3523 do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK);
3531 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
3533 "Turbostat forks the specified COMMAND and prints statistics\n"
3534 "when COMMAND completes.\n"
3535 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
3536 "to print statistics, until interrupted.\n"
3537 "--add add a counter\n"
3538 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
3539 "--debug run in \"debug\" mode\n"
3540 "--interval sec Override default 5-second measurement interval\n"
3541 "--help print this help message\n"
3542 "--out file create or truncate \"file\" for all output\n"
3543 "--version print version information\n"
3545 "For more help, run \"man turbostat\"\n");
3550 * in /dev/cpu/ return success for names that are numbers
3551 * ie. filter out ".", "..", "microcode".
3553 int dir_filter(const struct dirent *dirp)
3555 if (isdigit(dirp->d_name[0]))
3561 int open_dev_cpu_msr(int dummy1)
3566 void topology_probe()
3569 int max_core_id = 0;
3570 int max_package_id = 0;
3571 int max_siblings = 0;
3572 struct cpu_topology {
3574 int physical_package_id;
3577 /* Initialize num_cpus, max_cpu_num */
3579 topo.max_cpu_num = 0;
3580 for_all_proc_cpus(count_cpus);
3581 if (!summary_only && topo.num_cpus > 1)
3585 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
3587 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
3589 err(1, "calloc cpus");
3592 * Allocate and initialize cpu_present_set
3594 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
3595 if (cpu_present_set == NULL)
3596 err(3, "CPU_ALLOC");
3597 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3598 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3599 for_all_proc_cpus(mark_cpu_present);
3602 * Allocate and initialize cpu_affinity_set
3604 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
3605 if (cpu_affinity_set == NULL)
3606 err(3, "CPU_ALLOC");
3607 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3608 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3613 * find max_core_id, max_package_id
3615 for (i = 0; i <= topo.max_cpu_num; ++i) {
3618 if (cpu_is_not_present(i)) {
3620 fprintf(outf, "cpu%d NOT PRESENT\n", i);
3623 cpus[i].core_id = get_core_id(i);
3624 if (cpus[i].core_id > max_core_id)
3625 max_core_id = cpus[i].core_id;
3627 cpus[i].physical_package_id = get_physical_package_id(i);
3628 if (cpus[i].physical_package_id > max_package_id)
3629 max_package_id = cpus[i].physical_package_id;
3631 siblings = get_num_ht_siblings(i);
3632 if (siblings > max_siblings)
3633 max_siblings = siblings;
3635 fprintf(outf, "cpu %d pkg %d core %d\n",
3636 i, cpus[i].physical_package_id, cpus[i].core_id);
3638 topo.num_cores_per_pkg = max_core_id + 1;
3640 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
3641 max_core_id, topo.num_cores_per_pkg);
3642 if (debug && !summary_only && topo.num_cores_per_pkg > 1)
3645 topo.num_packages = max_package_id + 1;
3647 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
3648 max_package_id, topo.num_packages);
3649 if (debug && !summary_only && topo.num_packages > 1)
3652 topo.num_threads_per_core = max_siblings;
3654 fprintf(outf, "max_siblings %d\n", max_siblings);
3660 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3664 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
3665 topo.num_packages, sizeof(struct thread_data) + sys.thread_counter_bytes);
3669 for (i = 0; i < topo.num_threads_per_core *
3670 topo.num_cores_per_pkg * topo.num_packages; i++)
3671 (*t)[i].cpu_id = -1;
3673 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
3674 sizeof(struct core_data) + sys.core_counter_bytes);
3678 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
3679 (*c)[i].core_id = -1;
3681 *p = calloc(topo.num_packages, sizeof(struct pkg_data) + sys.package_counter_bytes);
3685 for (i = 0; i < topo.num_packages; i++)
3686 (*p)[i].package_id = i;
3690 err(1, "calloc counters");
3695 * set cpu_id, core_num, pkg_num
3696 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
3698 * increment topo.num_cores when 1st core in pkg seen
3700 void init_counter(struct thread_data *thread_base, struct core_data *core_base,
3701 struct pkg_data *pkg_base, int thread_num, int core_num,
3702 int pkg_num, int cpu_id)
3704 struct thread_data *t;
3705 struct core_data *c;
3708 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
3709 c = GET_CORE(core_base, core_num, pkg_num);
3710 p = GET_PKG(pkg_base, pkg_num);
3713 if (thread_num == 0) {
3714 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
3715 if (cpu_is_first_core_in_package(cpu_id))
3716 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
3719 c->core_id = core_num;
3720 p->package_id = pkg_num;
3724 int initialize_counters(int cpu_id)
3726 int my_thread_id, my_core_id, my_package_id;
3728 my_package_id = get_physical_package_id(cpu_id);
3729 my_core_id = get_core_id(cpu_id);
3730 my_thread_id = get_cpu_position_in_core(cpu_id);
3734 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3735 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3739 void allocate_output_buffer()
3741 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
3742 outp = output_buffer;
3744 err(-1, "calloc output buffer");
3746 void allocate_fd_percpu(void)
3748 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
3749 if (fd_percpu == NULL)
3750 err(-1, "calloc fd_percpu");
3752 void allocate_irq_buffers(void)
3754 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
3755 if (irq_column_2_cpu == NULL)
3756 err(-1, "calloc %d", topo.num_cpus);
3758 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
3759 if (irqs_per_cpu == NULL)
3760 err(-1, "calloc %d", topo.max_cpu_num + 1);
3762 void setup_all_buffers(void)
3765 allocate_irq_buffers();
3766 allocate_fd_percpu();
3767 allocate_counters(&thread_even, &core_even, &package_even);
3768 allocate_counters(&thread_odd, &core_odd, &package_odd);
3769 allocate_output_buffer();
3770 for_all_proc_cpus(initialize_counters);
3773 void set_base_cpu(void)
3775 base_cpu = sched_getcpu();
3777 err(-ENODEV, "No valid cpus found");
3780 fprintf(outf, "base_cpu = %d\n", base_cpu);
3783 void turbostat_init()
3785 setup_all_buffers();
3788 check_permissions();
3793 for_all_cpus(print_hwp, ODD_COUNTERS);
3796 for_all_cpus(print_epb, ODD_COUNTERS);
3799 for_all_cpus(print_perf_limit, ODD_COUNTERS);
3802 for_all_cpus(print_rapl, ODD_COUNTERS);
3804 for_all_cpus(set_temperature_target, ODD_COUNTERS);
3807 for_all_cpus(print_thermal, ODD_COUNTERS);
3809 if (debug && do_irtl_snb)
3813 int fork_it(char **argv)
3818 status = for_all_cpus(get_counters, EVEN_COUNTERS);
3821 /* clear affinity side-effect of get_counters() */
3822 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
3823 gettimeofday(&tv_even, (struct timezone *)NULL);
3828 execvp(argv[0], argv);
3832 if (child_pid == -1)
3835 signal(SIGINT, SIG_IGN);
3836 signal(SIGQUIT, SIG_IGN);
3837 if (waitpid(child_pid, &status, 0) == -1)
3838 err(status, "waitpid");
3841 * n.b. fork_it() does not check for errors from for_all_cpus()
3842 * because re-starting is problematic when forking
3844 for_all_cpus(get_counters, ODD_COUNTERS);
3845 gettimeofday(&tv_odd, (struct timezone *)NULL);
3846 timersub(&tv_odd, &tv_even, &tv_delta);
3847 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
3848 fprintf(outf, "%s: Counter reset detected\n", progname);
3850 compute_average(EVEN_COUNTERS);
3851 format_all_counters(EVEN_COUNTERS);
3854 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
3856 flush_output_stderr();
3861 int get_and_dump_counters(void)
3865 status = for_all_cpus(get_counters, ODD_COUNTERS);
3869 status = for_all_cpus(dump_counters, ODD_COUNTERS);
3873 flush_output_stdout();
3878 void print_version() {
3879 fprintf(outf, "turbostat version 4.16 24 Dec 2016"
3880 " - Len Brown <lenb@kernel.org>\n");
3883 int add_counter(unsigned int msr_num, char *name, unsigned int width,
3884 enum counter_scope scope, enum counter_type type,
3885 enum counter_format format)
3887 struct msr_counter *msrp;
3889 msrp = calloc(1, sizeof(struct msr_counter));
3895 msrp->msr_num = msr_num;
3896 strncpy(msrp->name, name, NAME_BYTES);
3897 msrp->width = width;
3899 msrp->format = format;
3904 sys.thread_counter_bytes += 64;
3905 msrp->next = sys.tp;
3907 sys.thread_counter_bytes += sizeof(unsigned long long);
3911 sys.core_counter_bytes += 64;
3912 msrp->next = sys.cp;
3914 sys.core_counter_bytes += sizeof(unsigned long long);
3918 sys.package_counter_bytes += 64;
3919 msrp->next = sys.pp;
3921 sys.package_counter_bytes += sizeof(unsigned long long);
3928 void parse_add_command(char *add_command)
3931 char name_buffer[NAME_BYTES];
3934 enum counter_scope scope = SCOPE_CPU;
3935 enum counter_type type = COUNTER_CYCLES;
3936 enum counter_format format = FORMAT_DELTA;
3938 while (add_command) {
3940 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
3943 if (sscanf(add_command, "msr%d", &msr_num) == 1)
3946 if (sscanf(add_command, "u%d", &width) == 1) {
3947 if ((width == 32) || (width == 64))
3951 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
3955 if (!strncmp(add_command, "core", strlen("core"))) {
3959 if (!strncmp(add_command, "package", strlen("package"))) {
3960 scope = SCOPE_PACKAGE;
3963 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
3964 type = COUNTER_CYCLES;
3967 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
3968 type = COUNTER_SECONDS;
3971 if (!strncmp(add_command, "raw", strlen("raw"))) {
3972 format = FORMAT_RAW;
3975 if (!strncmp(add_command, "delta", strlen("delta"))) {
3976 format = FORMAT_DELTA;
3979 if (!strncmp(add_command, "percent", strlen("percent"))) {
3980 format = FORMAT_PERCENT;
3984 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
3987 eos = strchr(name_buffer, ',');
3994 add_command = strchr(add_command, ',');
4000 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n");
4004 /* generate default column header */
4005 if (*name_buffer == '\0') {
4006 if (format == FORMAT_RAW) {
4008 sprintf(name_buffer, "msr%d", msr_num);
4010 sprintf(name_buffer, "MSR%d", msr_num);
4011 } else if (format == FORMAT_DELTA) {
4013 sprintf(name_buffer, "cnt%d", msr_num);
4015 sprintf(name_buffer, "CNT%d", msr_num);
4016 } else if (format == FORMAT_PERCENT) {
4018 sprintf(name_buffer, "msr%d%%", msr_num);
4020 sprintf(name_buffer, "MSR%d%%", msr_num);
4024 if (add_counter(msr_num, name_buffer, width, scope, type, format))
4032 void cmdline(int argc, char **argv)
4035 int option_index = 0;
4036 static struct option long_options[] = {
4037 {"add", required_argument, 0, 'a'},
4038 {"Dump", no_argument, 0, 'D'},
4039 {"debug", no_argument, 0, 'd'},
4040 {"interval", required_argument, 0, 'i'},
4041 {"help", no_argument, 0, 'h'},
4042 {"Joules", no_argument, 0, 'J'},
4043 {"out", required_argument, 0, 'o'},
4044 {"Package", no_argument, 0, 'p'},
4045 {"processor", no_argument, 0, 'p'},
4046 {"Summary", no_argument, 0, 'S'},
4047 {"TCC", required_argument, 0, 'T'},
4048 {"version", no_argument, 0, 'v' },
4054 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
4055 long_options, &option_index)) != -1) {
4058 parse_add_command(optarg);
4072 double interval = strtod(optarg, NULL);
4074 if (interval < 0.001) {
4075 fprintf(outf, "interval %f seconds is too small\n",
4080 interval_ts.tv_sec = interval;
4081 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
4088 outf = fopen_or_die(optarg, "w");
4100 tcc_activation_temp_override = atoi(optarg);
4110 int main(int argc, char **argv)
4114 cmdline(argc, argv);
4121 /* dump counters and exit */
4123 return get_and_dump_counters();
4126 * if any params left, it must be a command to fork
4129 return fork_it(argv + optind);