1 // SPDX-License-Identifier: GPL-2.0-only
3 * turbostat -- show CPU frequency and C-state residency
4 * on modern Intel and AMD processors.
6 * Copyright (c) 2023 Intel Corporation.
7 * Len Brown <len.brown@intel.com>
12 #include INTEL_FAMILY_HEADER
17 #include <sys/types.h>
20 #include <sys/select.h>
21 #include <sys/resource.h>
33 #include <sys/capability.h>
36 #include <linux/perf_event.h>
37 #include <asm/unistd.h>
40 #define UNUSED(x) (void)(x)
43 * This list matches the column headers, except
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
45 * 2. Core and CPU are moved to the end, we can't have strings that contain them
46 * matching on them for --show and --hide.
50 * buffer size used by sscanf() for added column names
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
54 #define PATH_BYTES 128
56 enum counter_scope { SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE };
57 enum counter_type { COUNTER_ITEMS, COUNTER_CYCLES, COUNTER_SECONDS, COUNTER_USEC };
58 enum counter_format { FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT };
62 char name[NAME_BYTES];
63 char path[PATH_BYTES];
65 enum counter_type type;
66 enum counter_format format;
67 struct msr_counter *next;
69 #define FLAGS_HIDE (1 << 0)
70 #define FLAGS_SHOW (1 << 1)
71 #define SYSFS_PERCPU (1 << 1)
74 struct msr_counter bic[] = {
75 { 0x0, "usec", "", 0, 0, 0, NULL, 0 },
76 { 0x0, "Time_Of_Day_Seconds", "", 0, 0, 0, NULL, 0 },
77 { 0x0, "Package", "", 0, 0, 0, NULL, 0 },
78 { 0x0, "Node", "", 0, 0, 0, NULL, 0 },
79 { 0x0, "Avg_MHz", "", 0, 0, 0, NULL, 0 },
80 { 0x0, "Busy%", "", 0, 0, 0, NULL, 0 },
81 { 0x0, "Bzy_MHz", "", 0, 0, 0, NULL, 0 },
82 { 0x0, "TSC_MHz", "", 0, 0, 0, NULL, 0 },
83 { 0x0, "IRQ", "", 0, 0, 0, NULL, 0 },
84 { 0x0, "SMI", "", 32, 0, FORMAT_DELTA, NULL, 0 },
85 { 0x0, "sysfs", "", 0, 0, 0, NULL, 0 },
86 { 0x0, "CPU%c1", "", 0, 0, 0, NULL, 0 },
87 { 0x0, "CPU%c3", "", 0, 0, 0, NULL, 0 },
88 { 0x0, "CPU%c6", "", 0, 0, 0, NULL, 0 },
89 { 0x0, "CPU%c7", "", 0, 0, 0, NULL, 0 },
90 { 0x0, "ThreadC", "", 0, 0, 0, NULL, 0 },
91 { 0x0, "CoreTmp", "", 0, 0, 0, NULL, 0 },
92 { 0x0, "CoreCnt", "", 0, 0, 0, NULL, 0 },
93 { 0x0, "PkgTmp", "", 0, 0, 0, NULL, 0 },
94 { 0x0, "GFX%rc6", "", 0, 0, 0, NULL, 0 },
95 { 0x0, "GFXMHz", "", 0, 0, 0, NULL, 0 },
96 { 0x0, "Pkg%pc2", "", 0, 0, 0, NULL, 0 },
97 { 0x0, "Pkg%pc3", "", 0, 0, 0, NULL, 0 },
98 { 0x0, "Pkg%pc6", "", 0, 0, 0, NULL, 0 },
99 { 0x0, "Pkg%pc7", "", 0, 0, 0, NULL, 0 },
100 { 0x0, "Pkg%pc8", "", 0, 0, 0, NULL, 0 },
101 { 0x0, "Pkg%pc9", "", 0, 0, 0, NULL, 0 },
102 { 0x0, "Pk%pc10", "", 0, 0, 0, NULL, 0 },
103 { 0x0, "CPU%LPI", "", 0, 0, 0, NULL, 0 },
104 { 0x0, "SYS%LPI", "", 0, 0, 0, NULL, 0 },
105 { 0x0, "PkgWatt", "", 0, 0, 0, NULL, 0 },
106 { 0x0, "CorWatt", "", 0, 0, 0, NULL, 0 },
107 { 0x0, "GFXWatt", "", 0, 0, 0, NULL, 0 },
108 { 0x0, "PkgCnt", "", 0, 0, 0, NULL, 0 },
109 { 0x0, "RAMWatt", "", 0, 0, 0, NULL, 0 },
110 { 0x0, "PKG_%", "", 0, 0, 0, NULL, 0 },
111 { 0x0, "RAM_%", "", 0, 0, 0, NULL, 0 },
112 { 0x0, "Pkg_J", "", 0, 0, 0, NULL, 0 },
113 { 0x0, "Cor_J", "", 0, 0, 0, NULL, 0 },
114 { 0x0, "GFX_J", "", 0, 0, 0, NULL, 0 },
115 { 0x0, "RAM_J", "", 0, 0, 0, NULL, 0 },
116 { 0x0, "Mod%c6", "", 0, 0, 0, NULL, 0 },
117 { 0x0, "Totl%C0", "", 0, 0, 0, NULL, 0 },
118 { 0x0, "Any%C0", "", 0, 0, 0, NULL, 0 },
119 { 0x0, "GFX%C0", "", 0, 0, 0, NULL, 0 },
120 { 0x0, "CPUGFX%", "", 0, 0, 0, NULL, 0 },
121 { 0x0, "Core", "", 0, 0, 0, NULL, 0 },
122 { 0x0, "CPU", "", 0, 0, 0, NULL, 0 },
123 { 0x0, "APIC", "", 0, 0, 0, NULL, 0 },
124 { 0x0, "X2APIC", "", 0, 0, 0, NULL, 0 },
125 { 0x0, "Die", "", 0, 0, 0, NULL, 0 },
126 { 0x0, "GFXAMHz", "", 0, 0, 0, NULL, 0 },
127 { 0x0, "IPC", "", 0, 0, 0, NULL, 0 },
128 { 0x0, "CoreThr", "", 0, 0, 0, NULL, 0 },
129 { 0x0, "UncMHz", "", 0, 0, 0, NULL, 0 },
132 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
133 #define BIC_USEC (1ULL << 0)
134 #define BIC_TOD (1ULL << 1)
135 #define BIC_Package (1ULL << 2)
136 #define BIC_Node (1ULL << 3)
137 #define BIC_Avg_MHz (1ULL << 4)
138 #define BIC_Busy (1ULL << 5)
139 #define BIC_Bzy_MHz (1ULL << 6)
140 #define BIC_TSC_MHz (1ULL << 7)
141 #define BIC_IRQ (1ULL << 8)
142 #define BIC_SMI (1ULL << 9)
143 #define BIC_sysfs (1ULL << 10)
144 #define BIC_CPU_c1 (1ULL << 11)
145 #define BIC_CPU_c3 (1ULL << 12)
146 #define BIC_CPU_c6 (1ULL << 13)
147 #define BIC_CPU_c7 (1ULL << 14)
148 #define BIC_ThreadC (1ULL << 15)
149 #define BIC_CoreTmp (1ULL << 16)
150 #define BIC_CoreCnt (1ULL << 17)
151 #define BIC_PkgTmp (1ULL << 18)
152 #define BIC_GFX_rc6 (1ULL << 19)
153 #define BIC_GFXMHz (1ULL << 20)
154 #define BIC_Pkgpc2 (1ULL << 21)
155 #define BIC_Pkgpc3 (1ULL << 22)
156 #define BIC_Pkgpc6 (1ULL << 23)
157 #define BIC_Pkgpc7 (1ULL << 24)
158 #define BIC_Pkgpc8 (1ULL << 25)
159 #define BIC_Pkgpc9 (1ULL << 26)
160 #define BIC_Pkgpc10 (1ULL << 27)
161 #define BIC_CPU_LPI (1ULL << 28)
162 #define BIC_SYS_LPI (1ULL << 29)
163 #define BIC_PkgWatt (1ULL << 30)
164 #define BIC_CorWatt (1ULL << 31)
165 #define BIC_GFXWatt (1ULL << 32)
166 #define BIC_PkgCnt (1ULL << 33)
167 #define BIC_RAMWatt (1ULL << 34)
168 #define BIC_PKG__ (1ULL << 35)
169 #define BIC_RAM__ (1ULL << 36)
170 #define BIC_Pkg_J (1ULL << 37)
171 #define BIC_Cor_J (1ULL << 38)
172 #define BIC_GFX_J (1ULL << 39)
173 #define BIC_RAM_J (1ULL << 40)
174 #define BIC_Mod_c6 (1ULL << 41)
175 #define BIC_Totl_c0 (1ULL << 42)
176 #define BIC_Any_c0 (1ULL << 43)
177 #define BIC_GFX_c0 (1ULL << 44)
178 #define BIC_CPUGFX (1ULL << 45)
179 #define BIC_Core (1ULL << 46)
180 #define BIC_CPU (1ULL << 47)
181 #define BIC_APIC (1ULL << 48)
182 #define BIC_X2APIC (1ULL << 49)
183 #define BIC_Die (1ULL << 50)
184 #define BIC_GFXACTMHz (1ULL << 51)
185 #define BIC_IPC (1ULL << 52)
186 #define BIC_CORE_THROT_CNT (1ULL << 53)
187 #define BIC_UNCORE_MHZ (1ULL << 54)
189 #define BIC_TOPOLOGY (BIC_Package | BIC_Node | BIC_CoreCnt | BIC_PkgCnt | BIC_Core | BIC_CPU | BIC_Die )
190 #define BIC_THERMAL_PWR ( BIC_CoreTmp | BIC_PkgTmp | BIC_PkgWatt | BIC_CorWatt | BIC_GFXWatt | BIC_RAMWatt | BIC_PKG__ | BIC_RAM__)
191 #define BIC_FREQUENCY ( BIC_Avg_MHz | BIC_Busy | BIC_Bzy_MHz | BIC_TSC_MHz | BIC_GFXMHz | BIC_GFXACTMHz | BIC_UNCORE_MHZ)
192 #define BIC_IDLE ( BIC_sysfs | BIC_CPU_c1 | BIC_CPU_c3 | BIC_CPU_c6 | BIC_CPU_c7 | BIC_GFX_rc6 | BIC_Pkgpc2 | BIC_Pkgpc3 | BIC_Pkgpc6 | BIC_Pkgpc7 | BIC_Pkgpc8 | BIC_Pkgpc9 | BIC_Pkgpc10 | BIC_CPU_LPI | BIC_SYS_LPI | BIC_Mod_c6 | BIC_Totl_c0 | BIC_Any_c0 | BIC_GFX_c0 | BIC_CPUGFX)
193 #define BIC_OTHER ( BIC_IRQ | BIC_SMI | BIC_ThreadC | BIC_CoreTmp | BIC_IPC)
195 #define BIC_DISABLED_BY_DEFAULT (BIC_USEC | BIC_TOD | BIC_APIC | BIC_X2APIC)
197 unsigned long long bic_enabled = (0xFFFFFFFFFFFFFFFFULL & ~BIC_DISABLED_BY_DEFAULT);
198 unsigned long long bic_present = BIC_USEC | BIC_TOD | BIC_sysfs | BIC_APIC | BIC_X2APIC;
200 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
201 #define DO_BIC_READ(COUNTER_NAME) (bic_present & COUNTER_NAME)
202 #define ENABLE_BIC(COUNTER_NAME) (bic_enabled |= COUNTER_NAME)
203 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
204 #define BIC_NOT_PRESENT(COUNTER_BIT) (bic_present &= ~COUNTER_BIT)
205 #define BIC_IS_ENABLED(COUNTER_BIT) (bic_enabled & COUNTER_BIT)
207 char *proc_stat = "/proc/stat";
210 int *fd_instr_count_percpu;
211 struct timeval interval_tv = { 5, 0 };
212 struct timespec interval_ts = { 5, 0 };
214 /* Save original CPU model */
215 unsigned int model_orig;
217 unsigned int num_iterations;
218 unsigned int header_iterations;
222 unsigned int sums_need_wide_columns;
223 unsigned int rapl_joules;
224 unsigned int summary_only;
225 unsigned int list_header_only;
226 unsigned int dump_only;
227 unsigned int do_snb_cstates;
228 unsigned int do_knl_cstates;
229 unsigned int do_slm_cstates;
230 unsigned int use_c1_residency_msr;
231 unsigned int has_aperf;
232 unsigned int has_epb;
233 unsigned int has_turbo;
234 unsigned int is_hybrid;
235 unsigned int do_irtl_snb;
236 unsigned int do_irtl_hsw;
237 unsigned int units = 1000000; /* MHz etc */
238 unsigned int genuine_intel;
239 unsigned int authentic_amd;
240 unsigned int hygon_genuine;
241 unsigned int max_level, max_extended_level;
242 unsigned int has_invariant_tsc;
243 unsigned int do_nhm_platform_info;
244 unsigned int no_MSR_MISC_PWR_MGMT;
245 unsigned int aperf_mperf_multiplier = 1;
248 unsigned int has_base_hz;
249 double tsc_tweak = 1.0;
250 unsigned int show_pkg_only;
251 unsigned int show_core_only;
252 char *output_buffer, *outp;
253 unsigned int do_rapl;
257 unsigned long long gfx_cur_rc6_ms;
258 unsigned long long cpuidle_cur_cpu_lpi_us;
259 unsigned long long cpuidle_cur_sys_lpi_us;
260 unsigned int gfx_cur_mhz;
261 unsigned int gfx_act_mhz;
263 unsigned int tj_max_override;
265 double rapl_power_units, rapl_time_units;
266 double rapl_dram_energy_units, rapl_energy_units;
267 double rapl_joule_counter_range;
268 unsigned int do_core_perf_limit_reasons;
269 unsigned int has_automatic_cstate_conversion;
270 unsigned int dis_cstate_prewake;
271 unsigned int do_gfx_perf_limit_reasons;
272 unsigned int do_ring_perf_limit_reasons;
273 unsigned int crystal_hz;
274 unsigned long long tsc_hz;
276 double discover_bclk(unsigned int family, unsigned int model);
277 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
278 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
279 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
280 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
281 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
282 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
283 unsigned int has_misc_feature_control;
284 unsigned int first_counter_read = 1;
287 #define RAPL_PKG (1 << 0)
288 /* 0x610 MSR_PKG_POWER_LIMIT */
289 /* 0x611 MSR_PKG_ENERGY_STATUS */
290 #define RAPL_PKG_PERF_STATUS (1 << 1)
291 /* 0x613 MSR_PKG_PERF_STATUS */
292 #define RAPL_PKG_POWER_INFO (1 << 2)
293 /* 0x614 MSR_PKG_POWER_INFO */
295 #define RAPL_DRAM (1 << 3)
296 /* 0x618 MSR_DRAM_POWER_LIMIT */
297 /* 0x619 MSR_DRAM_ENERGY_STATUS */
298 #define RAPL_DRAM_PERF_STATUS (1 << 4)
299 /* 0x61b MSR_DRAM_PERF_STATUS */
300 #define RAPL_DRAM_POWER_INFO (1 << 5)
301 /* 0x61c MSR_DRAM_POWER_INFO */
303 #define RAPL_CORES_POWER_LIMIT (1 << 6)
304 /* 0x638 MSR_PP0_POWER_LIMIT */
305 #define RAPL_CORE_POLICY (1 << 7)
306 /* 0x63a MSR_PP0_POLICY */
308 #define RAPL_GFX (1 << 8)
309 /* 0x640 MSR_PP1_POWER_LIMIT */
310 /* 0x641 MSR_PP1_ENERGY_STATUS */
311 /* 0x642 MSR_PP1_POLICY */
313 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
314 /* 0x639 MSR_PP0_ENERGY_STATUS */
315 #define RAPL_PER_CORE_ENERGY (1 << 10)
316 /* Indicates cores energy collection is per-core,
317 * not per-package. */
318 #define RAPL_AMD_F17H (1 << 11)
319 /* 0xc0010299 MSR_RAPL_PWR_UNIT */
320 /* 0xc001029a MSR_CORE_ENERGY_STAT */
321 /* 0xc001029b MSR_PKG_ENERGY_STAT */
322 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
323 #define TJMAX_DEFAULT 100
325 /* MSRs that are not yet in the kernel-provided header. */
326 #define MSR_RAPL_PWR_UNIT 0xc0010299
327 #define MSR_CORE_ENERGY_STAT 0xc001029a
328 #define MSR_PKG_ENERGY_STAT 0xc001029b
330 #define MAX(a, b) ((a) > (b) ? (a) : (b))
335 #define CPU_SUBSET_MAXCPUS 1024 /* need to use before probe... */
336 cpu_set_t *cpu_present_set, *cpu_affinity_set, *cpu_subset;
337 size_t cpu_present_setsize, cpu_affinity_setsize, cpu_subset_size;
338 #define MAX_ADDED_COUNTERS 8
339 #define MAX_ADDED_THREAD_COUNTERS 24
340 #define BITMASK_SIZE 32
343 struct timeval tv_begin;
344 struct timeval tv_end;
345 struct timeval tv_delta;
346 unsigned long long tsc;
347 unsigned long long aperf;
348 unsigned long long mperf;
349 unsigned long long c1;
350 unsigned long long instr_count;
351 unsigned long long irq_count;
352 unsigned int smi_count;
354 unsigned int apic_id;
355 unsigned int x2apic_id;
358 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
359 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
360 unsigned long long counter[MAX_ADDED_THREAD_COUNTERS];
361 } *thread_even, *thread_odd;
364 unsigned long long c3;
365 unsigned long long c6;
366 unsigned long long c7;
367 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
368 unsigned int core_temp_c;
369 unsigned int core_energy; /* MSR_CORE_ENERGY_STAT */
370 unsigned int core_id;
371 unsigned long long core_throt_cnt;
372 unsigned long long counter[MAX_ADDED_COUNTERS];
373 } *core_even, *core_odd;
376 unsigned long long pc2;
377 unsigned long long pc3;
378 unsigned long long pc6;
379 unsigned long long pc7;
380 unsigned long long pc8;
381 unsigned long long pc9;
382 unsigned long long pc10;
383 unsigned long long cpu_lpi;
384 unsigned long long sys_lpi;
385 unsigned long long pkg_wtd_core_c0;
386 unsigned long long pkg_any_core_c0;
387 unsigned long long pkg_any_gfxe_c0;
388 unsigned long long pkg_both_core_gfxe_c0;
389 long long gfx_rc6_ms;
390 unsigned int gfx_mhz;
391 unsigned int gfx_act_mhz;
392 unsigned int package_id;
393 unsigned long long energy_pkg; /* MSR_PKG_ENERGY_STATUS */
394 unsigned long long energy_dram; /* MSR_DRAM_ENERGY_STATUS */
395 unsigned long long energy_cores; /* MSR_PP0_ENERGY_STATUS */
396 unsigned long long energy_gfx; /* MSR_PP1_ENERGY_STATUS */
397 unsigned long long rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
398 unsigned long long rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
399 unsigned int pkg_temp_c;
400 unsigned int uncore_mhz;
401 unsigned long long counter[MAX_ADDED_COUNTERS];
402 } *package_even, *package_odd;
404 #define ODD_COUNTERS thread_odd, core_odd, package_odd
405 #define EVEN_COUNTERS thread_even, core_even, package_even
407 #define GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no) \
410 topo.nodes_per_pkg * topo.cores_per_node * topo.threads_per_core) + \
411 ((node_no) * topo.cores_per_node * topo.threads_per_core) + \
412 ((core_no) * topo.threads_per_core) + \
415 #define GET_CORE(core_base, core_no, node_no, pkg_no) \
417 ((pkg_no) * topo.nodes_per_pkg * topo.cores_per_node) + \
418 ((node_no) * topo.cores_per_node) + \
421 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
424 * The accumulated sum of MSR is defined as a monotonic
425 * increasing MSR, it will be accumulated periodically,
426 * despite its register's bit width.
438 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr);
440 struct msr_sum_array {
441 /* get_msr_sum() = sum + (get_msr() - last) */
443 /*The accumulated MSR value is updated by the timer */
444 unsigned long long sum;
445 /*The MSR footprint recorded in last timer */
446 unsigned long long last;
447 } entries[IDX_COUNT];
450 /* The percpu MSR sum array.*/
451 struct msr_sum_array *per_cpu_msr_sum;
453 off_t idx_to_offset(int idx)
459 if (do_rapl & RAPL_AMD_F17H)
460 offset = MSR_PKG_ENERGY_STAT;
462 offset = MSR_PKG_ENERGY_STATUS;
464 case IDX_DRAM_ENERGY:
465 offset = MSR_DRAM_ENERGY_STATUS;
468 offset = MSR_PP0_ENERGY_STATUS;
471 offset = MSR_PP1_ENERGY_STATUS;
474 offset = MSR_PKG_PERF_STATUS;
477 offset = MSR_DRAM_PERF_STATUS;
485 int offset_to_idx(off_t offset)
490 case MSR_PKG_ENERGY_STATUS:
491 case MSR_PKG_ENERGY_STAT:
492 idx = IDX_PKG_ENERGY;
494 case MSR_DRAM_ENERGY_STATUS:
495 idx = IDX_DRAM_ENERGY;
497 case MSR_PP0_ENERGY_STATUS:
498 idx = IDX_PP0_ENERGY;
500 case MSR_PP1_ENERGY_STATUS:
501 idx = IDX_PP1_ENERGY;
503 case MSR_PKG_PERF_STATUS:
506 case MSR_DRAM_PERF_STATUS:
515 int idx_valid(int idx)
519 return do_rapl & (RAPL_PKG | RAPL_AMD_F17H);
520 case IDX_DRAM_ENERGY:
521 return do_rapl & RAPL_DRAM;
523 return do_rapl & RAPL_CORES_ENERGY_STATUS;
525 return do_rapl & RAPL_GFX;
527 return do_rapl & RAPL_PKG_PERF_STATUS;
529 return do_rapl & RAPL_DRAM_PERF_STATUS;
535 struct sys_counters {
536 unsigned int added_thread_counters;
537 unsigned int added_core_counters;
538 unsigned int added_package_counters;
539 struct msr_counter *tp;
540 struct msr_counter *cp;
541 struct msr_counter *pp;
544 struct system_summary {
545 struct thread_data threads;
546 struct core_data cores;
547 struct pkg_data packages;
550 struct cpu_topology {
551 int physical_package_id;
554 int physical_node_id;
555 int logical_node_id; /* 0-based count within the package */
556 int physical_core_id;
558 cpu_set_t *put_ids; /* Processing Unit/Thread IDs */
570 int threads_per_core;
573 struct timeval tv_even, tv_odd, tv_delta;
575 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
576 int *irqs_per_cpu; /* indexed by cpu_num */
578 void setup_all_buffers(void);
581 char *sys_lpi_file_sysfs = "/sys/devices/system/cpu/cpuidle/low_power_idle_system_residency_us";
582 char *sys_lpi_file_debugfs = "/sys/kernel/debug/pmc_core/slp_s0_residency_usec";
584 int cpu_is_not_present(int cpu)
586 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
590 * run func(thread, core, package) in topology order
591 * skip non-present cpus
594 int for_all_cpus(int (func) (struct thread_data *, struct core_data *, struct pkg_data *),
595 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
597 int retval, pkg_no, core_no, thread_no, node_no;
599 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
600 for (node_no = 0; node_no < topo.nodes_per_pkg; node_no++) {
601 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
602 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
603 struct thread_data *t;
607 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
609 if (cpu_is_not_present(t->cpu_id))
612 c = GET_CORE(core_base, core_no, node_no, pkg_no);
613 p = GET_PKG(pkg_base, pkg_no);
615 retval = func(t, c, p);
625 int cpu_migrate(int cpu)
627 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
628 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
629 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
635 int get_msr_fd(int cpu)
645 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
646 fd = open(pathname, O_RDONLY);
648 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
655 static long perf_event_open(struct perf_event_attr *hw_event, pid_t pid, int cpu, int group_fd, unsigned long flags)
657 return syscall(__NR_perf_event_open, hw_event, pid, cpu, group_fd, flags);
660 static int perf_instr_count_open(int cpu_num)
662 struct perf_event_attr pea;
665 memset(&pea, 0, sizeof(struct perf_event_attr));
666 pea.type = PERF_TYPE_HARDWARE;
667 pea.size = sizeof(struct perf_event_attr);
668 pea.config = PERF_COUNT_HW_INSTRUCTIONS;
670 /* counter for cpu_num, including user + kernel and all processes */
671 fd = perf_event_open(&pea, -1, cpu_num, -1, 0);
673 warnx("capget(CAP_PERFMON) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
674 BIC_NOT_PRESENT(BIC_IPC);
680 int get_instr_count_fd(int cpu)
682 if (fd_instr_count_percpu[cpu])
683 return fd_instr_count_percpu[cpu];
685 fd_instr_count_percpu[cpu] = perf_instr_count_open(cpu);
687 return fd_instr_count_percpu[cpu];
690 int get_msr(int cpu, off_t offset, unsigned long long *msr)
694 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
696 if (retval != sizeof *msr)
697 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
702 #define MAX_DEFERRED 16
703 char *deferred_add_names[MAX_DEFERRED];
704 char *deferred_skip_names[MAX_DEFERRED];
705 int deferred_add_index;
706 int deferred_skip_index;
709 * HIDE_LIST - hide this list of counters, show the rest [default]
710 * SHOW_LIST - show this list of counters, hide the rest
712 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
717 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
719 "Turbostat forks the specified COMMAND and prints statistics\n"
720 "when COMMAND completes.\n"
721 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
722 "to print statistics, until interrupted.\n"
723 " -a, --add add a counter\n"
724 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
725 " -c, --cpu cpu-set limit output to summary plus cpu-set:\n"
726 " {core | package | j,k,l..m,n-p }\n"
727 " -d, --debug displays usec, Time_Of_Day_Seconds and more debugging\n"
728 " -D, --Dump displays the raw counter values\n"
729 " -e, --enable [all | column]\n"
730 " shows all or the specified disabled column\n"
731 " -H, --hide [column|column,column,...]\n"
732 " hide the specified column(s)\n"
733 " -i, --interval sec.subsec\n"
734 " Override default 5-second measurement interval\n"
735 " -J, --Joules displays energy in Joules instead of Watts\n"
736 " -l, --list list column headers only\n"
737 " -n, --num_iterations num\n"
738 " number of the measurement iterations\n"
739 " -N, --header_iterations num\n"
740 " print header every num iterations\n"
742 " create or truncate \"file\" for all output\n"
743 " -q, --quiet skip decoding system configuration header\n"
744 " -s, --show [column|column,column,...]\n"
745 " show only the specified column(s)\n"
747 " limits output to 1-line system summary per interval\n"
748 " -T, --TCC temperature\n"
749 " sets the Thermal Control Circuit temperature in\n"
751 " -h, --help print this help message\n"
752 " -v, --version print version information\n" "\n" "For more help, run \"man turbostat\"\n");
757 * for all the strings in comma separate name_list,
758 * set the approprate bit in return value.
760 unsigned long long bic_lookup(char *name_list, enum show_hide_mode mode)
763 unsigned long long retval = 0;
768 comma = strchr(name_list, ',');
773 for (i = 0; i < MAX_BIC; ++i) {
774 if (!strcmp(name_list, bic[i].name)) {
775 retval |= (1ULL << i);
778 if (!strcmp(name_list, "all")) {
781 } else if (!strcmp(name_list, "topology")) {
782 retval |= BIC_TOPOLOGY;
784 } else if (!strcmp(name_list, "power")) {
785 retval |= BIC_THERMAL_PWR;
787 } else if (!strcmp(name_list, "idle")) {
790 } else if (!strcmp(name_list, "frequency")) {
791 retval |= BIC_FREQUENCY;
793 } else if (!strcmp(name_list, "other")) {
800 if (mode == SHOW_LIST) {
801 deferred_add_names[deferred_add_index++] = name_list;
802 if (deferred_add_index >= MAX_DEFERRED) {
803 fprintf(stderr, "More than max %d un-recognized --add options '%s'\n",
804 MAX_DEFERRED, name_list);
809 deferred_skip_names[deferred_skip_index++] = name_list;
811 fprintf(stderr, "deferred \"%s\"\n", name_list);
812 if (deferred_skip_index >= MAX_DEFERRED) {
813 fprintf(stderr, "More than max %d un-recognized --skip options '%s'\n",
814 MAX_DEFERRED, name_list);
829 void print_header(char *delim)
831 struct msr_counter *mp;
834 if (DO_BIC(BIC_USEC))
835 outp += sprintf(outp, "%susec", (printed++ ? delim : ""));
837 outp += sprintf(outp, "%sTime_Of_Day_Seconds", (printed++ ? delim : ""));
838 if (DO_BIC(BIC_Package))
839 outp += sprintf(outp, "%sPackage", (printed++ ? delim : ""));
841 outp += sprintf(outp, "%sDie", (printed++ ? delim : ""));
842 if (DO_BIC(BIC_Node))
843 outp += sprintf(outp, "%sNode", (printed++ ? delim : ""));
844 if (DO_BIC(BIC_Core))
845 outp += sprintf(outp, "%sCore", (printed++ ? delim : ""));
847 outp += sprintf(outp, "%sCPU", (printed++ ? delim : ""));
848 if (DO_BIC(BIC_APIC))
849 outp += sprintf(outp, "%sAPIC", (printed++ ? delim : ""));
850 if (DO_BIC(BIC_X2APIC))
851 outp += sprintf(outp, "%sX2APIC", (printed++ ? delim : ""));
852 if (DO_BIC(BIC_Avg_MHz))
853 outp += sprintf(outp, "%sAvg_MHz", (printed++ ? delim : ""));
854 if (DO_BIC(BIC_Busy))
855 outp += sprintf(outp, "%sBusy%%", (printed++ ? delim : ""));
856 if (DO_BIC(BIC_Bzy_MHz))
857 outp += sprintf(outp, "%sBzy_MHz", (printed++ ? delim : ""));
858 if (DO_BIC(BIC_TSC_MHz))
859 outp += sprintf(outp, "%sTSC_MHz", (printed++ ? delim : ""));
862 outp += sprintf(outp, "%sIPC", (printed++ ? delim : ""));
864 if (DO_BIC(BIC_IRQ)) {
865 if (sums_need_wide_columns)
866 outp += sprintf(outp, "%s IRQ", (printed++ ? delim : ""));
868 outp += sprintf(outp, "%sIRQ", (printed++ ? delim : ""));
872 outp += sprintf(outp, "%sSMI", (printed++ ? delim : ""));
874 for (mp = sys.tp; mp; mp = mp->next) {
876 if (mp->format == FORMAT_RAW) {
878 outp += sprintf(outp, "%s%18.18s", (printed++ ? delim : ""), mp->name);
880 outp += sprintf(outp, "%s%10.10s", (printed++ ? delim : ""), mp->name);
882 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
883 outp += sprintf(outp, "%s%8s", (printed++ ? delim : ""), mp->name);
885 outp += sprintf(outp, "%s%s", (printed++ ? delim : ""), mp->name);
889 if (DO_BIC(BIC_CPU_c1))
890 outp += sprintf(outp, "%sCPU%%c1", (printed++ ? delim : ""));
891 if (DO_BIC(BIC_CPU_c3))
892 outp += sprintf(outp, "%sCPU%%c3", (printed++ ? delim : ""));
893 if (DO_BIC(BIC_CPU_c6))
894 outp += sprintf(outp, "%sCPU%%c6", (printed++ ? delim : ""));
895 if (DO_BIC(BIC_CPU_c7))
896 outp += sprintf(outp, "%sCPU%%c7", (printed++ ? delim : ""));
898 if (DO_BIC(BIC_Mod_c6))
899 outp += sprintf(outp, "%sMod%%c6", (printed++ ? delim : ""));
901 if (DO_BIC(BIC_CoreTmp))
902 outp += sprintf(outp, "%sCoreTmp", (printed++ ? delim : ""));
904 if (DO_BIC(BIC_CORE_THROT_CNT))
905 outp += sprintf(outp, "%sCoreThr", (printed++ ? delim : ""));
907 if (do_rapl && !rapl_joules) {
908 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
909 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
910 } else if (do_rapl && rapl_joules) {
911 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
912 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
915 for (mp = sys.cp; mp; mp = mp->next) {
916 if (mp->format == FORMAT_RAW) {
918 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
920 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
922 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
923 outp += sprintf(outp, "%s%8s", delim, mp->name);
925 outp += sprintf(outp, "%s%s", delim, mp->name);
929 if (DO_BIC(BIC_PkgTmp))
930 outp += sprintf(outp, "%sPkgTmp", (printed++ ? delim : ""));
932 if (DO_BIC(BIC_GFX_rc6))
933 outp += sprintf(outp, "%sGFX%%rc6", (printed++ ? delim : ""));
935 if (DO_BIC(BIC_GFXMHz))
936 outp += sprintf(outp, "%sGFXMHz", (printed++ ? delim : ""));
938 if (DO_BIC(BIC_GFXACTMHz))
939 outp += sprintf(outp, "%sGFXAMHz", (printed++ ? delim : ""));
941 if (DO_BIC(BIC_Totl_c0))
942 outp += sprintf(outp, "%sTotl%%C0", (printed++ ? delim : ""));
943 if (DO_BIC(BIC_Any_c0))
944 outp += sprintf(outp, "%sAny%%C0", (printed++ ? delim : ""));
945 if (DO_BIC(BIC_GFX_c0))
946 outp += sprintf(outp, "%sGFX%%C0", (printed++ ? delim : ""));
947 if (DO_BIC(BIC_CPUGFX))
948 outp += sprintf(outp, "%sCPUGFX%%", (printed++ ? delim : ""));
950 if (DO_BIC(BIC_Pkgpc2))
951 outp += sprintf(outp, "%sPkg%%pc2", (printed++ ? delim : ""));
952 if (DO_BIC(BIC_Pkgpc3))
953 outp += sprintf(outp, "%sPkg%%pc3", (printed++ ? delim : ""));
954 if (DO_BIC(BIC_Pkgpc6))
955 outp += sprintf(outp, "%sPkg%%pc6", (printed++ ? delim : ""));
956 if (DO_BIC(BIC_Pkgpc7))
957 outp += sprintf(outp, "%sPkg%%pc7", (printed++ ? delim : ""));
958 if (DO_BIC(BIC_Pkgpc8))
959 outp += sprintf(outp, "%sPkg%%pc8", (printed++ ? delim : ""));
960 if (DO_BIC(BIC_Pkgpc9))
961 outp += sprintf(outp, "%sPkg%%pc9", (printed++ ? delim : ""));
962 if (DO_BIC(BIC_Pkgpc10))
963 outp += sprintf(outp, "%sPk%%pc10", (printed++ ? delim : ""));
964 if (DO_BIC(BIC_CPU_LPI))
965 outp += sprintf(outp, "%sCPU%%LPI", (printed++ ? delim : ""));
966 if (DO_BIC(BIC_SYS_LPI))
967 outp += sprintf(outp, "%sSYS%%LPI", (printed++ ? delim : ""));
969 if (do_rapl && !rapl_joules) {
970 if (DO_BIC(BIC_PkgWatt))
971 outp += sprintf(outp, "%sPkgWatt", (printed++ ? delim : ""));
972 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
973 outp += sprintf(outp, "%sCorWatt", (printed++ ? delim : ""));
974 if (DO_BIC(BIC_GFXWatt))
975 outp += sprintf(outp, "%sGFXWatt", (printed++ ? delim : ""));
976 if (DO_BIC(BIC_RAMWatt))
977 outp += sprintf(outp, "%sRAMWatt", (printed++ ? delim : ""));
978 if (DO_BIC(BIC_PKG__))
979 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
980 if (DO_BIC(BIC_RAM__))
981 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
982 } else if (do_rapl && rapl_joules) {
983 if (DO_BIC(BIC_Pkg_J))
984 outp += sprintf(outp, "%sPkg_J", (printed++ ? delim : ""));
985 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
986 outp += sprintf(outp, "%sCor_J", (printed++ ? delim : ""));
987 if (DO_BIC(BIC_GFX_J))
988 outp += sprintf(outp, "%sGFX_J", (printed++ ? delim : ""));
989 if (DO_BIC(BIC_RAM_J))
990 outp += sprintf(outp, "%sRAM_J", (printed++ ? delim : ""));
991 if (DO_BIC(BIC_PKG__))
992 outp += sprintf(outp, "%sPKG_%%", (printed++ ? delim : ""));
993 if (DO_BIC(BIC_RAM__))
994 outp += sprintf(outp, "%sRAM_%%", (printed++ ? delim : ""));
996 if (DO_BIC(BIC_UNCORE_MHZ))
997 outp += sprintf(outp, "%sUncMHz", (printed++ ? delim : ""));
999 for (mp = sys.pp; mp; mp = mp->next) {
1000 if (mp->format == FORMAT_RAW) {
1001 if (mp->width == 64)
1002 outp += sprintf(outp, "%s%18.18s", delim, mp->name);
1004 outp += sprintf(outp, "%s%10.10s", delim, mp->name);
1006 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1007 outp += sprintf(outp, "%s%8s", delim, mp->name);
1009 outp += sprintf(outp, "%s%s", delim, mp->name);
1013 outp += sprintf(outp, "\n");
1016 int dump_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1019 struct msr_counter *mp;
1021 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
1024 outp += sprintf(outp, "CPU: %d flags 0x%x\n", t->cpu_id, t->flags);
1025 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
1026 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
1027 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
1028 outp += sprintf(outp, "c1: %016llX\n", t->c1);
1030 if (DO_BIC(BIC_IPC))
1031 outp += sprintf(outp, "IPC: %lld\n", t->instr_count);
1033 if (DO_BIC(BIC_IRQ))
1034 outp += sprintf(outp, "IRQ: %lld\n", t->irq_count);
1035 if (DO_BIC(BIC_SMI))
1036 outp += sprintf(outp, "SMI: %d\n", t->smi_count);
1038 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1039 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, t->counter[i]);
1044 outp += sprintf(outp, "core: %d\n", c->core_id);
1045 outp += sprintf(outp, "c3: %016llX\n", c->c3);
1046 outp += sprintf(outp, "c6: %016llX\n", c->c6);
1047 outp += sprintf(outp, "c7: %016llX\n", c->c7);
1048 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
1049 outp += sprintf(outp, "cpu_throt_count: %016llX\n", c->core_throt_cnt);
1050 outp += sprintf(outp, "Joules: %0X\n", c->core_energy);
1052 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1053 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, c->counter[i]);
1055 outp += sprintf(outp, "mc6_us: %016llX\n", c->mc6_us);
1059 outp += sprintf(outp, "package: %d\n", p->package_id);
1061 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
1062 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
1063 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
1064 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
1066 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
1067 if (DO_BIC(BIC_Pkgpc3))
1068 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
1069 if (DO_BIC(BIC_Pkgpc6))
1070 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
1071 if (DO_BIC(BIC_Pkgpc7))
1072 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
1073 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
1074 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
1075 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
1076 outp += sprintf(outp, "cpu_lpi: %016llX\n", p->cpu_lpi);
1077 outp += sprintf(outp, "sys_lpi: %016llX\n", p->sys_lpi);
1078 outp += sprintf(outp, "Joules PKG: %0llX\n", p->energy_pkg);
1079 outp += sprintf(outp, "Joules COR: %0llX\n", p->energy_cores);
1080 outp += sprintf(outp, "Joules GFX: %0llX\n", p->energy_gfx);
1081 outp += sprintf(outp, "Joules RAM: %0llX\n", p->energy_dram);
1082 outp += sprintf(outp, "Throttle PKG: %0llX\n", p->rapl_pkg_perf_status);
1083 outp += sprintf(outp, "Throttle RAM: %0llX\n", p->rapl_dram_perf_status);
1084 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
1086 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1087 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n", i, mp->msr_num, p->counter[i]);
1091 outp += sprintf(outp, "\n");
1097 * column formatting convention & formats
1099 int format_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1101 double interval_float, tsc;
1104 struct msr_counter *mp;
1108 /* if showing only 1st thread in core and this isn't one, bail out */
1109 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1112 /* if showing only 1st thread in pkg and this isn't one, bail out */
1113 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1116 /*if not summary line and --cpu is used */
1117 if ((t != &average.threads) && (cpu_subset && !CPU_ISSET_S(t->cpu_id, cpu_subset_size, cpu_subset)))
1120 if (DO_BIC(BIC_USEC)) {
1121 /* on each row, print how many usec each timestamp took to gather */
1124 timersub(&t->tv_end, &t->tv_begin, &tv);
1125 outp += sprintf(outp, "%5ld\t", tv.tv_sec * 1000000 + tv.tv_usec);
1128 /* Time_Of_Day_Seconds: on each row, print sec.usec last timestamp taken */
1129 if (DO_BIC(BIC_TOD))
1130 outp += sprintf(outp, "%10ld.%06ld\t", t->tv_end.tv_sec, t->tv_end.tv_usec);
1132 interval_float = t->tv_delta.tv_sec + t->tv_delta.tv_usec / 1000000.0;
1134 tsc = t->tsc * tsc_tweak;
1136 /* topo columns, print blanks on 1st (average) line */
1137 if (t == &average.threads) {
1138 if (DO_BIC(BIC_Package))
1139 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1140 if (DO_BIC(BIC_Die))
1141 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1142 if (DO_BIC(BIC_Node))
1143 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1144 if (DO_BIC(BIC_Core))
1145 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1146 if (DO_BIC(BIC_CPU))
1147 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1148 if (DO_BIC(BIC_APIC))
1149 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1150 if (DO_BIC(BIC_X2APIC))
1151 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1153 if (DO_BIC(BIC_Package)) {
1155 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->package_id);
1157 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1159 if (DO_BIC(BIC_Die)) {
1161 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), cpus[t->cpu_id].die_id);
1163 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1165 if (DO_BIC(BIC_Node)) {
1167 outp += sprintf(outp, "%s%d",
1168 (printed++ ? delim : ""), cpus[t->cpu_id].physical_node_id);
1170 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1172 if (DO_BIC(BIC_Core)) {
1174 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_id);
1176 outp += sprintf(outp, "%s-", (printed++ ? delim : ""));
1178 if (DO_BIC(BIC_CPU))
1179 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->cpu_id);
1180 if (DO_BIC(BIC_APIC))
1181 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->apic_id);
1182 if (DO_BIC(BIC_X2APIC))
1183 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->x2apic_id);
1186 if (DO_BIC(BIC_Avg_MHz))
1187 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 / units * t->aperf / interval_float);
1189 if (DO_BIC(BIC_Busy))
1190 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->mperf / tsc);
1192 if (DO_BIC(BIC_Bzy_MHz)) {
1195 sprintf(outp, "%s%.0f", (printed++ ? delim : ""), base_hz / units * t->aperf / t->mperf);
1197 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""),
1198 tsc / units * t->aperf / t->mperf / interval_float);
1201 if (DO_BIC(BIC_TSC_MHz))
1202 outp += sprintf(outp, "%s%.0f", (printed++ ? delim : ""), 1.0 * t->tsc / units / interval_float);
1204 if (DO_BIC(BIC_IPC))
1205 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 1.0 * t->instr_count / t->aperf);
1208 if (DO_BIC(BIC_IRQ)) {
1209 if (sums_need_wide_columns)
1210 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->irq_count);
1212 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->irq_count);
1216 if (DO_BIC(BIC_SMI))
1217 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), t->smi_count);
1219 /* Added counters */
1220 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1221 if (mp->format == FORMAT_RAW) {
1222 if (mp->width == 32)
1224 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)t->counter[i]);
1226 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), t->counter[i]);
1227 } else if (mp->format == FORMAT_DELTA) {
1228 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1229 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), t->counter[i]);
1231 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), t->counter[i]);
1232 } else if (mp->format == FORMAT_PERCENT) {
1233 if (mp->type == COUNTER_USEC)
1235 sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1236 t->counter[i] / interval_float / 10000);
1238 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->counter[i] / tsc);
1243 if (DO_BIC(BIC_CPU_c1))
1244 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * t->c1 / tsc);
1246 /* print per-core data only for 1st thread in core */
1247 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1250 if (DO_BIC(BIC_CPU_c3))
1251 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c3 / tsc);
1252 if (DO_BIC(BIC_CPU_c6))
1253 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c6 / tsc);
1254 if (DO_BIC(BIC_CPU_c7))
1255 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->c7 / tsc);
1258 if (DO_BIC(BIC_Mod_c6))
1259 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->mc6_us / tsc);
1261 if (DO_BIC(BIC_CoreTmp))
1262 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), c->core_temp_c);
1264 /* Core throttle count */
1265 if (DO_BIC(BIC_CORE_THROT_CNT))
1266 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->core_throt_cnt);
1268 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1269 if (mp->format == FORMAT_RAW) {
1270 if (mp->width == 32)
1272 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)c->counter[i]);
1274 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), c->counter[i]);
1275 } else if (mp->format == FORMAT_DELTA) {
1276 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1277 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), c->counter[i]);
1279 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), c->counter[i]);
1280 } else if (mp->format == FORMAT_PERCENT) {
1281 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * c->counter[i] / tsc);
1287 if (DO_BIC(BIC_CorWatt) && (do_rapl & RAPL_PER_CORE_ENERGY))
1289 sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units / interval_float);
1290 if (DO_BIC(BIC_Cor_J) && (do_rapl & RAPL_PER_CORE_ENERGY))
1291 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), c->core_energy * rapl_energy_units);
1293 /* print per-package data only for 1st core in package */
1294 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1298 if (DO_BIC(BIC_PkgTmp))
1299 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->pkg_temp_c);
1302 if (DO_BIC(BIC_GFX_rc6)) {
1303 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
1304 outp += sprintf(outp, "%s**.**", (printed++ ? delim : ""));
1306 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""),
1307 p->gfx_rc6_ms / 10.0 / interval_float);
1312 if (DO_BIC(BIC_GFXMHz))
1313 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_mhz);
1316 if (DO_BIC(BIC_GFXACTMHz))
1317 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->gfx_act_mhz);
1319 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
1320 if (DO_BIC(BIC_Totl_c0))
1321 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_wtd_core_c0 / tsc);
1322 if (DO_BIC(BIC_Any_c0))
1323 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_core_c0 / tsc);
1324 if (DO_BIC(BIC_GFX_c0))
1325 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_any_gfxe_c0 / tsc);
1326 if (DO_BIC(BIC_CPUGFX))
1327 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pkg_both_core_gfxe_c0 / tsc);
1329 if (DO_BIC(BIC_Pkgpc2))
1330 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc2 / tsc);
1331 if (DO_BIC(BIC_Pkgpc3))
1332 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc3 / tsc);
1333 if (DO_BIC(BIC_Pkgpc6))
1334 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc6 / tsc);
1335 if (DO_BIC(BIC_Pkgpc7))
1336 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc7 / tsc);
1337 if (DO_BIC(BIC_Pkgpc8))
1338 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc8 / tsc);
1339 if (DO_BIC(BIC_Pkgpc9))
1340 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc9 / tsc);
1341 if (DO_BIC(BIC_Pkgpc10))
1342 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->pc10 / tsc);
1344 if (DO_BIC(BIC_CPU_LPI))
1346 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->cpu_lpi / 1000000.0 / interval_float);
1347 if (DO_BIC(BIC_SYS_LPI))
1349 sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->sys_lpi / 1000000.0 / interval_float);
1351 if (DO_BIC(BIC_PkgWatt))
1353 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units / interval_float);
1355 if (DO_BIC(BIC_CorWatt) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1357 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units / interval_float);
1358 if (DO_BIC(BIC_GFXWatt))
1360 sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units / interval_float);
1361 if (DO_BIC(BIC_RAMWatt))
1363 sprintf(outp, fmt8, (printed++ ? delim : ""),
1364 p->energy_dram * rapl_dram_energy_units / interval_float);
1365 if (DO_BIC(BIC_Pkg_J))
1366 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_pkg * rapl_energy_units);
1367 if (DO_BIC(BIC_Cor_J) && !(do_rapl & RAPL_PER_CORE_ENERGY))
1368 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_cores * rapl_energy_units);
1369 if (DO_BIC(BIC_GFX_J))
1370 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_gfx * rapl_energy_units);
1371 if (DO_BIC(BIC_RAM_J))
1372 outp += sprintf(outp, fmt8, (printed++ ? delim : ""), p->energy_dram * rapl_dram_energy_units);
1373 if (DO_BIC(BIC_PKG__))
1375 sprintf(outp, fmt8, (printed++ ? delim : ""),
1376 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
1377 if (DO_BIC(BIC_RAM__))
1379 sprintf(outp, fmt8, (printed++ ? delim : ""),
1380 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
1382 if (DO_BIC(BIC_UNCORE_MHZ))
1383 outp += sprintf(outp, "%s%d", (printed++ ? delim : ""), p->uncore_mhz);
1385 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1386 if (mp->format == FORMAT_RAW) {
1387 if (mp->width == 32)
1389 sprintf(outp, "%s0x%08x", (printed++ ? delim : ""), (unsigned int)p->counter[i]);
1391 outp += sprintf(outp, "%s0x%016llx", (printed++ ? delim : ""), p->counter[i]);
1392 } else if (mp->format == FORMAT_DELTA) {
1393 if ((mp->type == COUNTER_ITEMS) && sums_need_wide_columns)
1394 outp += sprintf(outp, "%s%8lld", (printed++ ? delim : ""), p->counter[i]);
1396 outp += sprintf(outp, "%s%lld", (printed++ ? delim : ""), p->counter[i]);
1397 } else if (mp->format == FORMAT_PERCENT) {
1398 outp += sprintf(outp, "%s%.2f", (printed++ ? delim : ""), 100.0 * p->counter[i] / tsc);
1403 if (*(outp - 1) != '\n')
1404 outp += sprintf(outp, "\n");
1409 void flush_output_stdout(void)
1418 fputs(output_buffer, filep);
1421 outp = output_buffer;
1424 void flush_output_stderr(void)
1426 fputs(output_buffer, outf);
1428 outp = output_buffer;
1431 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1435 if ((!count || (header_iterations && !(count % header_iterations))) || !summary_only)
1438 format_counters(&average.threads, &average.cores, &average.packages);
1445 for_all_cpus(format_counters, t, c, p);
1448 #define DELTA_WRAP32(new, old) \
1449 old = ((((unsigned long long)new << 32) - ((unsigned long long)old << 32)) >> 32);
1451 int delta_package(struct pkg_data *new, struct pkg_data *old)
1454 struct msr_counter *mp;
1456 if (DO_BIC(BIC_Totl_c0))
1457 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
1458 if (DO_BIC(BIC_Any_c0))
1459 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
1460 if (DO_BIC(BIC_GFX_c0))
1461 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
1462 if (DO_BIC(BIC_CPUGFX))
1463 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
1465 old->pc2 = new->pc2 - old->pc2;
1466 if (DO_BIC(BIC_Pkgpc3))
1467 old->pc3 = new->pc3 - old->pc3;
1468 if (DO_BIC(BIC_Pkgpc6))
1469 old->pc6 = new->pc6 - old->pc6;
1470 if (DO_BIC(BIC_Pkgpc7))
1471 old->pc7 = new->pc7 - old->pc7;
1472 old->pc8 = new->pc8 - old->pc8;
1473 old->pc9 = new->pc9 - old->pc9;
1474 old->pc10 = new->pc10 - old->pc10;
1475 old->cpu_lpi = new->cpu_lpi - old->cpu_lpi;
1476 old->sys_lpi = new->sys_lpi - old->sys_lpi;
1477 old->pkg_temp_c = new->pkg_temp_c;
1479 /* flag an error when rc6 counter resets/wraps */
1480 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
1481 old->gfx_rc6_ms = -1;
1483 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
1485 old->uncore_mhz = new->uncore_mhz;
1486 old->gfx_mhz = new->gfx_mhz;
1487 old->gfx_act_mhz = new->gfx_act_mhz;
1489 old->energy_pkg = new->energy_pkg - old->energy_pkg;
1490 old->energy_cores = new->energy_cores - old->energy_cores;
1491 old->energy_gfx = new->energy_gfx - old->energy_gfx;
1492 old->energy_dram = new->energy_dram - old->energy_dram;
1493 old->rapl_pkg_perf_status = new->rapl_pkg_perf_status - old->rapl_pkg_perf_status;
1494 old->rapl_dram_perf_status = new->rapl_dram_perf_status - old->rapl_dram_perf_status;
1496 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1497 if (mp->format == FORMAT_RAW)
1498 old->counter[i] = new->counter[i];
1500 old->counter[i] = new->counter[i] - old->counter[i];
1506 void delta_core(struct core_data *new, struct core_data *old)
1509 struct msr_counter *mp;
1511 old->c3 = new->c3 - old->c3;
1512 old->c6 = new->c6 - old->c6;
1513 old->c7 = new->c7 - old->c7;
1514 old->core_temp_c = new->core_temp_c;
1515 old->core_throt_cnt = new->core_throt_cnt;
1516 old->mc6_us = new->mc6_us - old->mc6_us;
1518 DELTA_WRAP32(new->core_energy, old->core_energy);
1520 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1521 if (mp->format == FORMAT_RAW)
1522 old->counter[i] = new->counter[i];
1524 old->counter[i] = new->counter[i] - old->counter[i];
1528 int soft_c1_residency_display(int bic)
1530 if (!DO_BIC(BIC_CPU_c1) || use_c1_residency_msr)
1533 return DO_BIC_READ(bic);
1539 int delta_thread(struct thread_data *new, struct thread_data *old, struct core_data *core_delta)
1542 struct msr_counter *mp;
1544 /* we run cpuid just the 1st time, copy the results */
1545 if (DO_BIC(BIC_APIC))
1546 new->apic_id = old->apic_id;
1547 if (DO_BIC(BIC_X2APIC))
1548 new->x2apic_id = old->x2apic_id;
1551 * the timestamps from start of measurement interval are in "old"
1552 * the timestamp from end of measurement interval are in "new"
1553 * over-write old w/ new so we can print end of interval values
1556 timersub(&new->tv_begin, &old->tv_begin, &old->tv_delta);
1557 old->tv_begin = new->tv_begin;
1558 old->tv_end = new->tv_end;
1560 old->tsc = new->tsc - old->tsc;
1562 /* check for TSC < 1 Mcycles over interval */
1563 if (old->tsc < (1000 * 1000))
1564 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1565 "You can disable all c-states by booting with \"idle=poll\"\n"
1566 "or just the deep ones with \"processor.max_cstate=1\"");
1568 old->c1 = new->c1 - old->c1;
1570 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
1571 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1572 old->aperf = new->aperf - old->aperf;
1573 old->mperf = new->mperf - old->mperf;
1579 if (use_c1_residency_msr) {
1581 * Some models have a dedicated C1 residency MSR,
1582 * which should be more accurate than the derivation below.
1586 * As counter collection is not atomic,
1587 * it is possible for mperf's non-halted cycles + idle states
1588 * to exceed TSC's all cycles: show c1 = 0% in that case.
1590 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > (old->tsc * tsc_tweak))
1593 /* normal case, derive c1 */
1594 old->c1 = (old->tsc * tsc_tweak) - old->mperf - core_delta->c3
1595 - core_delta->c6 - core_delta->c7;
1599 if (old->mperf == 0) {
1601 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1602 old->mperf = 1; /* divide by 0 protection */
1605 if (DO_BIC(BIC_IPC))
1606 old->instr_count = new->instr_count - old->instr_count;
1608 if (DO_BIC(BIC_IRQ))
1609 old->irq_count = new->irq_count - old->irq_count;
1611 if (DO_BIC(BIC_SMI))
1612 old->smi_count = new->smi_count - old->smi_count;
1614 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1615 if (mp->format == FORMAT_RAW)
1616 old->counter[i] = new->counter[i];
1618 old->counter[i] = new->counter[i] - old->counter[i];
1623 int delta_cpu(struct thread_data *t, struct core_data *c,
1624 struct pkg_data *p, struct thread_data *t2, struct core_data *c2, struct pkg_data *p2)
1628 /* calculate core delta only for 1st thread in core */
1629 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1632 /* always calculate thread delta */
1633 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1637 /* calculate package delta only for 1st core in package */
1638 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1639 retval = delta_package(p, p2);
1644 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1647 struct msr_counter *mp;
1649 t->tv_begin.tv_sec = 0;
1650 t->tv_begin.tv_usec = 0;
1651 t->tv_end.tv_sec = 0;
1652 t->tv_end.tv_usec = 0;
1653 t->tv_delta.tv_sec = 0;
1654 t->tv_delta.tv_usec = 0;
1666 /* tells format_counters to dump all fields from this set */
1667 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1675 c->core_throt_cnt = 0;
1677 p->pkg_wtd_core_c0 = 0;
1678 p->pkg_any_core_c0 = 0;
1679 p->pkg_any_gfxe_c0 = 0;
1680 p->pkg_both_core_gfxe_c0 = 0;
1683 if (DO_BIC(BIC_Pkgpc3))
1685 if (DO_BIC(BIC_Pkgpc6))
1687 if (DO_BIC(BIC_Pkgpc7))
1697 p->energy_cores = 0;
1699 p->rapl_pkg_perf_status = 0;
1700 p->rapl_dram_perf_status = 0;
1707 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1710 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1713 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1717 int sum_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1720 struct msr_counter *mp;
1722 /* copy un-changing apic_id's */
1723 if (DO_BIC(BIC_APIC))
1724 average.threads.apic_id = t->apic_id;
1725 if (DO_BIC(BIC_X2APIC))
1726 average.threads.x2apic_id = t->x2apic_id;
1728 /* remember first tv_begin */
1729 if (average.threads.tv_begin.tv_sec == 0)
1730 average.threads.tv_begin = t->tv_begin;
1732 /* remember last tv_end */
1733 average.threads.tv_end = t->tv_end;
1735 average.threads.tsc += t->tsc;
1736 average.threads.aperf += t->aperf;
1737 average.threads.mperf += t->mperf;
1738 average.threads.c1 += t->c1;
1740 average.threads.instr_count += t->instr_count;
1742 average.threads.irq_count += t->irq_count;
1743 average.threads.smi_count += t->smi_count;
1745 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1746 if (mp->format == FORMAT_RAW)
1748 average.threads.counter[i] += t->counter[i];
1751 /* sum per-core values only for 1st thread in core */
1752 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1755 average.cores.c3 += c->c3;
1756 average.cores.c6 += c->c6;
1757 average.cores.c7 += c->c7;
1758 average.cores.mc6_us += c->mc6_us;
1760 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1761 average.cores.core_throt_cnt = MAX(average.cores.core_throt_cnt, c->core_throt_cnt);
1763 average.cores.core_energy += c->core_energy;
1765 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1766 if (mp->format == FORMAT_RAW)
1768 average.cores.counter[i] += c->counter[i];
1771 /* sum per-pkg values only for 1st core in pkg */
1772 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1775 if (DO_BIC(BIC_Totl_c0))
1776 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1777 if (DO_BIC(BIC_Any_c0))
1778 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1779 if (DO_BIC(BIC_GFX_c0))
1780 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1781 if (DO_BIC(BIC_CPUGFX))
1782 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1784 average.packages.pc2 += p->pc2;
1785 if (DO_BIC(BIC_Pkgpc3))
1786 average.packages.pc3 += p->pc3;
1787 if (DO_BIC(BIC_Pkgpc6))
1788 average.packages.pc6 += p->pc6;
1789 if (DO_BIC(BIC_Pkgpc7))
1790 average.packages.pc7 += p->pc7;
1791 average.packages.pc8 += p->pc8;
1792 average.packages.pc9 += p->pc9;
1793 average.packages.pc10 += p->pc10;
1795 average.packages.cpu_lpi = p->cpu_lpi;
1796 average.packages.sys_lpi = p->sys_lpi;
1798 average.packages.energy_pkg += p->energy_pkg;
1799 average.packages.energy_dram += p->energy_dram;
1800 average.packages.energy_cores += p->energy_cores;
1801 average.packages.energy_gfx += p->energy_gfx;
1803 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1804 average.packages.uncore_mhz = p->uncore_mhz;
1805 average.packages.gfx_mhz = p->gfx_mhz;
1806 average.packages.gfx_act_mhz = p->gfx_act_mhz;
1808 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1810 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1811 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1813 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1814 if (mp->format == FORMAT_RAW)
1816 average.packages.counter[i] += p->counter[i];
1822 * sum the counters for all cpus in the system
1823 * compute the weighted average
1825 void compute_average(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1828 struct msr_counter *mp;
1830 clear_counters(&average.threads, &average.cores, &average.packages);
1832 for_all_cpus(sum_counters, t, c, p);
1834 /* Use the global time delta for the average. */
1835 average.threads.tv_delta = tv_delta;
1837 average.threads.tsc /= topo.num_cpus;
1838 average.threads.aperf /= topo.num_cpus;
1839 average.threads.mperf /= topo.num_cpus;
1840 average.threads.instr_count /= topo.num_cpus;
1841 average.threads.c1 /= topo.num_cpus;
1843 if (average.threads.irq_count > 9999999)
1844 sums_need_wide_columns = 1;
1846 average.cores.c3 /= topo.num_cores;
1847 average.cores.c6 /= topo.num_cores;
1848 average.cores.c7 /= topo.num_cores;
1849 average.cores.mc6_us /= topo.num_cores;
1851 if (DO_BIC(BIC_Totl_c0))
1852 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1853 if (DO_BIC(BIC_Any_c0))
1854 average.packages.pkg_any_core_c0 /= topo.num_packages;
1855 if (DO_BIC(BIC_GFX_c0))
1856 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1857 if (DO_BIC(BIC_CPUGFX))
1858 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1860 average.packages.pc2 /= topo.num_packages;
1861 if (DO_BIC(BIC_Pkgpc3))
1862 average.packages.pc3 /= topo.num_packages;
1863 if (DO_BIC(BIC_Pkgpc6))
1864 average.packages.pc6 /= topo.num_packages;
1865 if (DO_BIC(BIC_Pkgpc7))
1866 average.packages.pc7 /= topo.num_packages;
1868 average.packages.pc8 /= topo.num_packages;
1869 average.packages.pc9 /= topo.num_packages;
1870 average.packages.pc10 /= topo.num_packages;
1872 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1873 if (mp->format == FORMAT_RAW)
1875 if (mp->type == COUNTER_ITEMS) {
1876 if (average.threads.counter[i] > 9999999)
1877 sums_need_wide_columns = 1;
1880 average.threads.counter[i] /= topo.num_cpus;
1882 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1883 if (mp->format == FORMAT_RAW)
1885 if (mp->type == COUNTER_ITEMS) {
1886 if (average.cores.counter[i] > 9999999)
1887 sums_need_wide_columns = 1;
1889 average.cores.counter[i] /= topo.num_cores;
1891 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1892 if (mp->format == FORMAT_RAW)
1894 if (mp->type == COUNTER_ITEMS) {
1895 if (average.packages.counter[i] > 9999999)
1896 sums_need_wide_columns = 1;
1898 average.packages.counter[i] /= topo.num_packages;
1902 static unsigned long long rdtsc(void)
1904 unsigned int low, high;
1906 asm volatile ("rdtsc":"=a" (low), "=d"(high));
1908 return low | ((unsigned long long)high) << 32;
1912 * Open a file, and exit on failure
1914 FILE *fopen_or_die(const char *path, const char *mode)
1916 FILE *filep = fopen(path, mode);
1919 err(1, "%s: open failed", path);
1924 * snapshot_sysfs_counter()
1926 * return snapshot of given counter
1928 unsigned long long snapshot_sysfs_counter(char *path)
1932 unsigned long long counter;
1934 fp = fopen_or_die(path, "r");
1936 retval = fscanf(fp, "%lld", &counter);
1938 err(1, "snapshot_sysfs_counter(%s)", path);
1945 int get_mp(int cpu, struct msr_counter *mp, unsigned long long *counterp)
1947 if (mp->msr_num != 0) {
1948 if (get_msr(cpu, mp->msr_num, counterp))
1951 char path[128 + PATH_BYTES];
1953 if (mp->flags & SYSFS_PERCPU) {
1954 sprintf(path, "/sys/devices/system/cpu/cpu%d/%s", cpu, mp->path);
1956 *counterp = snapshot_sysfs_counter(path);
1958 *counterp = snapshot_sysfs_counter(mp->path);
1965 unsigned long long get_uncore_mhz(int package, int die)
1969 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/current_freq_khz", package,
1972 return (snapshot_sysfs_counter(path) / 1000);
1975 int get_epb(int cpu)
1977 char path[128 + PATH_BYTES];
1978 unsigned long long msr;
1982 sprintf(path, "/sys/devices/system/cpu/cpu%d/power/energy_perf_bias", cpu);
1984 fp = fopen(path, "r");
1988 ret = fscanf(fp, "%d", &epb);
1990 err(1, "%s(%s)", __func__, path);
1997 get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr);
2002 void get_apic_id(struct thread_data *t)
2004 unsigned int eax, ebx, ecx, edx;
2006 if (DO_BIC(BIC_APIC)) {
2007 eax = ebx = ecx = edx = 0;
2008 __cpuid(1, eax, ebx, ecx, edx);
2010 t->apic_id = (ebx >> 24) & 0xff;
2013 if (!DO_BIC(BIC_X2APIC))
2016 if (authentic_amd || hygon_genuine) {
2017 unsigned int topology_extensions;
2019 if (max_extended_level < 0x8000001e)
2022 eax = ebx = ecx = edx = 0;
2023 __cpuid(0x80000001, eax, ebx, ecx, edx);
2024 topology_extensions = ecx & (1 << 22);
2026 if (topology_extensions == 0)
2029 eax = ebx = ecx = edx = 0;
2030 __cpuid(0x8000001e, eax, ebx, ecx, edx);
2039 if (max_level < 0xb)
2043 __cpuid(0xb, eax, ebx, ecx, edx);
2046 if (debug && (t->apic_id != (t->x2apic_id & 0xff)))
2047 fprintf(outf, "cpu%d: BIOS BUG: apic 0x%x x2apic 0x%x\n", t->cpu_id, t->apic_id, t->x2apic_id);
2050 int get_core_throt_cnt(int cpu, unsigned long long *cnt)
2052 char path[128 + PATH_BYTES];
2053 unsigned long long tmp;
2057 sprintf(path, "/sys/devices/system/cpu/cpu%d/thermal_throttle/core_throttle_count", cpu);
2058 fp = fopen(path, "r");
2061 ret = fscanf(fp, "%lld", &tmp);
2073 * acquire and record local counters for that cpu
2075 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2077 int cpu = t->cpu_id;
2078 unsigned long long msr;
2079 int aperf_mperf_retry_count = 0;
2080 struct msr_counter *mp;
2083 if (cpu_migrate(cpu)) {
2084 fprintf(outf, "get_counters: Could not migrate to CPU %d\n", cpu);
2088 gettimeofday(&t->tv_begin, (struct timezone *)NULL);
2090 if (first_counter_read)
2093 t->tsc = rdtsc(); /* we are running on local CPU of interest */
2095 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz) || soft_c1_residency_display(BIC_Avg_MHz)) {
2096 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
2099 * The TSC, APERF and MPERF must be read together for
2100 * APERF/MPERF and MPERF/TSC to give accurate results.
2102 * Unfortunately, APERF and MPERF are read by
2103 * individual system call, so delays may occur
2104 * between them. If the time to read them
2105 * varies by a large amount, we re-read them.
2109 * This initial dummy APERF read has been seen to
2110 * reduce jitter in the subsequent reads.
2113 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2116 t->tsc = rdtsc(); /* re-read close to APERF */
2118 tsc_before = t->tsc;
2120 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
2123 tsc_between = rdtsc();
2125 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
2128 tsc_after = rdtsc();
2130 aperf_time = tsc_between - tsc_before;
2131 mperf_time = tsc_after - tsc_between;
2134 * If the system call latency to read APERF and MPERF
2135 * differ by more than 2x, then try again.
2137 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
2138 aperf_mperf_retry_count++;
2139 if (aperf_mperf_retry_count < 5)
2142 warnx("cpu%d jitter %lld %lld", cpu, aperf_time, mperf_time);
2144 aperf_mperf_retry_count = 0;
2146 t->aperf = t->aperf * aperf_mperf_multiplier;
2147 t->mperf = t->mperf * aperf_mperf_multiplier;
2150 if (DO_BIC(BIC_IPC))
2151 if (read(get_instr_count_fd(cpu), &t->instr_count, sizeof(long long)) != sizeof(long long))
2154 if (DO_BIC(BIC_IRQ))
2155 t->irq_count = irqs_per_cpu[cpu];
2156 if (DO_BIC(BIC_SMI)) {
2157 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
2159 t->smi_count = msr & 0xFFFFFFFF;
2161 if (DO_BIC(BIC_CPU_c1) && use_c1_residency_msr) {
2162 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
2166 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
2167 if (get_mp(cpu, mp, &t->counter[i]))
2171 /* collect core counters only for 1st thread in core */
2172 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2175 if (DO_BIC(BIC_CPU_c3) || soft_c1_residency_display(BIC_CPU_c3)) {
2176 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
2180 if ((DO_BIC(BIC_CPU_c6) || soft_c1_residency_display(BIC_CPU_c6)) && !do_knl_cstates) {
2181 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
2183 } else if (do_knl_cstates && soft_c1_residency_display(BIC_CPU_c6)) {
2184 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
2188 if (DO_BIC(BIC_CPU_c7) || soft_c1_residency_display(BIC_CPU_c7)) {
2189 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
2191 else if (t->is_atom) {
2193 * For Atom CPUs that has core cstate deeper than c6,
2194 * MSR_CORE_C6_RESIDENCY returns residency of cc6 and deeper.
2195 * Minus CC7 (and deeper cstates) residency to get
2196 * accturate cc6 residency.
2202 if (DO_BIC(BIC_Mod_c6))
2203 if (get_msr(cpu, MSR_MODULE_C6_RES_MS, &c->mc6_us))
2206 if (DO_BIC(BIC_CoreTmp)) {
2207 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2209 c->core_temp_c = tj_max - ((msr >> 16) & 0x7F);
2212 if (DO_BIC(BIC_CORE_THROT_CNT))
2213 get_core_throt_cnt(cpu, &c->core_throt_cnt);
2215 if (do_rapl & RAPL_AMD_F17H) {
2216 if (get_msr(cpu, MSR_CORE_ENERGY_STAT, &msr))
2218 c->core_energy = msr & 0xFFFFFFFF;
2221 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
2222 if (get_mp(cpu, mp, &c->counter[i]))
2226 /* collect package counters only for 1st core in package */
2227 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2230 if (DO_BIC(BIC_Totl_c0)) {
2231 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
2234 if (DO_BIC(BIC_Any_c0)) {
2235 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
2238 if (DO_BIC(BIC_GFX_c0)) {
2239 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
2242 if (DO_BIC(BIC_CPUGFX)) {
2243 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
2246 if (DO_BIC(BIC_Pkgpc3))
2247 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
2249 if (DO_BIC(BIC_Pkgpc6)) {
2250 if (do_slm_cstates) {
2251 if (get_msr(cpu, MSR_ATOM_PKG_C6_RESIDENCY, &p->pc6))
2254 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
2259 if (DO_BIC(BIC_Pkgpc2))
2260 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
2262 if (DO_BIC(BIC_Pkgpc7))
2263 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
2265 if (DO_BIC(BIC_Pkgpc8))
2266 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
2268 if (DO_BIC(BIC_Pkgpc9))
2269 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
2271 if (DO_BIC(BIC_Pkgpc10))
2272 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
2275 if (DO_BIC(BIC_CPU_LPI))
2276 p->cpu_lpi = cpuidle_cur_cpu_lpi_us;
2277 if (DO_BIC(BIC_SYS_LPI))
2278 p->sys_lpi = cpuidle_cur_sys_lpi_us;
2280 if (do_rapl & RAPL_PKG) {
2281 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STATUS, &msr))
2283 p->energy_pkg = msr;
2285 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
2286 if (get_msr_sum(cpu, MSR_PP0_ENERGY_STATUS, &msr))
2288 p->energy_cores = msr;
2290 if (do_rapl & RAPL_DRAM) {
2291 if (get_msr_sum(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
2293 p->energy_dram = msr;
2295 if (do_rapl & RAPL_GFX) {
2296 if (get_msr_sum(cpu, MSR_PP1_ENERGY_STATUS, &msr))
2298 p->energy_gfx = msr;
2300 if (do_rapl & RAPL_PKG_PERF_STATUS) {
2301 if (get_msr_sum(cpu, MSR_PKG_PERF_STATUS, &msr))
2303 p->rapl_pkg_perf_status = msr;
2305 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
2306 if (get_msr_sum(cpu, MSR_DRAM_PERF_STATUS, &msr))
2308 p->rapl_dram_perf_status = msr;
2310 if (do_rapl & RAPL_AMD_F17H) {
2311 if (get_msr_sum(cpu, MSR_PKG_ENERGY_STAT, &msr))
2313 p->energy_pkg = msr;
2315 if (DO_BIC(BIC_PkgTmp)) {
2316 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2318 p->pkg_temp_c = tj_max - ((msr >> 16) & 0x7F);
2321 if (DO_BIC(BIC_GFX_rc6))
2322 p->gfx_rc6_ms = gfx_cur_rc6_ms;
2324 /* n.b. assume die0 uncore frequency applies to whole package */
2325 if (DO_BIC(BIC_UNCORE_MHZ))
2326 p->uncore_mhz = get_uncore_mhz(p->package_id, 0);
2328 if (DO_BIC(BIC_GFXMHz))
2329 p->gfx_mhz = gfx_cur_mhz;
2331 if (DO_BIC(BIC_GFXACTMHz))
2332 p->gfx_act_mhz = gfx_act_mhz;
2334 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
2335 if (get_mp(cpu, mp, &p->counter[i]))
2339 gettimeofday(&t->tv_end, (struct timezone *)NULL);
2345 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
2346 * If you change the values, note they are used both in comparisons
2347 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
2350 #define PCLUKN 0 /* Unknown */
2351 #define PCLRSV 1 /* Reserved */
2352 #define PCL__0 2 /* PC0 */
2353 #define PCL__1 3 /* PC1 */
2354 #define PCL__2 4 /* PC2 */
2355 #define PCL__3 5 /* PC3 */
2356 #define PCL__4 6 /* PC4 */
2357 #define PCL__6 7 /* PC6 */
2358 #define PCL_6N 8 /* PC6 No Retention */
2359 #define PCL_6R 9 /* PC6 Retention */
2360 #define PCL__7 10 /* PC7 */
2361 #define PCL_7S 11 /* PC7 Shrink */
2362 #define PCL__8 12 /* PC8 */
2363 #define PCL__9 13 /* PC9 */
2364 #define PCL_10 14 /* PC10 */
2365 #define PCLUNL 15 /* Unlimited */
2367 int pkg_cstate_limit = PCLUKN;
2368 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
2369 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "pc10", "unlimited"
2372 int nhm_pkg_cstate_limits[16] =
2373 { PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2377 int snb_pkg_cstate_limits[16] =
2378 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2382 int hsw_pkg_cstate_limits[16] =
2383 { PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2387 int slv_pkg_cstate_limits[16] =
2388 { PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2392 int amt_pkg_cstate_limits[16] =
2393 { PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2397 int phi_pkg_cstate_limits[16] =
2398 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2402 int glm_pkg_cstate_limits[16] =
2403 { PCLUNL, PCL__1, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCL_10, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2407 int skx_pkg_cstate_limits[16] =
2408 { PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2412 int icx_pkg_cstate_limits[16] =
2413 { PCL__0, PCL__2, PCL__6, PCL__6, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV,
2417 static void calculate_tsc_tweak()
2419 tsc_tweak = base_hz / tsc_hz;
2422 void prewake_cstate_probe(unsigned int family, unsigned int model);
2424 static void dump_nhm_platform_info(void)
2426 unsigned long long msr;
2429 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2431 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
2433 ratio = (msr >> 40) & 0xFF;
2434 fprintf(outf, "%d * %.1f = %.1f MHz max efficiency frequency\n", ratio, bclk, ratio * bclk);
2436 ratio = (msr >> 8) & 0xFF;
2437 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2439 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
2440 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
2441 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
2443 /* C-state Pre-wake Disable (CSTATE_PREWAKE_DISABLE) */
2444 if (dis_cstate_prewake)
2445 fprintf(outf, "C-state Pre-wake: %sabled\n", msr & 0x40000000 ? "DIS" : "EN");
2450 static void dump_hsw_turbo_ratio_limits(void)
2452 unsigned long long msr;
2455 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
2457 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
2459 ratio = (msr >> 8) & 0xFF;
2461 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 18 active cores\n", ratio, bclk, ratio * bclk);
2463 ratio = (msr >> 0) & 0xFF;
2465 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 17 active cores\n", ratio, bclk, ratio * bclk);
2469 static void dump_ivt_turbo_ratio_limits(void)
2471 unsigned long long msr;
2474 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
2476 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
2478 ratio = (msr >> 56) & 0xFF;
2480 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 16 active cores\n", ratio, bclk, ratio * bclk);
2482 ratio = (msr >> 48) & 0xFF;
2484 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 15 active cores\n", ratio, bclk, ratio * bclk);
2486 ratio = (msr >> 40) & 0xFF;
2488 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 14 active cores\n", ratio, bclk, ratio * bclk);
2490 ratio = (msr >> 32) & 0xFF;
2492 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 13 active cores\n", ratio, bclk, ratio * bclk);
2494 ratio = (msr >> 24) & 0xFF;
2496 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 12 active cores\n", ratio, bclk, ratio * bclk);
2498 ratio = (msr >> 16) & 0xFF;
2500 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 11 active cores\n", ratio, bclk, ratio * bclk);
2502 ratio = (msr >> 8) & 0xFF;
2504 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 10 active cores\n", ratio, bclk, ratio * bclk);
2506 ratio = (msr >> 0) & 0xFF;
2508 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 9 active cores\n", ratio, bclk, ratio * bclk);
2512 int has_turbo_ratio_group_limits(int family, int model)
2522 case INTEL_FAM6_ATOM_GOLDMONT:
2523 case INTEL_FAM6_SKYLAKE_X:
2524 case INTEL_FAM6_ICELAKE_X:
2525 case INTEL_FAM6_SAPPHIRERAPIDS_X:
2526 case INTEL_FAM6_ATOM_GOLDMONT_D:
2527 case INTEL_FAM6_ATOM_TREMONT_D:
2534 static void dump_turbo_ratio_limits(int trl_msr_offset, int family, int model)
2536 unsigned long long msr, core_counts;
2539 get_msr(base_cpu, trl_msr_offset, &msr);
2540 fprintf(outf, "cpu%d: MSR_%sTURBO_RATIO_LIMIT: 0x%08llx\n",
2541 base_cpu, trl_msr_offset == MSR_SECONDARY_TURBO_RATIO_LIMIT ? "SECONDARY_" : "", msr);
2543 if (has_turbo_ratio_group_limits(family, model)) {
2544 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &core_counts);
2545 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, core_counts);
2547 core_counts = 0x0807060504030201;
2550 for (shift = 56; shift >= 0; shift -= 8) {
2551 unsigned int ratio, group_size;
2553 ratio = (msr >> shift) & 0xFF;
2554 group_size = (core_counts >> shift) & 0xFF;
2556 fprintf(outf, "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2557 ratio, bclk, ratio * bclk, group_size);
2563 static void dump_atom_turbo_ratio_limits(void)
2565 unsigned long long msr;
2568 get_msr(base_cpu, MSR_ATOM_CORE_RATIOS, &msr);
2569 fprintf(outf, "cpu%d: MSR_ATOM_CORE_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2571 ratio = (msr >> 0) & 0x3F;
2573 fprintf(outf, "%d * %.1f = %.1f MHz minimum operating frequency\n", ratio, bclk, ratio * bclk);
2575 ratio = (msr >> 8) & 0x3F;
2577 fprintf(outf, "%d * %.1f = %.1f MHz low frequency mode (LFM)\n", ratio, bclk, ratio * bclk);
2579 ratio = (msr >> 16) & 0x3F;
2581 fprintf(outf, "%d * %.1f = %.1f MHz base frequency\n", ratio, bclk, ratio * bclk);
2583 get_msr(base_cpu, MSR_ATOM_CORE_TURBO_RATIOS, &msr);
2584 fprintf(outf, "cpu%d: MSR_ATOM_CORE_TURBO_RATIOS: 0x%08llx\n", base_cpu, msr & 0xFFFFFFFF);
2586 ratio = (msr >> 24) & 0x3F;
2588 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 4 active cores\n", ratio, bclk, ratio * bclk);
2590 ratio = (msr >> 16) & 0x3F;
2592 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 3 active cores\n", ratio, bclk, ratio * bclk);
2594 ratio = (msr >> 8) & 0x3F;
2596 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 2 active cores\n", ratio, bclk, ratio * bclk);
2598 ratio = (msr >> 0) & 0x3F;
2600 fprintf(outf, "%d * %.1f = %.1f MHz max turbo 1 active core\n", ratio, bclk, ratio * bclk);
2603 static void dump_knl_turbo_ratio_limits(void)
2605 const unsigned int buckets_no = 7;
2607 unsigned long long msr;
2608 int delta_cores, delta_ratio;
2610 unsigned int cores[buckets_no];
2611 unsigned int ratio[buckets_no];
2613 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
2615 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
2618 * Turbo encoding in KNL is as follows:
2620 * [7:1] -- Base value of number of active cores of bucket 1.
2621 * [15:8] -- Base value of freq ratio of bucket 1.
2622 * [20:16] -- +ve delta of number of active cores of bucket 2.
2623 * i.e. active cores of bucket 2 =
2624 * active cores of bucket 1 + delta
2625 * [23:21] -- Negative delta of freq ratio of bucket 2.
2626 * i.e. freq ratio of bucket 2 =
2627 * freq ratio of bucket 1 - delta
2628 * [28:24]-- +ve delta of number of active cores of bucket 3.
2629 * [31:29]-- -ve delta of freq ratio of bucket 3.
2630 * [36:32]-- +ve delta of number of active cores of bucket 4.
2631 * [39:37]-- -ve delta of freq ratio of bucket 4.
2632 * [44:40]-- +ve delta of number of active cores of bucket 5.
2633 * [47:45]-- -ve delta of freq ratio of bucket 5.
2634 * [52:48]-- +ve delta of number of active cores of bucket 6.
2635 * [55:53]-- -ve delta of freq ratio of bucket 6.
2636 * [60:56]-- +ve delta of number of active cores of bucket 7.
2637 * [63:61]-- -ve delta of freq ratio of bucket 7.
2641 cores[b_nr] = (msr & 0xFF) >> 1;
2642 ratio[b_nr] = (msr >> 8) & 0xFF;
2644 for (i = 16; i < 64; i += 8) {
2645 delta_cores = (msr >> i) & 0x1F;
2646 delta_ratio = (msr >> (i + 5)) & 0x7;
2648 cores[b_nr + 1] = cores[b_nr] + delta_cores;
2649 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
2653 for (i = buckets_no - 1; i >= 0; i--)
2654 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
2656 "%d * %.1f = %.1f MHz max turbo %d active cores\n",
2657 ratio[i], bclk, ratio[i] * bclk, cores[i]);
2660 static void dump_nhm_cst_cfg(void)
2662 unsigned long long msr;
2664 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
2666 fprintf(outf, "cpu%d: MSR_PKG_CST_CONFIG_CONTROL: 0x%08llx", base_cpu, msr);
2668 fprintf(outf, " (%s%s%s%s%slocked, pkg-cstate-limit=%d (%s)",
2669 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
2670 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
2671 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
2672 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
2673 (msr & (1 << 15)) ? "" : "UN", (unsigned int)msr & 0xF, pkg_cstate_limit_strings[pkg_cstate_limit]);
2675 #define AUTOMATIC_CSTATE_CONVERSION (1UL << 16)
2676 if (has_automatic_cstate_conversion) {
2677 fprintf(outf, ", automatic c-state conversion=%s", (msr & AUTOMATIC_CSTATE_CONVERSION) ? "on" : "off");
2680 fprintf(outf, ")\n");
2685 static void dump_config_tdp(void)
2687 unsigned long long msr;
2689 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
2690 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
2691 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
2693 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
2694 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
2696 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2697 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2698 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2699 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
2701 fprintf(outf, ")\n");
2703 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
2704 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
2706 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
2707 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
2708 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
2709 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
2711 fprintf(outf, ")\n");
2713 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
2714 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
2716 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
2717 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2718 fprintf(outf, ")\n");
2720 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
2721 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
2722 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
2723 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
2724 fprintf(outf, ")\n");
2727 unsigned int irtl_time_units[] = { 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
2729 void print_irtl(void)
2731 unsigned long long msr;
2733 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
2734 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
2735 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2736 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2738 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
2739 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
2740 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2741 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2743 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
2744 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
2745 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2746 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2751 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
2752 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
2753 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2754 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2756 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
2757 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
2758 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2759 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2761 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
2762 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
2763 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
2764 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
2768 void free_fd_percpu(void)
2772 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
2773 if (fd_percpu[i] != 0)
2774 close(fd_percpu[i]);
2780 void free_all_buffers(void)
2784 CPU_FREE(cpu_present_set);
2785 cpu_present_set = NULL;
2786 cpu_present_setsize = 0;
2788 CPU_FREE(cpu_affinity_set);
2789 cpu_affinity_set = NULL;
2790 cpu_affinity_setsize = 0;
2798 package_even = NULL;
2808 free(output_buffer);
2809 output_buffer = NULL;
2814 free(irq_column_2_cpu);
2817 for (i = 0; i <= topo.max_cpu_num; ++i) {
2818 if (cpus[i].put_ids)
2819 CPU_FREE(cpus[i].put_ids);
2825 * Parse a file containing a single int.
2826 * Return 0 if file can not be opened
2827 * Exit if file can be opened, but can not be parsed
2829 int parse_int_file(const char *fmt, ...)
2832 char path[PATH_MAX];
2836 va_start(args, fmt);
2837 vsnprintf(path, sizeof(path), fmt, args);
2839 filep = fopen(path, "r");
2842 if (fscanf(filep, "%d", &value) != 1)
2843 err(1, "%s: failed to parse number from file", path);
2849 * cpu_is_first_core_in_package(cpu)
2850 * return 1 if given CPU is 1st core in package
2852 int cpu_is_first_core_in_package(int cpu)
2854 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
2857 int get_physical_package_id(int cpu)
2859 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
2862 int get_die_id(int cpu)
2864 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/die_id", cpu);
2867 int get_core_id(int cpu)
2869 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2872 void set_node_data(void)
2874 int pkg, node, lnode, cpu, cpux;
2877 /* initialize logical_node_id */
2878 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu)
2879 cpus[cpu].logical_node_id = -1;
2882 for (pkg = 0; pkg < topo.num_packages; pkg++) {
2884 for (cpu = 0; cpu <= topo.max_cpu_num; ++cpu) {
2885 if (cpus[cpu].physical_package_id != pkg)
2887 /* find a cpu with an unset logical_node_id */
2888 if (cpus[cpu].logical_node_id != -1)
2890 cpus[cpu].logical_node_id = lnode;
2891 node = cpus[cpu].physical_node_id;
2894 * find all matching cpus on this pkg and set
2895 * the logical_node_id
2897 for (cpux = cpu; cpux <= topo.max_cpu_num; cpux++) {
2898 if ((cpus[cpux].physical_package_id == pkg) && (cpus[cpux].physical_node_id == node)) {
2899 cpus[cpux].logical_node_id = lnode;
2904 if (lnode > topo.nodes_per_pkg)
2905 topo.nodes_per_pkg = lnode;
2907 if (cpu_count >= topo.max_cpu_num)
2912 int get_physical_node_id(struct cpu_topology *thiscpu)
2917 int cpu = thiscpu->logical_cpu_id;
2919 for (i = 0; i <= topo.max_cpu_num; i++) {
2920 sprintf(path, "/sys/devices/system/cpu/cpu%d/node%i/cpulist", cpu, i);
2921 filep = fopen(path, "r");
2930 int get_thread_siblings(struct cpu_topology *thiscpu)
2932 char path[80], character;
2935 int so, shift, sib_core;
2936 int cpu = thiscpu->logical_cpu_id;
2937 int offset = topo.max_cpu_num + 1;
2941 thiscpu->put_ids = CPU_ALLOC((topo.max_cpu_num + 1));
2942 if (thiscpu->thread_id < 0)
2943 thiscpu->thread_id = thread_id++;
2944 if (!thiscpu->put_ids)
2947 size = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
2948 CPU_ZERO_S(size, thiscpu->put_ids);
2950 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", cpu);
2951 filep = fopen(path, "r");
2954 warnx("%s: open failed", path);
2958 offset -= BITMASK_SIZE;
2959 if (fscanf(filep, "%lx%c", &map, &character) != 2)
2960 err(1, "%s: failed to parse file", path);
2961 for (shift = 0; shift < BITMASK_SIZE; shift++) {
2962 if ((map >> shift) & 0x1) {
2963 so = shift + offset;
2964 sib_core = get_core_id(so);
2965 if (sib_core == thiscpu->physical_core_id) {
2966 CPU_SET_S(so, size, thiscpu->put_ids);
2967 if ((so != cpu) && (cpus[so].thread_id < 0))
2968 cpus[so].thread_id = thread_id++;
2972 } while (character == ',');
2975 return CPU_COUNT_S(size, thiscpu->put_ids);
2979 * run func(thread, core, package) in topology order
2980 * skip non-present cpus
2983 int for_all_cpus_2(int (func) (struct thread_data *, struct core_data *,
2984 struct pkg_data *, struct thread_data *, struct core_data *,
2985 struct pkg_data *), struct thread_data *thread_base,
2986 struct core_data *core_base, struct pkg_data *pkg_base,
2987 struct thread_data *thread_base2, struct core_data *core_base2, struct pkg_data *pkg_base2)
2989 int retval, pkg_no, node_no, core_no, thread_no;
2991 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2992 for (node_no = 0; node_no < topo.nodes_per_pkg; ++node_no) {
2993 for (core_no = 0; core_no < topo.cores_per_node; ++core_no) {
2994 for (thread_no = 0; thread_no < topo.threads_per_core; ++thread_no) {
2995 struct thread_data *t, *t2;
2996 struct core_data *c, *c2;
2997 struct pkg_data *p, *p2;
2999 t = GET_THREAD(thread_base, thread_no, core_no, node_no, pkg_no);
3001 if (cpu_is_not_present(t->cpu_id))
3004 t2 = GET_THREAD(thread_base2, thread_no, core_no, node_no, pkg_no);
3006 c = GET_CORE(core_base, core_no, node_no, pkg_no);
3007 c2 = GET_CORE(core_base2, core_no, node_no, pkg_no);
3009 p = GET_PKG(pkg_base, pkg_no);
3010 p2 = GET_PKG(pkg_base2, pkg_no);
3012 retval = func(t, c, p, t2, c2, p2);
3023 * run func(cpu) on every cpu in /proc/stat
3024 * return max_cpu number
3026 int for_all_proc_cpus(int (func) (int))
3032 fp = fopen_or_die(proc_stat, "r");
3034 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
3036 err(1, "%s: failed to parse format", proc_stat);
3039 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
3043 retval = func(cpu_num);
3053 void re_initialize(void)
3056 setup_all_buffers();
3057 fprintf(outf, "turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
3060 void set_max_cpu_num(void)
3064 unsigned long dummy;
3067 base_cpu = sched_getcpu();
3069 err(1, "cannot find calling cpu ID");
3070 sprintf(pathname, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings", base_cpu);
3072 filep = fopen_or_die(pathname, "r");
3073 topo.max_cpu_num = 0;
3074 while (fscanf(filep, "%lx,", &dummy) == 1)
3075 topo.max_cpu_num += BITMASK_SIZE;
3077 topo.max_cpu_num--; /* 0 based */
3082 * remember the last one seen, it will be the max
3084 int count_cpus(int cpu)
3092 int mark_cpu_present(int cpu)
3094 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
3098 int init_thread_id(int cpu)
3100 cpus[cpu].thread_id = -1;
3105 * snapshot_proc_interrupts()
3107 * read and record summary of /proc/interrupts
3109 * return 1 if config change requires a restart, else return 0
3111 int snapshot_proc_interrupts(void)
3117 fp = fopen_or_die("/proc/interrupts", "r");
3121 /* read 1st line of /proc/interrupts to get cpu* name for each column */
3122 for (column = 0; column < topo.num_cpus; ++column) {
3125 retval = fscanf(fp, " CPU%d", &cpu_number);
3129 if (cpu_number > topo.max_cpu_num) {
3130 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
3134 irq_column_2_cpu[column] = cpu_number;
3135 irqs_per_cpu[cpu_number] = 0;
3138 /* read /proc/interrupt count lines and sum up irqs per cpu */
3143 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
3147 /* read the count per cpu */
3148 for (column = 0; column < topo.num_cpus; ++column) {
3150 int cpu_number, irq_count;
3152 retval = fscanf(fp, " %d", &irq_count);
3156 cpu_number = irq_column_2_cpu[column];
3157 irqs_per_cpu[cpu_number] += irq_count;
3161 while (getc(fp) != '\n') ; /* flush interrupt description */
3168 * snapshot_gfx_rc6_ms()
3170 * record snapshot of
3171 * /sys/class/drm/card0/power/rc6_residency_ms
3173 * return 1 if config change requires a restart, else return 0
3175 int snapshot_gfx_rc6_ms(void)
3180 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
3182 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
3192 * snapshot_gfx_mhz()
3194 * record snapshot of
3195 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
3197 * return 1 if config change requires a restart, else return 0
3199 int snapshot_gfx_mhz(void)
3205 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
3211 retval = fscanf(fp, "%d", &gfx_cur_mhz);
3219 * snapshot_gfx_cur_mhz()
3221 * record snapshot of
3222 * /sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz
3224 * return 1 if config change requires a restart, else return 0
3226 int snapshot_gfx_act_mhz(void)
3232 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", "r");
3238 retval = fscanf(fp, "%d", &gfx_act_mhz);
3240 err(1, "GFX ACT MHz");
3246 * snapshot_cpu_lpi()
3248 * record snapshot of
3249 * /sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us
3251 int snapshot_cpu_lpi_us(void)
3256 fp = fopen_or_die("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", "r");
3258 retval = fscanf(fp, "%lld", &cpuidle_cur_cpu_lpi_us);
3260 fprintf(stderr, "Disabling Low Power Idle CPU output\n");
3261 BIC_NOT_PRESENT(BIC_CPU_LPI);
3272 * snapshot_sys_lpi()
3274 * record snapshot of sys_lpi_file
3276 int snapshot_sys_lpi_us(void)
3281 fp = fopen_or_die(sys_lpi_file, "r");
3283 retval = fscanf(fp, "%lld", &cpuidle_cur_sys_lpi_us);
3285 fprintf(stderr, "Disabling Low Power Idle System output\n");
3286 BIC_NOT_PRESENT(BIC_SYS_LPI);
3296 * snapshot /proc and /sys files
3298 * return 1 if configuration restart needed, else return 0
3300 int snapshot_proc_sysfs_files(void)
3302 if (DO_BIC(BIC_IRQ))
3303 if (snapshot_proc_interrupts())
3306 if (DO_BIC(BIC_GFX_rc6))
3307 snapshot_gfx_rc6_ms();
3309 if (DO_BIC(BIC_GFXMHz))
3312 if (DO_BIC(BIC_GFXACTMHz))
3313 snapshot_gfx_act_mhz();
3315 if (DO_BIC(BIC_CPU_LPI))
3316 snapshot_cpu_lpi_us();
3318 if (DO_BIC(BIC_SYS_LPI))
3319 snapshot_sys_lpi_us();
3326 static void signal_handler(int signal)
3332 fprintf(stderr, " SIGINT\n");
3336 fprintf(stderr, "SIGUSR1\n");
3341 void setup_signal_handler(void)
3343 struct sigaction sa;
3345 memset(&sa, 0, sizeof(sa));
3347 sa.sa_handler = &signal_handler;
3349 if (sigaction(SIGINT, &sa, NULL) < 0)
3350 err(1, "sigaction SIGINT");
3351 if (sigaction(SIGUSR1, &sa, NULL) < 0)
3352 err(1, "sigaction SIGUSR1");
3357 struct timeval tout;
3358 struct timespec rest;
3363 FD_SET(0, &readfds);
3366 nanosleep(&interval_ts, NULL);
3371 retval = select(1, &readfds, NULL, NULL, &tout);
3374 switch (getc(stdin)) {
3380 * 'stdin' is a pipe closed on the other end. There
3381 * won't be any further input.
3384 /* Sleep the rest of the time */
3385 rest.tv_sec = (tout.tv_sec + tout.tv_usec / 1000000);
3386 rest.tv_nsec = (tout.tv_usec % 1000000) * 1000;
3387 nanosleep(&rest, NULL);
3392 int get_msr_sum(int cpu, off_t offset, unsigned long long *msr)
3395 unsigned long long msr_cur, msr_last;
3397 if (!per_cpu_msr_sum)
3400 idx = offset_to_idx(offset);
3403 /* get_msr_sum() = sum + (get_msr() - last) */
3404 ret = get_msr(cpu, offset, &msr_cur);
3407 msr_last = per_cpu_msr_sum[cpu].entries[idx].last;
3408 DELTA_WRAP32(msr_cur, msr_last);
3409 *msr = msr_last + per_cpu_msr_sum[cpu].entries[idx].sum;
3416 /* Timer callback, update the sum of MSRs periodically. */
3417 static int update_msr_sum(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3420 int cpu = t->cpu_id;
3425 for (i = IDX_PKG_ENERGY; i < IDX_COUNT; i++) {
3426 unsigned long long msr_cur, msr_last;
3431 offset = idx_to_offset(i);
3434 ret = get_msr(cpu, offset, &msr_cur);
3436 fprintf(outf, "Can not update msr(0x%llx)\n", (unsigned long long)offset);
3440 msr_last = per_cpu_msr_sum[cpu].entries[i].last;
3441 per_cpu_msr_sum[cpu].entries[i].last = msr_cur & 0xffffffff;
3443 DELTA_WRAP32(msr_cur, msr_last);
3444 per_cpu_msr_sum[cpu].entries[i].sum += msr_last;
3449 static void msr_record_handler(union sigval v)
3453 for_all_cpus(update_msr_sum, EVEN_COUNTERS);
3456 void msr_sum_record(void)
3458 struct itimerspec its;
3459 struct sigevent sev;
3461 per_cpu_msr_sum = calloc(topo.max_cpu_num + 1, sizeof(struct msr_sum_array));
3462 if (!per_cpu_msr_sum) {
3463 fprintf(outf, "Can not allocate memory for long time MSR.\n");
3467 * Signal handler might be restricted, so use thread notifier instead.
3469 memset(&sev, 0, sizeof(struct sigevent));
3470 sev.sigev_notify = SIGEV_THREAD;
3471 sev.sigev_notify_function = msr_record_handler;
3473 sev.sigev_value.sival_ptr = &timerid;
3474 if (timer_create(CLOCK_REALTIME, &sev, &timerid) == -1) {
3475 fprintf(outf, "Can not create timer.\n");
3479 its.it_value.tv_sec = 0;
3480 its.it_value.tv_nsec = 1;
3482 * A wraparound time has been calculated early.
3483 * Some sources state that the peak power for a
3484 * microprocessor is usually 1.5 times the TDP rating,
3485 * use 2 * TDP for safety.
3487 its.it_interval.tv_sec = rapl_joule_counter_range / 2;
3488 its.it_interval.tv_nsec = 0;
3490 if (timer_settime(timerid, 0, &its, NULL) == -1) {
3491 fprintf(outf, "Can not set timer.\n");
3497 timer_delete(timerid);
3499 free(per_cpu_msr_sum);
3503 * set_my_sched_priority(pri)
3506 int set_my_sched_priority(int priority)
3509 int original_priority;
3512 original_priority = getpriority(PRIO_PROCESS, 0);
3513 if (errno && (original_priority == -1))
3514 err(errno, "getpriority");
3516 retval = setpriority(PRIO_PROCESS, 0, priority);
3518 errx(retval, "capget(CAP_SYS_NICE) failed,try \"# setcap cap_sys_nice=ep %s\"", progname);
3521 retval = getpriority(PRIO_PROCESS, 0);
3522 if (retval != priority)
3523 err(retval, "getpriority(%d) != setpriority(%d)", retval, priority);
3525 return original_priority;
3528 void turbostat_loop()
3532 unsigned int done_iters = 0;
3534 setup_signal_handler();
3537 * elevate own priority for interval mode
3539 set_my_sched_priority(-20);
3544 snapshot_proc_sysfs_files();
3545 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3546 first_counter_read = 0;
3549 } else if (retval == -1) {
3550 if (restarted > 10) {
3558 gettimeofday(&tv_even, (struct timezone *)NULL);
3561 if (for_all_proc_cpus(cpu_is_not_present)) {
3566 if (snapshot_proc_sysfs_files())
3568 retval = for_all_cpus(get_counters, ODD_COUNTERS);
3571 } else if (retval == -1) {
3575 gettimeofday(&tv_odd, (struct timezone *)NULL);
3576 timersub(&tv_odd, &tv_even, &tv_delta);
3577 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
3581 compute_average(EVEN_COUNTERS);
3582 format_all_counters(EVEN_COUNTERS);
3583 flush_output_stdout();
3586 if (num_iterations && ++done_iters >= num_iterations)
3589 if (snapshot_proc_sysfs_files())
3591 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
3594 } else if (retval == -1) {
3598 gettimeofday(&tv_even, (struct timezone *)NULL);
3599 timersub(&tv_even, &tv_odd, &tv_delta);
3600 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
3604 compute_average(ODD_COUNTERS);
3605 format_all_counters(ODD_COUNTERS);
3606 flush_output_stdout();
3609 if (num_iterations && ++done_iters >= num_iterations)
3614 void check_dev_msr()
3619 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3620 if (stat(pathname, &sb))
3621 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
3622 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
3626 * check for CAP_SYS_RAWIO
3627 * return 0 on success
3630 int check_for_cap_sys_rawio(void)
3633 cap_flag_value_t cap_flag_value;
3635 caps = cap_get_proc();
3637 err(-6, "cap_get_proc\n");
3639 if (cap_get_flag(caps, CAP_SYS_RAWIO, CAP_EFFECTIVE, &cap_flag_value))
3640 err(-6, "cap_get\n");
3642 if (cap_flag_value != CAP_SET) {
3643 warnx("capget(CAP_SYS_RAWIO) failed," " try \"# setcap cap_sys_rawio=ep %s\"", progname);
3647 if (cap_free(caps) == -1)
3648 err(-6, "cap_free\n");
3653 void check_permissions(void)
3658 /* check for CAP_SYS_RAWIO */
3659 do_exit += check_for_cap_sys_rawio();
3661 /* test file permissions */
3662 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
3663 if (euidaccess(pathname, R_OK)) {
3665 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
3668 /* if all else fails, thell them to be root */
3671 warnx("... or simply run as root");
3678 * NHM adds support for additional MSRs:
3680 * MSR_SMI_COUNT 0x00000034
3682 * MSR_PLATFORM_INFO 0x000000ce
3683 * MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
3685 * MSR_MISC_PWR_MGMT 0x000001aa
3687 * MSR_PKG_C3_RESIDENCY 0x000003f8
3688 * MSR_PKG_C6_RESIDENCY 0x000003f9
3689 * MSR_CORE_C3_RESIDENCY 0x000003fc
3690 * MSR_CORE_C6_RESIDENCY 0x000003fd
3693 * sets global pkg_cstate_limit to decode MSR_PKG_CST_CONFIG_CONTROL
3694 * sets has_misc_feature_control
3696 int probe_nhm_msrs(unsigned int family, unsigned int model)
3698 unsigned long long msr;
3699 unsigned int base_ratio;
3700 int *pkg_cstate_limits;
3708 bclk = discover_bclk(family, model);
3711 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
3712 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3713 pkg_cstate_limits = nhm_pkg_cstate_limits;
3715 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
3716 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
3717 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3718 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3719 pkg_cstate_limits = snb_pkg_cstate_limits;
3720 has_misc_feature_control = 1;
3722 case INTEL_FAM6_HASWELL: /* HSW */
3723 case INTEL_FAM6_HASWELL_G: /* HSW */
3724 case INTEL_FAM6_HASWELL_X: /* HSX */
3725 case INTEL_FAM6_HASWELL_L: /* HSW */
3726 case INTEL_FAM6_BROADWELL: /* BDW */
3727 case INTEL_FAM6_BROADWELL_G: /* BDW */
3728 case INTEL_FAM6_BROADWELL_X: /* BDX */
3729 case INTEL_FAM6_SKYLAKE_L: /* SKL */
3730 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
3731 pkg_cstate_limits = hsw_pkg_cstate_limits;
3732 has_misc_feature_control = 1;
3734 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3735 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
3736 pkg_cstate_limits = skx_pkg_cstate_limits;
3737 has_misc_feature_control = 1;
3739 case INTEL_FAM6_ICELAKE_X: /* ICX */
3740 pkg_cstate_limits = icx_pkg_cstate_limits;
3741 has_misc_feature_control = 1;
3743 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
3744 no_MSR_MISC_PWR_MGMT = 1;
3746 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
3747 pkg_cstate_limits = slv_pkg_cstate_limits;
3749 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
3750 pkg_cstate_limits = amt_pkg_cstate_limits;
3751 no_MSR_MISC_PWR_MGMT = 1;
3753 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
3754 pkg_cstate_limits = phi_pkg_cstate_limits;
3756 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3757 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
3758 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
3759 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
3760 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
3761 pkg_cstate_limits = glm_pkg_cstate_limits;
3766 get_msr(base_cpu, MSR_PKG_CST_CONFIG_CONTROL, &msr);
3767 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
3769 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
3770 base_ratio = (msr >> 8) & 0xFF;
3772 base_hz = base_ratio * bclk * 1000000;
3778 * SLV client has support for unique MSRs:
3780 * MSR_CC6_DEMOTION_POLICY_CONFIG
3781 * MSR_MC6_DEMOTION_POLICY_CONFIG
3784 int has_slv_msrs(unsigned int family, unsigned int model)
3793 case INTEL_FAM6_ATOM_SILVERMONT:
3794 case INTEL_FAM6_ATOM_SILVERMONT_MID:
3795 case INTEL_FAM6_ATOM_AIRMONT_MID:
3801 int is_dnv(unsigned int family, unsigned int model)
3811 case INTEL_FAM6_ATOM_GOLDMONT_D:
3817 int is_bdx(unsigned int family, unsigned int model)
3827 case INTEL_FAM6_BROADWELL_X:
3833 int is_skx(unsigned int family, unsigned int model)
3843 case INTEL_FAM6_SKYLAKE_X:
3849 int is_icx(unsigned int family, unsigned int model)
3859 case INTEL_FAM6_ICELAKE_X:
3865 int is_spr(unsigned int family, unsigned int model)
3875 case INTEL_FAM6_SAPPHIRERAPIDS_X:
3881 int is_ehl(unsigned int family, unsigned int model)
3890 case INTEL_FAM6_ATOM_TREMONT:
3896 int is_jvl(unsigned int family, unsigned int model)
3905 case INTEL_FAM6_ATOM_TREMONT_D:
3911 int has_turbo_ratio_limit(unsigned int family, unsigned int model)
3913 if (has_slv_msrs(family, model))
3920 /* Nehalem compatible, but do not include turbo-ratio limit support */
3921 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
3922 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
3929 int has_atom_turbo_ratio_limit(unsigned int family, unsigned int model)
3931 if (has_slv_msrs(family, model))
3937 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
3946 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3947 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3954 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
3963 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
3970 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
3979 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
3986 int has_glm_turbo_ratio_limit(unsigned int family, unsigned int model)
3995 case INTEL_FAM6_ATOM_GOLDMONT:
3996 case INTEL_FAM6_SKYLAKE_X:
3997 case INTEL_FAM6_ICELAKE_X:
3998 case INTEL_FAM6_SAPPHIRERAPIDS_X:
4005 int has_config_tdp(unsigned int family, unsigned int model)
4014 case INTEL_FAM6_IVYBRIDGE: /* IVB */
4015 case INTEL_FAM6_HASWELL: /* HSW */
4016 case INTEL_FAM6_HASWELL_X: /* HSX */
4017 case INTEL_FAM6_HASWELL_L: /* HSW */
4018 case INTEL_FAM6_HASWELL_G: /* HSW */
4019 case INTEL_FAM6_BROADWELL: /* BDW */
4020 case INTEL_FAM6_BROADWELL_G: /* BDW */
4021 case INTEL_FAM6_BROADWELL_X: /* BDX */
4022 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4023 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4024 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4025 case INTEL_FAM6_ICELAKE_X: /* ICX */
4026 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
4027 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
4036 * 0: Tcc Offset not supported (Default)
4037 * 6: Bit 29:24 of MSR_PLATFORM_INFO
4038 * 4: Bit 27:24 of MSR_PLATFORM_INFO
4040 void check_tcc_offset(int model)
4042 unsigned long long msr;
4048 case INTEL_FAM6_SKYLAKE_L:
4049 case INTEL_FAM6_SKYLAKE:
4050 case INTEL_FAM6_KABYLAKE_L:
4051 case INTEL_FAM6_KABYLAKE:
4052 case INTEL_FAM6_ICELAKE_L:
4053 case INTEL_FAM6_ICELAKE:
4054 case INTEL_FAM6_TIGERLAKE_L:
4055 case INTEL_FAM6_TIGERLAKE:
4056 case INTEL_FAM6_COMETLAKE:
4057 if (!get_msr(base_cpu, MSR_PLATFORM_INFO, &msr)) {
4058 msr = (msr >> 30) & 1;
4060 tcc_offset_bits = 6;
4068 static void remove_underbar(char *s)
4081 static void dump_turbo_ratio_info(unsigned int family, unsigned int model)
4086 if (has_hsw_turbo_ratio_limit(family, model))
4087 dump_hsw_turbo_ratio_limits();
4089 if (has_ivt_turbo_ratio_limit(family, model))
4090 dump_ivt_turbo_ratio_limits();
4092 if (has_turbo_ratio_limit(family, model)) {
4093 dump_turbo_ratio_limits(MSR_TURBO_RATIO_LIMIT, family, model);
4096 dump_turbo_ratio_limits(MSR_SECONDARY_TURBO_RATIO_LIMIT, family, model);
4099 if (has_atom_turbo_ratio_limit(family, model))
4100 dump_atom_turbo_ratio_limits();
4102 if (has_knl_turbo_ratio_limit(family, model))
4103 dump_knl_turbo_ratio_limits();
4105 if (has_config_tdp(family, model))
4109 static void dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
4111 if (!do_nhm_platform_info)
4114 dump_nhm_platform_info();
4115 dump_turbo_ratio_info(family, model);
4119 static int read_sysfs_int(char *path)
4124 input = fopen(path, "r");
4125 if (input == NULL) {
4127 fprintf(outf, "NSFOD %s\n", path);
4130 if (fscanf(input, "%d", &retval) != 1)
4131 err(1, "%s: failed to read int from file", path);
4137 static void dump_sysfs_file(char *path)
4140 char cpuidle_buf[64];
4142 input = fopen(path, "r");
4143 if (input == NULL) {
4145 fprintf(outf, "NSFOD %s\n", path);
4148 if (!fgets(cpuidle_buf, sizeof(cpuidle_buf), input))
4149 err(1, "%s: failed to read file", path);
4152 fprintf(outf, "%s: %s", strrchr(path, '/') + 1, cpuidle_buf);
4155 static void intel_uncore_frequency_probe(void)
4163 if (access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00", R_OK))
4166 /* Cluster level sysfs not supported yet. */
4167 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/uncore00", R_OK))
4170 if (!access("/sys/devices/system/cpu/intel_uncore_frequency/package_00_die_00/current_freq_khz", R_OK))
4171 BIC_PRESENT(BIC_UNCORE_MHZ);
4176 for (i = 0; i < topo.num_packages; ++i) {
4177 for (j = 0; j < topo.num_die; ++j) {
4180 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/min_freq_khz",
4182 k = read_sysfs_int(path);
4183 sprintf(path, "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/max_freq_khz",
4185 l = read_sysfs_int(path);
4186 fprintf(outf, "Uncore Frequency pkg%d die%d: %d - %d MHz ", i, j, k / 1000, l / 1000);
4189 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_min_freq_khz",
4191 k = read_sysfs_int(path);
4193 "/sys/devices/system/cpu/intel_uncore_frequency/package_0%d_die_0%d/initial_max_freq_khz",
4195 l = read_sysfs_int(path);
4196 fprintf(outf, "(%d - %d MHz)\n", k / 1000, l / 1000);
4201 static void dump_sysfs_cstate_config(void)
4210 if (access("/sys/devices/system/cpu/cpuidle", R_OK)) {
4211 fprintf(outf, "cpuidle not loaded\n");
4215 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_driver");
4216 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor");
4217 dump_sysfs_file("/sys/devices/system/cpu/cpuidle/current_governor_ro");
4219 for (state = 0; state < 10; ++state) {
4221 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
4222 input = fopen(path, "r");
4225 if (!fgets(name_buf, sizeof(name_buf), input))
4226 err(1, "%s: failed to read file", path);
4228 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
4229 sp = strchr(name_buf, '-');
4231 sp = strchrnul(name_buf, '\n');
4235 remove_underbar(name_buf);
4237 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/desc", base_cpu, state);
4238 input = fopen(path, "r");
4241 if (!fgets(desc, sizeof(desc), input))
4242 err(1, "%s: failed to read file", path);
4244 fprintf(outf, "cpu%d: %s: %s", base_cpu, name_buf, desc);
4249 static void dump_sysfs_pstate_config(void)
4252 char driver_buf[64];
4253 char governor_buf[64];
4257 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_driver", base_cpu);
4258 input = fopen(path, "r");
4259 if (input == NULL) {
4260 fprintf(outf, "NSFOD %s\n", path);
4263 if (!fgets(driver_buf, sizeof(driver_buf), input))
4264 err(1, "%s: failed to read file", path);
4267 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpufreq/scaling_governor", base_cpu);
4268 input = fopen(path, "r");
4269 if (input == NULL) {
4270 fprintf(outf, "NSFOD %s\n", path);
4273 if (!fgets(governor_buf, sizeof(governor_buf), input))
4274 err(1, "%s: failed to read file", path);
4277 fprintf(outf, "cpu%d: cpufreq driver: %s", base_cpu, driver_buf);
4278 fprintf(outf, "cpu%d: cpufreq governor: %s", base_cpu, governor_buf);
4280 sprintf(path, "/sys/devices/system/cpu/cpufreq/boost");
4281 input = fopen(path, "r");
4282 if (input != NULL) {
4283 if (fscanf(input, "%d", &turbo) != 1)
4284 err(1, "%s: failed to parse number from file", path);
4285 fprintf(outf, "cpufreq boost: %d\n", turbo);
4289 sprintf(path, "/sys/devices/system/cpu/intel_pstate/no_turbo");
4290 input = fopen(path, "r");
4291 if (input != NULL) {
4292 if (fscanf(input, "%d", &turbo) != 1)
4293 err(1, "%s: failed to parse number from file", path);
4294 fprintf(outf, "cpufreq intel_pstate no_turbo: %d\n", turbo);
4301 * Decode the ENERGY_PERF_BIAS MSR
4303 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4316 /* EPB is per-package */
4317 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4320 if (cpu_migrate(cpu)) {
4321 fprintf(outf, "print_epb: Could not migrate to CPU %d\n", cpu);
4330 case ENERGY_PERF_BIAS_PERFORMANCE:
4331 epb_string = "performance";
4333 case ENERGY_PERF_BIAS_NORMAL:
4334 epb_string = "balanced";
4336 case ENERGY_PERF_BIAS_POWERSAVE:
4337 epb_string = "powersave";
4340 epb_string = "custom";
4343 fprintf(outf, "cpu%d: EPB: %d (%s)\n", cpu, epb, epb_string);
4350 * Decode the MSR_HWP_CAPABILITIES
4352 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4354 unsigned long long msr;
4365 /* MSR_HWP_CAPABILITIES is per-package */
4366 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4369 if (cpu_migrate(cpu)) {
4370 fprintf(outf, "print_hwp: Could not migrate to CPU %d\n", cpu);
4374 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
4377 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", cpu, msr, (msr & (1 << 0)) ? "" : "No-");
4379 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
4380 if ((msr & (1 << 0)) == 0)
4383 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
4386 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
4387 "(high %d guar %d eff %d low %d)\n",
4389 (unsigned int)HWP_HIGHEST_PERF(msr),
4390 (unsigned int)HWP_GUARANTEED_PERF(msr),
4391 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), (unsigned int)HWP_LOWEST_PERF(msr));
4393 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
4396 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
4397 "(min %d max %d des %d epp 0x%x window 0x%x pkg 0x%x)\n",
4399 (unsigned int)(((msr) >> 0) & 0xff),
4400 (unsigned int)(((msr) >> 8) & 0xff),
4401 (unsigned int)(((msr) >> 16) & 0xff),
4402 (unsigned int)(((msr) >> 24) & 0xff),
4403 (unsigned int)(((msr) >> 32) & 0xff3), (unsigned int)(((msr) >> 42) & 0x1));
4406 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
4409 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
4410 "(min %d max %d des %d epp 0x%x window 0x%x)\n",
4412 (unsigned int)(((msr) >> 0) & 0xff),
4413 (unsigned int)(((msr) >> 8) & 0xff),
4414 (unsigned int)(((msr) >> 16) & 0xff),
4415 (unsigned int)(((msr) >> 24) & 0xff), (unsigned int)(((msr) >> 32) & 0xff3));
4417 if (has_hwp_notify) {
4418 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
4421 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
4422 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
4423 cpu, msr, ((msr) & 0x1) ? "EN" : "Dis", ((msr) & 0x2) ? "EN" : "Dis");
4425 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
4428 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
4429 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
4430 cpu, msr, ((msr) & 0x1) ? "" : "No-", ((msr) & 0x4) ? "" : "No-");
4436 * print_perf_limit()
4438 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4440 unsigned long long msr;
4449 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4452 if (cpu_migrate(cpu)) {
4453 fprintf(outf, "print_perf_limit: Could not migrate to CPU %d\n", cpu);
4457 if (do_core_perf_limit_reasons) {
4458 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
4459 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4460 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
4461 (msr & 1 << 15) ? "bit15, " : "",
4462 (msr & 1 << 14) ? "bit14, " : "",
4463 (msr & 1 << 13) ? "Transitions, " : "",
4464 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
4465 (msr & 1 << 11) ? "PkgPwrL2, " : "",
4466 (msr & 1 << 10) ? "PkgPwrL1, " : "",
4467 (msr & 1 << 9) ? "CorePwr, " : "",
4468 (msr & 1 << 8) ? "Amps, " : "",
4469 (msr & 1 << 6) ? "VR-Therm, " : "",
4470 (msr & 1 << 5) ? "Auto-HWP, " : "",
4471 (msr & 1 << 4) ? "Graphics, " : "",
4472 (msr & 1 << 2) ? "bit2, " : "",
4473 (msr & 1 << 1) ? "ThermStatus, " : "", (msr & 1 << 0) ? "PROCHOT, " : "");
4474 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
4475 (msr & 1 << 31) ? "bit31, " : "",
4476 (msr & 1 << 30) ? "bit30, " : "",
4477 (msr & 1 << 29) ? "Transitions, " : "",
4478 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
4479 (msr & 1 << 27) ? "PkgPwrL2, " : "",
4480 (msr & 1 << 26) ? "PkgPwrL1, " : "",
4481 (msr & 1 << 25) ? "CorePwr, " : "",
4482 (msr & 1 << 24) ? "Amps, " : "",
4483 (msr & 1 << 22) ? "VR-Therm, " : "",
4484 (msr & 1 << 21) ? "Auto-HWP, " : "",
4485 (msr & 1 << 20) ? "Graphics, " : "",
4486 (msr & 1 << 18) ? "bit18, " : "",
4487 (msr & 1 << 17) ? "ThermStatus, " : "", (msr & 1 << 16) ? "PROCHOT, " : "");
4490 if (do_gfx_perf_limit_reasons) {
4491 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
4492 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4493 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
4494 (msr & 1 << 0) ? "PROCHOT, " : "",
4495 (msr & 1 << 1) ? "ThermStatus, " : "",
4496 (msr & 1 << 4) ? "Graphics, " : "",
4497 (msr & 1 << 6) ? "VR-Therm, " : "",
4498 (msr & 1 << 8) ? "Amps, " : "",
4499 (msr & 1 << 9) ? "GFXPwr, " : "",
4500 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4501 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
4502 (msr & 1 << 16) ? "PROCHOT, " : "",
4503 (msr & 1 << 17) ? "ThermStatus, " : "",
4504 (msr & 1 << 20) ? "Graphics, " : "",
4505 (msr & 1 << 22) ? "VR-Therm, " : "",
4506 (msr & 1 << 24) ? "Amps, " : "",
4507 (msr & 1 << 25) ? "GFXPwr, " : "",
4508 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4510 if (do_ring_perf_limit_reasons) {
4511 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
4512 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
4513 fprintf(outf, " (Active: %s%s%s%s%s%s)",
4514 (msr & 1 << 0) ? "PROCHOT, " : "",
4515 (msr & 1 << 1) ? "ThermStatus, " : "",
4516 (msr & 1 << 6) ? "VR-Therm, " : "",
4517 (msr & 1 << 8) ? "Amps, " : "",
4518 (msr & 1 << 10) ? "PkgPwrL1, " : "", (msr & 1 << 11) ? "PkgPwrL2, " : "");
4519 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
4520 (msr & 1 << 16) ? "PROCHOT, " : "",
4521 (msr & 1 << 17) ? "ThermStatus, " : "",
4522 (msr & 1 << 22) ? "VR-Therm, " : "",
4523 (msr & 1 << 24) ? "Amps, " : "",
4524 (msr & 1 << 26) ? "PkgPwrL1, " : "", (msr & 1 << 27) ? "PkgPwrL2, " : "");
4529 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
4530 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
4532 double get_tdp_intel(unsigned int model)
4534 unsigned long long msr;
4536 if (do_rapl & RAPL_PKG_POWER_INFO)
4537 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
4538 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
4541 case INTEL_FAM6_ATOM_SILVERMONT:
4542 case INTEL_FAM6_ATOM_SILVERMONT_D:
4549 double get_tdp_amd(unsigned int family)
4553 /* This is the max stock TDP of HEDT/Server Fam17h+ chips */
4558 * rapl_dram_energy_units_probe()
4559 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
4561 static double rapl_dram_energy_units_probe(int model, double rapl_energy_units)
4563 /* only called for genuine_intel, family 6 */
4566 case INTEL_FAM6_HASWELL_X: /* HSX */
4567 case INTEL_FAM6_BROADWELL_X: /* BDX */
4568 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4569 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4570 case INTEL_FAM6_ICELAKE_X: /* ICX */
4571 return (rapl_dram_energy_units = 15.3 / 1000000);
4573 return (rapl_energy_units);
4577 void rapl_probe_intel(unsigned int family, unsigned int model)
4579 unsigned long long msr;
4580 unsigned int time_unit;
4587 case INTEL_FAM6_SANDYBRIDGE:
4588 case INTEL_FAM6_IVYBRIDGE:
4589 case INTEL_FAM6_HASWELL: /* HSW */
4590 case INTEL_FAM6_HASWELL_L: /* HSW */
4591 case INTEL_FAM6_HASWELL_G: /* HSW */
4592 case INTEL_FAM6_BROADWELL: /* BDW */
4593 case INTEL_FAM6_BROADWELL_G: /* BDW */
4594 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
4596 BIC_PRESENT(BIC_Pkg_J);
4597 BIC_PRESENT(BIC_Cor_J);
4598 BIC_PRESENT(BIC_GFX_J);
4600 BIC_PRESENT(BIC_PkgWatt);
4601 BIC_PRESENT(BIC_CorWatt);
4602 BIC_PRESENT(BIC_GFXWatt);
4605 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
4606 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
4607 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
4609 BIC_PRESENT(BIC_Pkg_J);
4611 BIC_PRESENT(BIC_PkgWatt);
4613 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
4615 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4616 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4618 BIC_PRESENT(BIC_Pkg_J);
4619 BIC_PRESENT(BIC_Cor_J);
4620 BIC_PRESENT(BIC_RAM_J);
4621 BIC_PRESENT(BIC_GFX_J);
4623 BIC_PRESENT(BIC_PkgWatt);
4624 BIC_PRESENT(BIC_CorWatt);
4625 BIC_PRESENT(BIC_RAMWatt);
4626 BIC_PRESENT(BIC_GFXWatt);
4629 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
4630 do_rapl = RAPL_PKG | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
4631 BIC_PRESENT(BIC_PKG__);
4633 BIC_PRESENT(BIC_Pkg_J);
4635 BIC_PRESENT(BIC_PkgWatt);
4637 case INTEL_FAM6_SKYLAKE_L: /* SKL */
4638 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
4640 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS
4641 | RAPL_GFX | RAPL_PKG_POWER_INFO;
4642 BIC_PRESENT(BIC_PKG__);
4643 BIC_PRESENT(BIC_RAM__);
4645 BIC_PRESENT(BIC_Pkg_J);
4646 BIC_PRESENT(BIC_Cor_J);
4647 BIC_PRESENT(BIC_RAM_J);
4648 BIC_PRESENT(BIC_GFX_J);
4650 BIC_PRESENT(BIC_PkgWatt);
4651 BIC_PRESENT(BIC_CorWatt);
4652 BIC_PRESENT(BIC_RAMWatt);
4653 BIC_PRESENT(BIC_GFXWatt);
4656 case INTEL_FAM6_HASWELL_X: /* HSX */
4657 case INTEL_FAM6_BROADWELL_X: /* BDX */
4658 case INTEL_FAM6_SKYLAKE_X: /* SKX */
4659 case INTEL_FAM6_ICELAKE_X: /* ICX */
4660 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
4661 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
4663 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4664 RAPL_PKG_POWER_INFO;
4665 BIC_PRESENT(BIC_PKG__);
4666 BIC_PRESENT(BIC_RAM__);
4668 BIC_PRESENT(BIC_Pkg_J);
4669 BIC_PRESENT(BIC_RAM_J);
4671 BIC_PRESENT(BIC_PkgWatt);
4672 BIC_PRESENT(BIC_RAMWatt);
4675 case INTEL_FAM6_SANDYBRIDGE_X:
4676 case INTEL_FAM6_IVYBRIDGE_X:
4678 RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS |
4679 RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
4680 BIC_PRESENT(BIC_PKG__);
4681 BIC_PRESENT(BIC_RAM__);
4683 BIC_PRESENT(BIC_Pkg_J);
4684 BIC_PRESENT(BIC_Cor_J);
4685 BIC_PRESENT(BIC_RAM_J);
4687 BIC_PRESENT(BIC_PkgWatt);
4688 BIC_PRESENT(BIC_CorWatt);
4689 BIC_PRESENT(BIC_RAMWatt);
4692 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
4693 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
4694 do_rapl = RAPL_PKG | RAPL_CORES;
4696 BIC_PRESENT(BIC_Pkg_J);
4697 BIC_PRESENT(BIC_Cor_J);
4699 BIC_PRESENT(BIC_PkgWatt);
4700 BIC_PRESENT(BIC_CorWatt);
4703 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
4705 RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS |
4706 RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
4707 BIC_PRESENT(BIC_PKG__);
4708 BIC_PRESENT(BIC_RAM__);
4710 BIC_PRESENT(BIC_Pkg_J);
4711 BIC_PRESENT(BIC_Cor_J);
4712 BIC_PRESENT(BIC_RAM_J);
4714 BIC_PRESENT(BIC_PkgWatt);
4715 BIC_PRESENT(BIC_CorWatt);
4716 BIC_PRESENT(BIC_RAMWatt);
4723 /* units on package 0, verify later other packages match */
4724 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
4727 rapl_power_units = 1.0 / (1 << (msr & 0xF));
4728 if (model == INTEL_FAM6_ATOM_SILVERMONT)
4729 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
4731 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
4733 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
4735 time_unit = msr >> 16 & 0xF;
4739 rapl_time_units = 1.0 / (1 << (time_unit));
4741 tdp = get_tdp_intel(model);
4743 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4745 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4748 void rapl_probe_amd(unsigned int family, unsigned int model)
4750 unsigned long long msr;
4751 unsigned int eax, ebx, ecx, edx;
4752 unsigned int has_rapl = 0;
4757 if (max_extended_level >= 0x80000007) {
4758 __cpuid(0x80000007, eax, ebx, ecx, edx);
4759 /* RAPL (Fam 17h+) */
4760 has_rapl = edx & (1 << 14);
4763 if (!has_rapl || family < 0x17)
4766 do_rapl = RAPL_AMD_F17H | RAPL_PER_CORE_ENERGY;
4768 BIC_PRESENT(BIC_Pkg_J);
4769 BIC_PRESENT(BIC_Cor_J);
4771 BIC_PRESENT(BIC_PkgWatt);
4772 BIC_PRESENT(BIC_CorWatt);
4775 if (get_msr(base_cpu, MSR_RAPL_PWR_UNIT, &msr))
4778 rapl_time_units = ldexp(1.0, -(msr >> 16 & 0xf));
4779 rapl_energy_units = ldexp(1.0, -(msr >> 8 & 0x1f));
4780 rapl_power_units = ldexp(1.0, -(msr & 0xf));
4782 tdp = get_tdp_amd(family);
4784 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
4786 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
4792 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
4794 void rapl_probe(unsigned int family, unsigned int model)
4797 rapl_probe_intel(family, model);
4798 if (authentic_amd || hygon_genuine)
4799 rapl_probe_amd(family, model);
4802 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
4811 case INTEL_FAM6_HASWELL: /* HSW */
4812 case INTEL_FAM6_HASWELL_L: /* HSW */
4813 case INTEL_FAM6_HASWELL_G: /* HSW */
4814 do_gfx_perf_limit_reasons = 1;
4816 case INTEL_FAM6_HASWELL_X: /* HSX */
4817 do_core_perf_limit_reasons = 1;
4818 do_ring_perf_limit_reasons = 1;
4824 void automatic_cstate_conversion_probe(unsigned int family, unsigned int model)
4830 case INTEL_FAM6_BROADWELL_X:
4831 case INTEL_FAM6_SKYLAKE_X:
4832 has_automatic_cstate_conversion = 1;
4836 void prewake_cstate_probe(unsigned int family, unsigned int model)
4838 if (is_icx(family, model) || is_spr(family, model))
4839 dis_cstate_prewake = 1;
4842 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4844 unsigned long long msr;
4845 unsigned int dts, dts2;
4851 if (!(do_dts || do_ptm))
4856 /* DTS is per-core, no need to print for each thread */
4857 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
4860 if (cpu_migrate(cpu)) {
4861 fprintf(outf, "print_thermal: Could not migrate to CPU %d\n", cpu);
4865 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
4866 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
4869 dts = (msr >> 16) & 0x7F;
4870 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", cpu, msr, tj_max - dts);
4872 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
4875 dts = (msr >> 16) & 0x7F;
4876 dts2 = (msr >> 8) & 0x7F;
4877 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4878 cpu, msr, tj_max - dts, tj_max - dts2);
4881 if (do_dts && debug) {
4882 unsigned int resolution;
4884 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
4887 dts = (msr >> 16) & 0x7F;
4888 resolution = (msr >> 27) & 0xF;
4889 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
4890 cpu, msr, tj_max - dts, resolution);
4892 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
4895 dts = (msr >> 16) & 0x7F;
4896 dts2 = (msr >> 8) & 0x7F;
4897 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
4898 cpu, msr, tj_max - dts, tj_max - dts2);
4904 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
4906 fprintf(outf, "cpu%d: %s: %sabled (%0.3f Watts, %f sec, clamp %sabled)\n",
4908 ((msr >> 15) & 1) ? "EN" : "DIS",
4909 ((msr >> 0) & 0x7FFF) * rapl_power_units,
4910 (1.0 + (((msr >> 22) & 0x3) / 4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
4911 (((msr >> 16) & 1) ? "EN" : "DIS"));
4916 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
4918 unsigned long long msr;
4919 const char *msr_name;
4928 /* RAPL counters are per package, so print only for 1st thread/package */
4929 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
4933 if (cpu_migrate(cpu)) {
4934 fprintf(outf, "print_rapl: Could not migrate to CPU %d\n", cpu);
4938 if (do_rapl & RAPL_AMD_F17H) {
4939 msr_name = "MSR_RAPL_PWR_UNIT";
4940 if (get_msr(cpu, MSR_RAPL_PWR_UNIT, &msr))
4943 msr_name = "MSR_RAPL_POWER_UNIT";
4944 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
4948 fprintf(outf, "cpu%d: %s: 0x%08llx (%f Watts, %f Joules, %f sec.)\n", cpu, msr_name, msr,
4949 rapl_power_units, rapl_energy_units, rapl_time_units);
4951 if (do_rapl & RAPL_PKG_POWER_INFO) {
4953 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
4956 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4958 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4959 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4960 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4961 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4964 if (do_rapl & RAPL_PKG) {
4966 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
4969 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
4970 cpu, msr, (msr >> 63) & 1 ? "" : "UN");
4972 print_power_limit_msr(cpu, msr, "PKG Limit #1");
4973 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%0.3f Watts, %f* sec, clamp %sabled)\n",
4975 ((msr >> 47) & 1) ? "EN" : "DIS",
4976 ((msr >> 32) & 0x7FFF) * rapl_power_units,
4977 (1.0 + (((msr >> 54) & 0x3) / 4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
4978 ((msr >> 48) & 1) ? "EN" : "DIS");
4980 if (get_msr(cpu, MSR_VR_CURRENT_CONFIG, &msr))
4983 fprintf(outf, "cpu%d: MSR_VR_CURRENT_CONFIG: 0x%08llx\n", cpu, msr);
4984 fprintf(outf, "cpu%d: PKG Limit #4: %f Watts (%slocked)\n",
4985 cpu, ((msr >> 0) & 0x1FFF) * rapl_power_units, (msr >> 31) & 1 ? "" : "UN");
4988 if (do_rapl & RAPL_DRAM_POWER_INFO) {
4989 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
4992 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
4994 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4995 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4996 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
4997 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
4999 if (do_rapl & RAPL_DRAM) {
5000 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
5002 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
5003 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5005 print_power_limit_msr(cpu, msr, "DRAM Limit");
5007 if (do_rapl & RAPL_CORE_POLICY) {
5008 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
5011 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
5013 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
5014 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
5016 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
5017 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5018 print_power_limit_msr(cpu, msr, "Cores Limit");
5020 if (do_rapl & RAPL_GFX) {
5021 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
5024 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
5026 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
5028 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
5029 cpu, msr, (msr >> 31) & 1 ? "" : "UN");
5030 print_power_limit_msr(cpu, msr, "GFX Limit");
5036 * SNB adds support for additional MSRs:
5038 * MSR_PKG_C7_RESIDENCY 0x000003fa
5039 * MSR_CORE_C7_RESIDENCY 0x000003fe
5040 * MSR_PKG_C2_RESIDENCY 0x0000060d
5043 int has_snb_msrs(unsigned int family, unsigned int model)
5052 case INTEL_FAM6_SANDYBRIDGE:
5053 case INTEL_FAM6_SANDYBRIDGE_X:
5054 case INTEL_FAM6_IVYBRIDGE: /* IVB */
5055 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
5056 case INTEL_FAM6_HASWELL: /* HSW */
5057 case INTEL_FAM6_HASWELL_X: /* HSW */
5058 case INTEL_FAM6_HASWELL_L: /* HSW */
5059 case INTEL_FAM6_HASWELL_G: /* HSW */
5060 case INTEL_FAM6_BROADWELL: /* BDW */
5061 case INTEL_FAM6_BROADWELL_G: /* BDW */
5062 case INTEL_FAM6_BROADWELL_X: /* BDX */
5063 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5064 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5065 case INTEL_FAM6_SKYLAKE_X: /* SKX */
5066 case INTEL_FAM6_ICELAKE_X: /* ICX */
5067 case INTEL_FAM6_SAPPHIRERAPIDS_X: /* SPR */
5068 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5069 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5070 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
5071 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5072 case INTEL_FAM6_ATOM_TREMONT_D: /* JVL */
5079 * HSW ULT added support for C8/C9/C10 MSRs:
5081 * MSR_PKG_C8_RESIDENCY 0x00000630
5082 * MSR_PKG_C9_RESIDENCY 0x00000631
5083 * MSR_PKG_C10_RESIDENCY 0x00000632
5085 * MSR_PKGC8_IRTL 0x00000633
5086 * MSR_PKGC9_IRTL 0x00000634
5087 * MSR_PKGC10_IRTL 0x00000635
5090 int has_c8910_msrs(unsigned int family, unsigned int model)
5099 case INTEL_FAM6_HASWELL_L: /* HSW */
5100 case INTEL_FAM6_BROADWELL: /* BDW */
5101 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5102 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5103 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5104 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5105 case INTEL_FAM6_ATOM_TREMONT: /* EHL */
5112 * SKL adds support for additional MSRS:
5114 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
5115 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
5116 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
5117 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
5119 int has_skl_msrs(unsigned int family, unsigned int model)
5128 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5129 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5135 int is_slm(unsigned int family, unsigned int model)
5144 case INTEL_FAM6_ATOM_SILVERMONT: /* BYT */
5145 case INTEL_FAM6_ATOM_SILVERMONT_D: /* AVN */
5151 int is_knl(unsigned int family, unsigned int model)
5160 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
5166 int is_cnl(unsigned int family, unsigned int model)
5175 case INTEL_FAM6_CANNONLAKE_L: /* CNL */
5182 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
5184 if (is_knl(family, model))
5189 #define SLM_BCLK_FREQS 5
5190 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0 };
5192 double slm_bclk(void)
5194 unsigned long long msr = 3;
5198 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
5199 fprintf(outf, "SLM BCLK: unknown\n");
5202 if (i >= SLM_BCLK_FREQS) {
5203 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
5206 freq = slm_freq_table[i];
5209 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
5214 double discover_bclk(unsigned int family, unsigned int model)
5216 if (has_snb_msrs(family, model) || is_knl(family, model))
5218 else if (is_slm(family, model))
5224 int get_cpu_type(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5226 unsigned int eax, ebx, ecx, edx;
5234 if (cpu_migrate(t->cpu_id)) {
5235 fprintf(outf, "Could not migrate to CPU %d\n", t->cpu_id);
5239 if (max_level < 0x1a)
5242 __cpuid(0x1a, eax, ebx, ecx, edx);
5243 eax = (eax >> 24) & 0xFF;
5250 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
5251 * the Thermal Control Circuit (TCC) activates.
5252 * This is usually equal to tjMax.
5254 * Older processors do not have this MSR, so there we guess,
5255 * but also allow cmdline over-ride with -T.
5257 * Several MSR temperature values are in units of degrees-C
5258 * below this value, including the Digital Thermal Sensor (DTS),
5259 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
5261 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
5263 unsigned long long msr;
5264 unsigned int tcc_default, tcc_offset;
5270 /* tj_max is used only for dts or ptm */
5271 if (!(do_dts || do_ptm))
5274 /* this is a per-package concept */
5275 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
5279 if (cpu_migrate(cpu)) {
5280 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
5284 if (tj_max_override != 0) {
5285 tj_max = tj_max_override;
5286 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", cpu, tj_max);
5290 /* Temperature Target MSR is Nehalem and newer only */
5291 if (!do_nhm_platform_info)
5294 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
5297 tcc_default = (msr >> 16) & 0xFF;
5300 switch (tcc_offset_bits) {
5302 tcc_offset = (msr >> 24) & 0xF;
5303 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5304 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5307 tcc_offset = (msr >> 24) & 0x3F;
5308 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C) (%d default - %d offset)\n",
5309 cpu, msr, tcc_default - tcc_offset, tcc_default, tcc_offset);
5312 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", cpu, msr, tcc_default);
5320 tj_max = tcc_default;
5325 tj_max = TJMAX_DEFAULT;
5326 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", cpu, tj_max);
5331 void decode_feature_control_msr(void)
5333 unsigned long long msr;
5335 if (!get_msr(base_cpu, MSR_IA32_FEAT_CTL, &msr))
5336 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
5337 base_cpu, msr, msr & FEAT_CTL_LOCKED ? "" : "UN-", msr & (1 << 18) ? "SGX" : "");
5340 void decode_misc_enable_msr(void)
5342 unsigned long long msr;
5347 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
5348 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%sTCC %sEIST %sMWAIT %sPREFETCH %sTURBO)\n",
5350 msr & MSR_IA32_MISC_ENABLE_TM1 ? "" : "No-",
5351 msr & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP ? "" : "No-",
5352 msr & MSR_IA32_MISC_ENABLE_MWAIT ? "" : "No-",
5353 msr & MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE ? "No-" : "",
5354 msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ? "No-" : "");
5357 void decode_misc_feature_control(void)
5359 unsigned long long msr;
5361 if (!has_misc_feature_control)
5364 if (!get_msr(base_cpu, MSR_MISC_FEATURE_CONTROL, &msr))
5366 "cpu%d: MSR_MISC_FEATURE_CONTROL: 0x%08llx (%sL2-Prefetch %sL2-Prefetch-pair %sL1-Prefetch %sL1-IP-Prefetch)\n",
5367 base_cpu, msr, msr & (0 << 0) ? "No-" : "", msr & (1 << 0) ? "No-" : "",
5368 msr & (2 << 0) ? "No-" : "", msr & (3 << 0) ? "No-" : "");
5372 * Decode MSR_MISC_PWR_MGMT
5374 * Decode the bits according to the Nehalem documentation
5375 * bit[0] seems to continue to have same meaning going forward
5378 void decode_misc_pwr_mgmt_msr(void)
5380 unsigned long long msr;
5382 if (!do_nhm_platform_info)
5385 if (no_MSR_MISC_PWR_MGMT)
5388 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
5389 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
5391 msr & (1 << 0) ? "DIS" : "EN", msr & (1 << 1) ? "EN" : "DIS", msr & (1 << 8) ? "EN" : "DIS");
5395 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
5397 * This MSRs are present on Silvermont processors,
5398 * Intel Atom processor E3000 series (Baytrail), and friends.
5400 void decode_c6_demotion_policy_msr(void)
5402 unsigned long long msr;
5404 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
5405 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
5406 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5408 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
5409 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
5410 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
5414 * When models are the same, for the purpose of turbostat, reuse
5416 unsigned int intel_model_duplicates(unsigned int model)
5420 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
5421 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
5422 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
5423 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
5424 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
5425 return INTEL_FAM6_NEHALEM;
5427 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
5428 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
5429 return INTEL_FAM6_NEHALEM_EX;
5431 case INTEL_FAM6_XEON_PHI_KNM:
5432 return INTEL_FAM6_XEON_PHI_KNL;
5434 case INTEL_FAM6_BROADWELL_X:
5435 case INTEL_FAM6_BROADWELL_D: /* BDX-DE */
5436 return INTEL_FAM6_BROADWELL_X;
5438 case INTEL_FAM6_SKYLAKE_L:
5439 case INTEL_FAM6_SKYLAKE:
5440 case INTEL_FAM6_KABYLAKE_L:
5441 case INTEL_FAM6_KABYLAKE:
5442 case INTEL_FAM6_COMETLAKE_L:
5443 case INTEL_FAM6_COMETLAKE:
5444 return INTEL_FAM6_SKYLAKE_L;
5446 case INTEL_FAM6_ICELAKE_L:
5447 case INTEL_FAM6_ICELAKE_NNPI:
5448 case INTEL_FAM6_TIGERLAKE_L:
5449 case INTEL_FAM6_TIGERLAKE:
5450 case INTEL_FAM6_ROCKETLAKE:
5451 case INTEL_FAM6_LAKEFIELD:
5452 case INTEL_FAM6_ALDERLAKE:
5453 case INTEL_FAM6_ALDERLAKE_L:
5454 case INTEL_FAM6_ATOM_GRACEMONT:
5455 case INTEL_FAM6_RAPTORLAKE:
5456 case INTEL_FAM6_RAPTORLAKE_P:
5457 case INTEL_FAM6_RAPTORLAKE_S:
5458 case INTEL_FAM6_METEORLAKE:
5459 case INTEL_FAM6_METEORLAKE_L:
5460 return INTEL_FAM6_CANNONLAKE_L;
5462 case INTEL_FAM6_ATOM_TREMONT_L:
5463 return INTEL_FAM6_ATOM_TREMONT;
5465 case INTEL_FAM6_ICELAKE_D:
5466 return INTEL_FAM6_ICELAKE_X;
5468 case INTEL_FAM6_EMERALDRAPIDS_X:
5469 return INTEL_FAM6_SAPPHIRERAPIDS_X;
5474 void print_dev_latency(void)
5476 char *path = "/dev/cpu_dma_latency";
5481 fd = open(path, O_RDONLY);
5483 warnx("capget(CAP_SYS_ADMIN) failed, try \"# setcap cap_sys_admin=ep %s\"", progname);
5487 retval = read(fd, (void *)&value, sizeof(int));
5488 if (retval != sizeof(int)) {
5489 warn("read failed %s", path);
5493 fprintf(outf, "/dev/cpu_dma_latency: %d usec (%s)\n", value, value == 2000000000 ? "default" : "constrained");
5499 * Linux-perf manages the HW instructions-retired counter
5500 * by enabling when requested, and hiding rollover
5502 void linux_perf_init(void)
5504 if (!BIC_IS_ENABLED(BIC_IPC))
5507 if (access("/proc/sys/kernel/perf_event_paranoid", F_OK))
5510 fd_instr_count_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
5511 if (fd_instr_count_percpu == NULL)
5512 err(-1, "calloc fd_instr_count_percpu");
5514 BIC_PRESENT(BIC_IPC);
5517 void process_cpuid()
5519 unsigned int eax, ebx, ecx, edx;
5520 unsigned int fms, family, model, stepping, ecx_flags, edx_flags;
5521 unsigned long long ucode_patch = 0;
5523 eax = ebx = ecx = edx = 0;
5525 __cpuid(0, max_level, ebx, ecx, edx);
5527 if (ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69)
5529 else if (ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65)
5531 else if (ebx == 0x6f677948 && ecx == 0x656e6975 && edx == 0x6e65476e)
5535 fprintf(outf, "CPUID(0): %.4s%.4s%.4s 0x%x CPUID levels\n",
5536 (char *)&ebx, (char *)&edx, (char *)&ecx, max_level);
5538 __cpuid(1, fms, ebx, ecx, edx);
5539 family = (fms >> 8) & 0xf;
5540 model = (fms >> 4) & 0xf;
5541 stepping = fms & 0xf;
5543 family += (fms >> 20) & 0xff;
5545 model += ((fms >> 16) & 0xf) << 4;
5549 if (get_msr(sched_getcpu(), MSR_IA32_UCODE_REV, &ucode_patch))
5550 warnx("get_msr(UCODE)");
5553 * check max extended function levels of CPUID.
5554 * This is needed to check for invariant TSC.
5555 * This check is valid for both Intel and AMD.
5557 ebx = ecx = edx = 0;
5558 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
5561 fprintf(outf, "CPUID(1): family:model:stepping 0x%x:%x:%x (%d:%d:%d) microcode 0x%x\n",
5562 family, model, stepping, family, model, stepping,
5563 (unsigned int)((ucode_patch >> 32) & 0xFFFFFFFF));
5564 fprintf(outf, "CPUID(0x80000000): max_extended_levels: 0x%x\n", max_extended_level);
5565 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s %s\n",
5566 ecx_flags & (1 << 0) ? "SSE3" : "-",
5567 ecx_flags & (1 << 3) ? "MONITOR" : "-",
5568 ecx_flags & (1 << 6) ? "SMX" : "-",
5569 ecx_flags & (1 << 7) ? "EIST" : "-",
5570 ecx_flags & (1 << 8) ? "TM2" : "-",
5571 edx_flags & (1 << 4) ? "TSC" : "-",
5572 edx_flags & (1 << 5) ? "MSR" : "-",
5573 edx_flags & (1 << 22) ? "ACPI-TM" : "-",
5574 edx_flags & (1 << 28) ? "HT" : "-", edx_flags & (1 << 29) ? "TM" : "-");
5576 if (genuine_intel) {
5578 model = intel_model_duplicates(model);
5581 if (!(edx_flags & (1 << 5)))
5582 errx(1, "CPUID: no MSR");
5584 if (max_extended_level >= 0x80000007) {
5587 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
5588 * this check is valid for both Intel and AMD
5590 __cpuid(0x80000007, eax, ebx, ecx, edx);
5591 has_invariant_tsc = edx & (1 << 8);
5595 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
5596 * this check is valid for both Intel and AMD
5599 __cpuid(0x6, eax, ebx, ecx, edx);
5600 has_aperf = ecx & (1 << 0);
5602 BIC_PRESENT(BIC_Avg_MHz);
5603 BIC_PRESENT(BIC_Busy);
5604 BIC_PRESENT(BIC_Bzy_MHz);
5606 do_dts = eax & (1 << 0);
5608 BIC_PRESENT(BIC_CoreTmp);
5609 has_turbo = eax & (1 << 1);
5610 do_ptm = eax & (1 << 6);
5612 BIC_PRESENT(BIC_PkgTmp);
5613 has_hwp = eax & (1 << 7);
5614 has_hwp_notify = eax & (1 << 8);
5615 has_hwp_activity_window = eax & (1 << 9);
5616 has_hwp_epp = eax & (1 << 10);
5617 has_hwp_pkg = eax & (1 << 11);
5618 has_epb = ecx & (1 << 3);
5621 fprintf(outf, "CPUID(6): %sAPERF, %sTURBO, %sDTS, %sPTM, %sHWP, "
5622 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
5623 has_aperf ? "" : "No-",
5624 has_turbo ? "" : "No-",
5625 do_dts ? "" : "No-",
5626 do_ptm ? "" : "No-",
5627 has_hwp ? "" : "No-",
5628 has_hwp_notify ? "" : "No-",
5629 has_hwp_activity_window ? "" : "No-",
5630 has_hwp_epp ? "" : "No-", has_hwp_pkg ? "" : "No-", has_epb ? "" : "No-");
5633 decode_misc_enable_msr();
5635 if (max_level >= 0x7 && !quiet) {
5640 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
5642 has_sgx = ebx & (1 << 2);
5644 is_hybrid = edx & (1 << 15);
5646 fprintf(outf, "CPUID(7): %sSGX %sHybrid\n", has_sgx ? "" : "No-", is_hybrid ? "" : "No-");
5649 decode_feature_control_msr();
5652 if (max_level >= 0x15) {
5653 unsigned int eax_crystal;
5654 unsigned int ebx_tsc;
5657 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
5659 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
5660 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
5664 if (!quiet && (ebx != 0))
5665 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
5666 eax_crystal, ebx_tsc, crystal_hz);
5668 if (crystal_hz == 0)
5670 case INTEL_FAM6_SKYLAKE_L: /* SKL */
5671 crystal_hz = 24000000; /* 24.0 MHz */
5673 case INTEL_FAM6_ATOM_GOLDMONT_D: /* DNV */
5674 crystal_hz = 25000000; /* 25.0 MHz */
5676 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
5677 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
5678 crystal_hz = 19200000; /* 19.2 MHz */
5685 tsc_hz = (unsigned long long)crystal_hz *ebx_tsc / eax_crystal;
5687 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
5688 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
5692 if (max_level >= 0x16) {
5693 unsigned int base_mhz, max_mhz, bus_mhz, edx;
5696 * CPUID 16H Base MHz, Max MHz, Bus MHz
5698 base_mhz = max_mhz = bus_mhz = edx = 0;
5700 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
5702 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
5703 base_mhz, max_mhz, bus_mhz);
5707 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
5709 BIC_PRESENT(BIC_IRQ);
5710 BIC_PRESENT(BIC_TSC_MHz);
5712 if (probe_nhm_msrs(family, model)) {
5713 do_nhm_platform_info = 1;
5714 BIC_PRESENT(BIC_CPU_c1);
5715 BIC_PRESENT(BIC_CPU_c3);
5716 BIC_PRESENT(BIC_CPU_c6);
5717 BIC_PRESENT(BIC_SMI);
5719 do_snb_cstates = has_snb_msrs(family, model);
5722 BIC_PRESENT(BIC_CPU_c7);
5724 do_irtl_snb = has_snb_msrs(family, model);
5725 if (do_snb_cstates && (pkg_cstate_limit >= PCL__2))
5726 BIC_PRESENT(BIC_Pkgpc2);
5727 if (pkg_cstate_limit >= PCL__3)
5728 BIC_PRESENT(BIC_Pkgpc3);
5729 if (pkg_cstate_limit >= PCL__6)
5730 BIC_PRESENT(BIC_Pkgpc6);
5731 if (do_snb_cstates && (pkg_cstate_limit >= PCL__7))
5732 BIC_PRESENT(BIC_Pkgpc7);
5733 if (has_slv_msrs(family, model)) {
5734 BIC_NOT_PRESENT(BIC_Pkgpc2);
5735 BIC_NOT_PRESENT(BIC_Pkgpc3);
5736 BIC_PRESENT(BIC_Pkgpc6);
5737 BIC_NOT_PRESENT(BIC_Pkgpc7);
5738 BIC_PRESENT(BIC_Mod_c6);
5739 use_c1_residency_msr = 1;
5741 if (is_jvl(family, model)) {
5742 BIC_NOT_PRESENT(BIC_CPU_c3);
5743 BIC_NOT_PRESENT(BIC_CPU_c7);
5744 BIC_NOT_PRESENT(BIC_Pkgpc2);
5745 BIC_NOT_PRESENT(BIC_Pkgpc3);
5746 BIC_NOT_PRESENT(BIC_Pkgpc6);
5747 BIC_NOT_PRESENT(BIC_Pkgpc7);
5749 if (is_dnv(family, model)) {
5750 BIC_PRESENT(BIC_CPU_c1);
5751 BIC_NOT_PRESENT(BIC_CPU_c3);
5752 BIC_NOT_PRESENT(BIC_Pkgpc3);
5753 BIC_NOT_PRESENT(BIC_CPU_c7);
5754 BIC_NOT_PRESENT(BIC_Pkgpc7);
5755 use_c1_residency_msr = 1;
5757 if (is_skx(family, model) || is_icx(family, model) || is_spr(family, model)) {
5758 BIC_NOT_PRESENT(BIC_CPU_c3);
5759 BIC_NOT_PRESENT(BIC_Pkgpc3);
5760 BIC_NOT_PRESENT(BIC_CPU_c7);
5761 BIC_NOT_PRESENT(BIC_Pkgpc7);
5763 if (is_bdx(family, model)) {
5764 BIC_NOT_PRESENT(BIC_CPU_c7);
5765 BIC_NOT_PRESENT(BIC_Pkgpc7);
5767 if (has_c8910_msrs(family, model)) {
5768 if (pkg_cstate_limit >= PCL__8)
5769 BIC_PRESENT(BIC_Pkgpc8);
5770 if (pkg_cstate_limit >= PCL__9)
5771 BIC_PRESENT(BIC_Pkgpc9);
5772 if (pkg_cstate_limit >= PCL_10)
5773 BIC_PRESENT(BIC_Pkgpc10);
5775 do_irtl_hsw = has_c8910_msrs(family, model);
5776 if (has_skl_msrs(family, model)) {
5777 BIC_PRESENT(BIC_Totl_c0);
5778 BIC_PRESENT(BIC_Any_c0);
5779 BIC_PRESENT(BIC_GFX_c0);
5780 BIC_PRESENT(BIC_CPUGFX);
5782 do_slm_cstates = is_slm(family, model);
5783 do_knl_cstates = is_knl(family, model);
5785 if (do_slm_cstates || do_knl_cstates || is_cnl(family, model) || is_ehl(family, model))
5786 BIC_NOT_PRESENT(BIC_CPU_c3);
5789 decode_misc_pwr_mgmt_msr();
5791 if (!quiet && has_slv_msrs(family, model))
5792 decode_c6_demotion_policy_msr();
5794 rapl_probe(family, model);
5795 perf_limit_reasons_probe(family, model);
5796 automatic_cstate_conversion_probe(family, model);
5798 check_tcc_offset(model_orig);
5801 dump_cstate_pstate_config_info(family, model);
5802 intel_uncore_frequency_probe();
5805 print_dev_latency();
5807 dump_sysfs_cstate_config();
5809 dump_sysfs_pstate_config();
5811 if (has_skl_msrs(family, model) || is_ehl(family, model))
5812 calculate_tsc_tweak();
5814 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
5815 BIC_PRESENT(BIC_GFX_rc6);
5817 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
5818 BIC_PRESENT(BIC_GFXMHz);
5820 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_act_freq_mhz", R_OK))
5821 BIC_PRESENT(BIC_GFXACTMHz);
5823 if (!access("/sys/devices/system/cpu/cpuidle/low_power_idle_cpu_residency_us", R_OK))
5824 BIC_PRESENT(BIC_CPU_LPI);
5826 BIC_NOT_PRESENT(BIC_CPU_LPI);
5828 if (!access("/sys/devices/system/cpu/cpu0/thermal_throttle/core_throttle_count", R_OK))
5829 BIC_PRESENT(BIC_CORE_THROT_CNT);
5831 BIC_NOT_PRESENT(BIC_CORE_THROT_CNT);
5833 if (!access(sys_lpi_file_sysfs, R_OK)) {
5834 sys_lpi_file = sys_lpi_file_sysfs;
5835 BIC_PRESENT(BIC_SYS_LPI);
5836 } else if (!access(sys_lpi_file_debugfs, R_OK)) {
5837 sys_lpi_file = sys_lpi_file_debugfs;
5838 BIC_PRESENT(BIC_SYS_LPI);
5840 sys_lpi_file_sysfs = NULL;
5841 BIC_NOT_PRESENT(BIC_SYS_LPI);
5845 decode_misc_feature_control();
5851 * in /dev/cpu/ return success for names that are numbers
5852 * ie. filter out ".", "..", "microcode".
5854 int dir_filter(const struct dirent *dirp)
5856 if (isdigit(dirp->d_name[0]))
5862 void topology_probe()
5865 int max_core_id = 0;
5866 int max_package_id = 0;
5868 int max_siblings = 0;
5870 /* Initialize num_cpus, max_cpu_num */
5873 for_all_proc_cpus(count_cpus);
5874 if (!summary_only && topo.num_cpus > 1)
5875 BIC_PRESENT(BIC_CPU);
5878 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
5880 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
5882 err(1, "calloc cpus");
5885 * Allocate and initialize cpu_present_set
5887 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
5888 if (cpu_present_set == NULL)
5889 err(3, "CPU_ALLOC");
5890 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5891 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
5892 for_all_proc_cpus(mark_cpu_present);
5895 * Validate that all cpus in cpu_subset are also in cpu_present_set
5897 for (i = 0; i < CPU_SUBSET_MAXCPUS; ++i) {
5898 if (CPU_ISSET_S(i, cpu_subset_size, cpu_subset))
5899 if (!CPU_ISSET_S(i, cpu_present_setsize, cpu_present_set))
5900 err(1, "cpu%d not present", i);
5904 * Allocate and initialize cpu_affinity_set
5906 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
5907 if (cpu_affinity_set == NULL)
5908 err(3, "CPU_ALLOC");
5909 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
5910 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
5912 for_all_proc_cpus(init_thread_id);
5916 * find max_core_id, max_package_id
5918 for (i = 0; i <= topo.max_cpu_num; ++i) {
5921 if (cpu_is_not_present(i)) {
5923 fprintf(outf, "cpu%d NOT PRESENT\n", i);
5927 cpus[i].logical_cpu_id = i;
5929 /* get package information */
5930 cpus[i].physical_package_id = get_physical_package_id(i);
5931 if (cpus[i].physical_package_id > max_package_id)
5932 max_package_id = cpus[i].physical_package_id;
5934 /* get die information */
5935 cpus[i].die_id = get_die_id(i);
5936 if (cpus[i].die_id > max_die_id)
5937 max_die_id = cpus[i].die_id;
5939 /* get numa node information */
5940 cpus[i].physical_node_id = get_physical_node_id(&cpus[i]);
5941 if (cpus[i].physical_node_id > topo.max_node_num)
5942 topo.max_node_num = cpus[i].physical_node_id;
5944 /* get core information */
5945 cpus[i].physical_core_id = get_core_id(i);
5946 if (cpus[i].physical_core_id > max_core_id)
5947 max_core_id = cpus[i].physical_core_id;
5949 /* get thread information */
5950 siblings = get_thread_siblings(&cpus[i]);
5951 if (siblings > max_siblings)
5952 max_siblings = siblings;
5953 if (cpus[i].thread_id == 0)
5957 topo.cores_per_node = max_core_id + 1;
5959 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", max_core_id, topo.cores_per_node);
5960 if (!summary_only && topo.cores_per_node > 1)
5961 BIC_PRESENT(BIC_Core);
5963 topo.num_die = max_die_id + 1;
5965 fprintf(outf, "max_die_id %d, sizing for %d die\n", max_die_id, topo.num_die);
5966 if (!summary_only && topo.num_die > 1)
5967 BIC_PRESENT(BIC_Die);
5969 topo.num_packages = max_package_id + 1;
5971 fprintf(outf, "max_package_id %d, sizing for %d packages\n", max_package_id, topo.num_packages);
5972 if (!summary_only && topo.num_packages > 1)
5973 BIC_PRESENT(BIC_Package);
5977 fprintf(outf, "nodes_per_pkg %d\n", topo.nodes_per_pkg);
5978 if (!summary_only && topo.nodes_per_pkg > 1)
5979 BIC_PRESENT(BIC_Node);
5981 topo.threads_per_core = max_siblings;
5983 fprintf(outf, "max_siblings %d\n", max_siblings);
5988 for (i = 0; i <= topo.max_cpu_num; ++i) {
5989 if (cpu_is_not_present(i))
5992 "cpu %d pkg %d die %d node %d lnode %d core %d thread %d\n",
5993 i, cpus[i].physical_package_id, cpus[i].die_id,
5994 cpus[i].physical_node_id, cpus[i].logical_node_id, cpus[i].physical_core_id, cpus[i].thread_id);
5999 void allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
6002 int num_cores = topo.cores_per_node * topo.nodes_per_pkg * topo.num_packages;
6003 int num_threads = topo.threads_per_core * num_cores;
6005 *t = calloc(num_threads, sizeof(struct thread_data));
6009 for (i = 0; i < num_threads; i++)
6010 (*t)[i].cpu_id = -1;
6012 *c = calloc(num_cores, sizeof(struct core_data));
6016 for (i = 0; i < num_cores; i++)
6017 (*c)[i].core_id = -1;
6019 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
6023 for (i = 0; i < topo.num_packages; i++)
6024 (*p)[i].package_id = i;
6028 err(1, "calloc counters");
6034 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
6036 void init_counter(struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base, int cpu_id)
6038 int pkg_id = cpus[cpu_id].physical_package_id;
6039 int node_id = cpus[cpu_id].logical_node_id;
6040 int core_id = cpus[cpu_id].physical_core_id;
6041 int thread_id = cpus[cpu_id].thread_id;
6042 struct thread_data *t;
6043 struct core_data *c;
6046 /* Workaround for systems where physical_node_id==-1
6047 * and logical_node_id==(-1 - topo.num_cpus)
6052 t = GET_THREAD(thread_base, thread_id, core_id, node_id, pkg_id);
6053 c = GET_CORE(core_base, core_id, node_id, pkg_id);
6054 p = GET_PKG(pkg_base, pkg_id);
6057 if (thread_id == 0) {
6058 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
6059 if (cpu_is_first_core_in_package(cpu_id))
6060 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
6063 c->core_id = core_id;
6064 p->package_id = pkg_id;
6067 int initialize_counters(int cpu_id)
6069 init_counter(EVEN_COUNTERS, cpu_id);
6070 init_counter(ODD_COUNTERS, cpu_id);
6074 void allocate_output_buffer()
6076 output_buffer = calloc(1, (1 + topo.num_cpus) * 2048);
6077 outp = output_buffer;
6079 err(-1, "calloc output buffer");
6082 void allocate_fd_percpu(void)
6084 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6085 if (fd_percpu == NULL)
6086 err(-1, "calloc fd_percpu");
6089 void allocate_irq_buffers(void)
6091 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
6092 if (irq_column_2_cpu == NULL)
6093 err(-1, "calloc %d", topo.num_cpus);
6095 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
6096 if (irqs_per_cpu == NULL)
6097 err(-1, "calloc %d", topo.max_cpu_num + 1);
6100 void setup_all_buffers(void)
6103 allocate_irq_buffers();
6104 allocate_fd_percpu();
6105 allocate_counters(&thread_even, &core_even, &package_even);
6106 allocate_counters(&thread_odd, &core_odd, &package_odd);
6107 allocate_output_buffer();
6108 for_all_proc_cpus(initialize_counters);
6111 void set_base_cpu(void)
6113 base_cpu = sched_getcpu();
6115 err(-ENODEV, "No valid cpus found");
6118 fprintf(outf, "base_cpu = %d\n", base_cpu);
6121 void turbostat_init()
6123 setup_all_buffers();
6126 check_permissions();
6131 for_all_cpus(print_hwp, ODD_COUNTERS);
6134 for_all_cpus(print_epb, ODD_COUNTERS);
6137 for_all_cpus(print_perf_limit, ODD_COUNTERS);
6140 for_all_cpus(print_rapl, ODD_COUNTERS);
6142 for_all_cpus(set_temperature_target, ODD_COUNTERS);
6144 for_all_cpus(get_cpu_type, ODD_COUNTERS);
6145 for_all_cpus(get_cpu_type, EVEN_COUNTERS);
6148 for_all_cpus(print_thermal, ODD_COUNTERS);
6150 if (!quiet && do_irtl_snb)
6153 if (DO_BIC(BIC_IPC))
6154 (void)get_instr_count_fd(base_cpu);
6157 int fork_it(char **argv)
6162 snapshot_proc_sysfs_files();
6163 status = for_all_cpus(get_counters, EVEN_COUNTERS);
6164 first_counter_read = 0;
6167 /* clear affinity side-effect of get_counters() */
6168 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
6169 gettimeofday(&tv_even, (struct timezone *)NULL);
6174 execvp(argv[0], argv);
6175 err(errno, "exec %s", argv[0]);
6179 if (child_pid == -1)
6182 signal(SIGINT, SIG_IGN);
6183 signal(SIGQUIT, SIG_IGN);
6184 if (waitpid(child_pid, &status, 0) == -1)
6185 err(status, "waitpid");
6187 if (WIFEXITED(status))
6188 status = WEXITSTATUS(status);
6191 * n.b. fork_it() does not check for errors from for_all_cpus()
6192 * because re-starting is problematic when forking
6194 snapshot_proc_sysfs_files();
6195 for_all_cpus(get_counters, ODD_COUNTERS);
6196 gettimeofday(&tv_odd, (struct timezone *)NULL);
6197 timersub(&tv_odd, &tv_even, &tv_delta);
6198 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
6199 fprintf(outf, "%s: Counter reset detected\n", progname);
6201 compute_average(EVEN_COUNTERS);
6202 format_all_counters(EVEN_COUNTERS);
6205 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec / 1000000.0);
6207 flush_output_stderr();
6212 int get_and_dump_counters(void)
6216 snapshot_proc_sysfs_files();
6217 status = for_all_cpus(get_counters, ODD_COUNTERS);
6221 status = for_all_cpus(dump_counters, ODD_COUNTERS);
6225 flush_output_stdout();
6230 void print_version()
6232 fprintf(outf, "turbostat version 2023.03.17 - Len Brown <lenb@kernel.org>\n");
6235 #define COMMAND_LINE_SIZE 2048
6237 void print_bootcmd(void)
6239 char bootcmd[COMMAND_LINE_SIZE];
6243 memset(bootcmd, 0, COMMAND_LINE_SIZE);
6244 fp = fopen("/proc/cmdline", "r");
6248 ret = fread(bootcmd, sizeof(char), COMMAND_LINE_SIZE - 1, fp);
6250 bootcmd[ret] = '\0';
6251 /* the last character is already '\n' */
6252 fprintf(outf, "Kernel command line: %s", bootcmd);
6258 int add_counter(unsigned int msr_num, char *path, char *name,
6259 unsigned int width, enum counter_scope scope,
6260 enum counter_type type, enum counter_format format, int flags)
6262 struct msr_counter *msrp;
6264 msrp = calloc(1, sizeof(struct msr_counter));
6270 msrp->msr_num = msr_num;
6271 strncpy(msrp->name, name, NAME_BYTES - 1);
6273 strncpy(msrp->path, path, PATH_BYTES - 1);
6274 msrp->width = width;
6276 msrp->format = format;
6277 msrp->flags = flags;
6282 msrp->next = sys.tp;
6284 sys.added_thread_counters++;
6285 if (sys.added_thread_counters > MAX_ADDED_THREAD_COUNTERS) {
6286 fprintf(stderr, "exceeded max %d added thread counters\n", MAX_ADDED_COUNTERS);
6292 msrp->next = sys.cp;
6294 sys.added_core_counters++;
6295 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
6296 fprintf(stderr, "exceeded max %d added core counters\n", MAX_ADDED_COUNTERS);
6302 msrp->next = sys.pp;
6304 sys.added_package_counters++;
6305 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
6306 fprintf(stderr, "exceeded max %d added package counters\n", MAX_ADDED_COUNTERS);
6315 void parse_add_command(char *add_command)
6319 char name_buffer[NAME_BYTES] = "";
6322 enum counter_scope scope = SCOPE_CPU;
6323 enum counter_type type = COUNTER_CYCLES;
6324 enum counter_format format = FORMAT_DELTA;
6326 while (add_command) {
6328 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
6331 if (sscanf(add_command, "msr%d", &msr_num) == 1)
6334 if (*add_command == '/') {
6339 if (sscanf(add_command, "u%d", &width) == 1) {
6340 if ((width == 32) || (width == 64))
6344 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
6348 if (!strncmp(add_command, "core", strlen("core"))) {
6352 if (!strncmp(add_command, "package", strlen("package"))) {
6353 scope = SCOPE_PACKAGE;
6356 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
6357 type = COUNTER_CYCLES;
6360 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
6361 type = COUNTER_SECONDS;
6364 if (!strncmp(add_command, "usec", strlen("usec"))) {
6365 type = COUNTER_USEC;
6368 if (!strncmp(add_command, "raw", strlen("raw"))) {
6369 format = FORMAT_RAW;
6372 if (!strncmp(add_command, "delta", strlen("delta"))) {
6373 format = FORMAT_DELTA;
6376 if (!strncmp(add_command, "percent", strlen("percent"))) {
6377 format = FORMAT_PERCENT;
6381 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
6384 eos = strchr(name_buffer, ',');
6391 add_command = strchr(add_command, ',');
6393 *add_command = '\0';
6398 if ((msr_num == 0) && (path == NULL)) {
6399 fprintf(stderr, "--add: (msrDDD | msr0xXXX | /path_to_counter ) required\n");
6403 /* generate default column header */
6404 if (*name_buffer == '\0') {
6406 sprintf(name_buffer, "M0x%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6408 sprintf(name_buffer, "M0X%x%s", msr_num, format == FORMAT_PERCENT ? "%" : "");
6411 if (add_counter(msr_num, path, name_buffer, width, scope, type, format, 0))
6420 int is_deferred_add(char *name)
6424 for (i = 0; i < deferred_add_index; ++i)
6425 if (!strcmp(name, deferred_add_names[i]))
6430 int is_deferred_skip(char *name)
6434 for (i = 0; i < deferred_skip_index; ++i)
6435 if (!strcmp(name, deferred_skip_names[i]))
6440 void probe_sysfs(void)
6448 for (state = 10; state >= 0; --state) {
6450 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6451 input = fopen(path, "r");
6454 if (!fgets(name_buf, sizeof(name_buf), input))
6455 err(1, "%s: failed to read file", path);
6457 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6458 sp = strchr(name_buf, '-');
6460 sp = strchrnul(name_buf, '\n');
6464 remove_underbar(name_buf);
6468 sprintf(path, "cpuidle/state%d/time", state);
6470 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6473 if (is_deferred_skip(name_buf))
6476 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_USEC, FORMAT_PERCENT, SYSFS_PERCPU);
6479 for (state = 10; state >= 0; --state) {
6481 sprintf(path, "/sys/devices/system/cpu/cpu%d/cpuidle/state%d/name", base_cpu, state);
6482 input = fopen(path, "r");
6485 if (!fgets(name_buf, sizeof(name_buf), input))
6486 err(1, "%s: failed to read file", path);
6487 /* truncate "C1-HSW\n" to "C1", or truncate "C1\n" to "C1" */
6488 sp = strchr(name_buf, '-');
6490 sp = strchrnul(name_buf, '\n');
6494 remove_underbar(name_buf);
6496 sprintf(path, "cpuidle/state%d/usage", state);
6498 if (!DO_BIC(BIC_sysfs) && !is_deferred_add(name_buf))
6501 if (is_deferred_skip(name_buf))
6504 add_counter(0, path, name_buf, 64, SCOPE_CPU, COUNTER_ITEMS, FORMAT_DELTA, SYSFS_PERCPU);
6510 * parse cpuset with following syntax
6511 * 1,2,4..6,8-10 and set bits in cpu_subset
6513 void parse_cpu_command(char *optarg)
6515 unsigned int start, end;
6518 if (!strcmp(optarg, "core")) {
6524 if (!strcmp(optarg, "package")) {
6530 if (show_core_only || show_pkg_only)
6533 cpu_subset = CPU_ALLOC(CPU_SUBSET_MAXCPUS);
6534 if (cpu_subset == NULL)
6535 err(3, "CPU_ALLOC");
6536 cpu_subset_size = CPU_ALLOC_SIZE(CPU_SUBSET_MAXCPUS);
6538 CPU_ZERO_S(cpu_subset_size, cpu_subset);
6542 while (next && *next) {
6544 if (*next == '-') /* no negative cpu numbers */
6547 start = strtoul(next, &next, 10);
6549 if (start >= CPU_SUBSET_MAXCPUS)
6551 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6562 next += 1; /* start range */
6563 } else if (*next == '.') {
6566 next += 1; /* start range */
6571 end = strtoul(next, &next, 10);
6575 while (++start <= end) {
6576 if (start >= CPU_SUBSET_MAXCPUS)
6578 CPU_SET_S(start, cpu_subset_size, cpu_subset);
6583 else if (*next != '\0')
6590 fprintf(stderr, "\"--cpu %s\" malformed\n", optarg);
6595 void cmdline(int argc, char **argv)
6598 int option_index = 0;
6599 static struct option long_options[] = {
6600 { "add", required_argument, 0, 'a' },
6601 { "cpu", required_argument, 0, 'c' },
6602 { "Dump", no_argument, 0, 'D' },
6603 { "debug", no_argument, 0, 'd' }, /* internal, not documented */
6604 { "enable", required_argument, 0, 'e' },
6605 { "interval", required_argument, 0, 'i' },
6606 { "IPC", no_argument, 0, 'I' },
6607 { "num_iterations", required_argument, 0, 'n' },
6608 { "header_iterations", required_argument, 0, 'N' },
6609 { "help", no_argument, 0, 'h' },
6610 { "hide", required_argument, 0, 'H' }, // meh, -h taken by --help
6611 { "Joules", no_argument, 0, 'J' },
6612 { "list", no_argument, 0, 'l' },
6613 { "out", required_argument, 0, 'o' },
6614 { "quiet", no_argument, 0, 'q' },
6615 { "show", required_argument, 0, 's' },
6616 { "Summary", no_argument, 0, 'S' },
6617 { "TCC", required_argument, 0, 'T' },
6618 { "version", no_argument, 0, 'v' },
6624 while ((opt = getopt_long_only(argc, argv, "+C:c:Dde:hi:Jn:o:qST:v", long_options, &option_index)) != -1) {
6627 parse_add_command(optarg);
6630 parse_cpu_command(optarg);
6636 /* --enable specified counter */
6637 bic_enabled = bic_enabled | bic_lookup(optarg, SHOW_LIST);
6641 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6645 * --hide: do not show those specified
6646 * multiple invocations simply clear more bits in enabled mask
6648 bic_enabled &= ~bic_lookup(optarg, HIDE_LIST);
6656 double interval = strtod(optarg, NULL);
6658 if (interval < 0.001) {
6659 fprintf(outf, "interval %f seconds is too small\n", interval);
6663 interval_tv.tv_sec = interval_ts.tv_sec = interval;
6664 interval_tv.tv_usec = (interval - interval_tv.tv_sec) * 1000000;
6665 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
6672 ENABLE_BIC(BIC_DISABLED_BY_DEFAULT);
6677 outf = fopen_or_die(optarg, "w");
6683 num_iterations = strtod(optarg, NULL);
6685 if (num_iterations <= 0) {
6686 fprintf(outf, "iterations %d should be positive number\n", num_iterations);
6691 header_iterations = strtod(optarg, NULL);
6693 if (header_iterations <= 0) {
6694 fprintf(outf, "iterations %d should be positive number\n", header_iterations);
6700 * --show: show only those specified
6701 * The 1st invocation will clear and replace the enabled mask
6702 * subsequent invocations can add to it.
6705 bic_enabled = bic_lookup(optarg, SHOW_LIST);
6707 bic_enabled |= bic_lookup(optarg, SHOW_LIST);
6714 tj_max_override = atoi(optarg);
6724 int main(int argc, char **argv)
6727 cmdline(argc, argv);
6740 /* dump counters and exit */
6742 return get_and_dump_counters();
6744 /* list header and exit */
6745 if (list_header_only) {
6747 flush_output_stdout();
6752 * if any params left, it must be a command to fork
6755 return fork_it(argv + optind);