2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
5 * Copyright (c) 2013 Intel Corporation.
6 * Len Brown <len.brown@intel.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
24 #include INTEL_FAMILY_HEADER
29 #include <sys/types.h>
32 #include <sys/resource.h>
44 #include <linux/capability.h>
47 char *proc_stat = "/proc/stat";
50 struct timespec interval_ts = {5, 0};
52 unsigned int rapl_joules;
53 unsigned int summary_only;
54 unsigned int dump_only;
55 unsigned int do_snb_cstates;
56 unsigned int do_knl_cstates;
61 unsigned int do_c8_c9_c10;
62 unsigned int do_skl_residency;
63 unsigned int do_slm_cstates;
64 unsigned int use_c1_residency_msr;
65 unsigned int has_aperf;
67 unsigned int do_irtl_snb;
68 unsigned int do_irtl_hsw;
69 unsigned int units = 1000000; /* MHz etc */
70 unsigned int genuine_intel;
71 unsigned int has_invariant_tsc;
72 unsigned int do_nhm_platform_info;
73 unsigned int no_MSR_MISC_PWR_MGMT;
74 unsigned int aperf_mperf_multiplier = 1;
77 unsigned int has_base_hz;
78 double tsc_tweak = 1.0;
79 unsigned int show_pkg_only;
80 unsigned int show_core_only;
81 char *output_buffer, *outp;
85 unsigned long long gfx_cur_rc6_ms;
86 unsigned int gfx_cur_mhz;
87 unsigned int tcc_activation_temp;
88 unsigned int tcc_activation_temp_override;
89 double rapl_power_units, rapl_time_units;
90 double rapl_dram_energy_units, rapl_energy_units;
91 double rapl_joule_counter_range;
92 unsigned int do_core_perf_limit_reasons;
93 unsigned int do_gfx_perf_limit_reasons;
94 unsigned int do_ring_perf_limit_reasons;
95 unsigned int crystal_hz;
96 unsigned long long tsc_hz;
98 double discover_bclk(unsigned int family, unsigned int model);
99 unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
100 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
101 unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
102 unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
103 unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
104 unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
106 #define RAPL_PKG (1 << 0)
107 /* 0x610 MSR_PKG_POWER_LIMIT */
108 /* 0x611 MSR_PKG_ENERGY_STATUS */
109 #define RAPL_PKG_PERF_STATUS (1 << 1)
110 /* 0x613 MSR_PKG_PERF_STATUS */
111 #define RAPL_PKG_POWER_INFO (1 << 2)
112 /* 0x614 MSR_PKG_POWER_INFO */
114 #define RAPL_DRAM (1 << 3)
115 /* 0x618 MSR_DRAM_POWER_LIMIT */
116 /* 0x619 MSR_DRAM_ENERGY_STATUS */
117 #define RAPL_DRAM_PERF_STATUS (1 << 4)
118 /* 0x61b MSR_DRAM_PERF_STATUS */
119 #define RAPL_DRAM_POWER_INFO (1 << 5)
120 /* 0x61c MSR_DRAM_POWER_INFO */
122 #define RAPL_CORES_POWER_LIMIT (1 << 6)
123 /* 0x638 MSR_PP0_POWER_LIMIT */
124 #define RAPL_CORE_POLICY (1 << 7)
125 /* 0x63a MSR_PP0_POLICY */
127 #define RAPL_GFX (1 << 8)
128 /* 0x640 MSR_PP1_POWER_LIMIT */
129 /* 0x641 MSR_PP1_ENERGY_STATUS */
130 /* 0x642 MSR_PP1_POLICY */
132 #define RAPL_CORES_ENERGY_STATUS (1 << 9)
133 /* 0x639 MSR_PP0_ENERGY_STATUS */
134 #define RAPL_CORES (RAPL_CORES_ENERGY_STATUS | RAPL_CORES_POWER_LIMIT)
135 #define TJMAX_DEFAULT 100
137 #define MAX(a, b) ((a) > (b) ? (a) : (b))
140 * buffer size used by sscanf() for added column names
141 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
143 #define NAME_BYTES 20
148 cpu_set_t *cpu_present_set, *cpu_affinity_set;
149 size_t cpu_present_setsize, cpu_affinity_setsize;
150 #define MAX_ADDED_COUNTERS 16
153 unsigned long long tsc;
154 unsigned long long aperf;
155 unsigned long long mperf;
156 unsigned long long c1;
157 unsigned int irq_count;
158 unsigned int smi_count;
161 #define CPU_IS_FIRST_THREAD_IN_CORE 0x2
162 #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
163 unsigned long long counter[MAX_ADDED_COUNTERS];
164 } *thread_even, *thread_odd;
167 unsigned long long c3;
168 unsigned long long c6;
169 unsigned long long c7;
170 unsigned int core_temp_c;
171 unsigned int core_id;
172 unsigned long long counter[MAX_ADDED_COUNTERS];
173 } *core_even, *core_odd;
176 unsigned long long pc2;
177 unsigned long long pc3;
178 unsigned long long pc6;
179 unsigned long long pc7;
180 unsigned long long pc8;
181 unsigned long long pc9;
182 unsigned long long pc10;
183 unsigned long long pkg_wtd_core_c0;
184 unsigned long long pkg_any_core_c0;
185 unsigned long long pkg_any_gfxe_c0;
186 unsigned long long pkg_both_core_gfxe_c0;
187 long long gfx_rc6_ms;
188 unsigned int gfx_mhz;
189 unsigned int package_id;
190 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
191 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
192 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
193 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
194 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
195 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
196 unsigned int pkg_temp_c;
197 unsigned long long counter[MAX_ADDED_COUNTERS];
198 } *package_even, *package_odd;
200 #define ODD_COUNTERS thread_odd, core_odd, package_odd
201 #define EVEN_COUNTERS thread_even, core_even, package_even
203 #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
204 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
205 topo.num_threads_per_core + \
206 (core_no) * topo.num_threads_per_core + (thread_no))
207 #define GET_CORE(core_base, core_no, pkg_no) \
208 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
209 #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
211 enum counter_scope {SCOPE_CPU, SCOPE_CORE, SCOPE_PACKAGE};
212 enum counter_type {COUNTER_CYCLES, COUNTER_SECONDS};
213 enum counter_format {FORMAT_RAW, FORMAT_DELTA, FORMAT_PERCENT};
216 unsigned int msr_num;
217 char name[NAME_BYTES];
219 enum counter_type type;
220 enum counter_format format;
221 struct msr_counter *next;
223 #define FLAGS_HIDE (1 << 0)
224 #define FLAGS_SHOW (1 << 1)
227 struct sys_counters {
228 unsigned int added_thread_counters;
229 unsigned int added_core_counters;
230 unsigned int added_package_counters;
231 struct msr_counter *tp;
232 struct msr_counter *cp;
233 struct msr_counter *pp;
236 struct system_summary {
237 struct thread_data threads;
238 struct core_data cores;
239 struct pkg_data packages;
248 int num_cores_per_pkg;
249 int num_threads_per_core;
252 struct timeval tv_even, tv_odd, tv_delta;
254 int *irq_column_2_cpu; /* /proc/interrupts column numbers */
255 int *irqs_per_cpu; /* indexed by cpu_num */
257 void setup_all_buffers(void);
259 int cpu_is_not_present(int cpu)
261 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
264 * run func(thread, core, package) in topology order
265 * skip non-present cpus
268 int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
269 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
271 int retval, pkg_no, core_no, thread_no;
273 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
274 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
275 for (thread_no = 0; thread_no <
276 topo.num_threads_per_core; ++thread_no) {
277 struct thread_data *t;
281 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
283 if (cpu_is_not_present(t->cpu_id))
286 c = GET_CORE(core_base, core_no, pkg_no);
287 p = GET_PKG(pkg_base, pkg_no);
289 retval = func(t, c, p);
298 int cpu_migrate(int cpu)
300 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
301 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
302 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
307 int get_msr_fd(int cpu)
317 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
318 fd = open(pathname, O_RDONLY);
320 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
327 int get_msr(int cpu, off_t offset, unsigned long long *msr)
331 retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset);
333 if (retval != sizeof *msr)
334 err(-1, "cpu%d: msr offset 0x%llx read failed", cpu, (unsigned long long)offset);
340 * Each string in this array is compared in --show and --hide cmdline.
341 * Thus, strings that are proper sub-sets must follow their more specific peers.
343 struct msr_counter bic[] = {
349 { 0x0, "SMI", 32, 0, FORMAT_DELTA, NULL},
380 #define MAX_BIC (sizeof(bic) / sizeof(struct msr_counter))
381 #define BIC_Package (1ULL << 0)
382 #define BIC_Avg_MHz (1ULL << 1)
383 #define BIC_Bzy_MHz (1ULL << 2)
384 #define BIC_TSC_MHz (1ULL << 3)
385 #define BIC_IRQ (1ULL << 4)
386 #define BIC_SMI (1ULL << 5)
387 #define BIC_Busy (1ULL << 6)
388 #define BIC_CPU_c1 (1ULL << 7)
389 #define BIC_CPU_c3 (1ULL << 8)
390 #define BIC_CPU_c6 (1ULL << 9)
391 #define BIC_CPU_c7 (1ULL << 10)
392 #define BIC_ThreadC (1ULL << 11)
393 #define BIC_CoreTmp (1ULL << 12)
394 #define BIC_CoreCnt (1ULL << 13)
395 #define BIC_PkgTmp (1ULL << 14)
396 #define BIC_GFX_rc6 (1ULL << 15)
397 #define BIC_GFXMHz (1ULL << 16)
398 #define BIC_Pkgpc2 (1ULL << 17)
399 #define BIC_Pkgpc3 (1ULL << 18)
400 #define BIC_Pkgpc6 (1ULL << 19)
401 #define BIC_Pkgpc7 (1ULL << 20)
402 #define BIC_PkgWatt (1ULL << 21)
403 #define BIC_CorWatt (1ULL << 22)
404 #define BIC_GFXWatt (1ULL << 23)
405 #define BIC_PkgCnt (1ULL << 24)
406 #define BIC_RAMWatt (1ULL << 27)
407 #define BIC_PKG__ (1ULL << 28)
408 #define BIC_RAM__ (1ULL << 29)
409 #define BIC_Pkg_J (1ULL << 30)
410 #define BIC_Cor_J (1ULL << 31)
411 #define BIC_GFX_J (1ULL << 30)
412 #define BIC_RAM_J (1ULL << 31)
413 #define BIC_Core (1ULL << 32)
414 #define BIC_CPU (1ULL << 33)
416 unsigned long long bic_enabled = 0xFFFFFFFFFFFFFFFFULL;
417 unsigned long long bic_present;
419 #define DO_BIC(COUNTER_NAME) (bic_enabled & bic_present & COUNTER_NAME)
420 #define BIC_PRESENT(COUNTER_BIT) (bic_present |= COUNTER_BIT)
424 * for all the strings in comma separate name_list,
425 * set the approprate bit in return value.
427 unsigned long long bic_lookup(char *name_list)
430 unsigned long long retval = 0;
435 comma = strchr(name_list, ',');
440 for (i = 0; i < MAX_BIC; ++i) {
441 if (!strcmp(name_list, bic[i].name)) {
442 retval |= (1ULL << i);
447 fprintf(stderr, "Invalid counter name: %s\n", name_list);
459 void print_header(void)
461 struct msr_counter *mp;
463 if (DO_BIC(BIC_Package))
464 outp += sprintf(outp, "\tPackage");
465 if (DO_BIC(BIC_Core))
466 outp += sprintf(outp, "\tCore");
468 outp += sprintf(outp, "\tCPU");
469 if (DO_BIC(BIC_Avg_MHz))
470 outp += sprintf(outp, "\tAvg_MHz");
471 if (DO_BIC(BIC_Busy))
472 outp += sprintf(outp, "\tBusy%%");
473 if (DO_BIC(BIC_Bzy_MHz))
474 outp += sprintf(outp, "\tBzy_MHz");
475 if (DO_BIC(BIC_TSC_MHz))
476 outp += sprintf(outp, "\tTSC_MHz");
482 outp += sprintf(outp, "\tIRQ");
484 outp += sprintf(outp, "\tSMI");
486 if (DO_BIC(BIC_CPU_c1))
487 outp += sprintf(outp, "\tCPU%%c1");
489 for (mp = sys.tp; mp; mp = mp->next) {
490 if (mp->format == FORMAT_RAW) {
492 outp += sprintf(outp, "\t%18.18s", mp->name);
494 outp += sprintf(outp, "\t%10.10s", mp->name);
496 outp += sprintf(outp, "\t%-7.7s", mp->name);
500 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
501 outp += sprintf(outp, "\tCPU%%c3");
502 if (DO_BIC(BIC_CPU_c6))
503 outp += sprintf(outp, "\tCPU%%c6");
504 if (DO_BIC(BIC_CPU_c7))
505 outp += sprintf(outp, "\tCPU%%c7");
508 if (DO_BIC(BIC_CoreTmp))
509 outp += sprintf(outp, "\tCoreTmp");
511 for (mp = sys.cp; mp; mp = mp->next) {
512 if (mp->format == FORMAT_RAW) {
514 outp += sprintf(outp, "\t%18.18s", mp->name);
516 outp += sprintf(outp, "\t%10.10s", mp->name);
518 outp += sprintf(outp, "\t%-7.7s", mp->name);
522 if (DO_BIC(BIC_PkgTmp))
523 outp += sprintf(outp, "\tPkgTmp");
525 if (DO_BIC(BIC_GFX_rc6))
526 outp += sprintf(outp, "\tGFX%%rc6");
528 if (DO_BIC(BIC_GFXMHz))
529 outp += sprintf(outp, "\tGFXMHz");
531 if (do_skl_residency) {
532 outp += sprintf(outp, "\tTotl%%C0");
533 outp += sprintf(outp, "\tAny%%C0");
534 outp += sprintf(outp, "\tGFX%%C0");
535 outp += sprintf(outp, "\tCPUGFX%%");
539 outp += sprintf(outp, "\tPkg%%pc2");
541 outp += sprintf(outp, "\tPkg%%pc3");
543 outp += sprintf(outp, "\tPkg%%pc6");
545 outp += sprintf(outp, "\tPkg%%pc7");
547 outp += sprintf(outp, "\tPkg%%pc8");
548 outp += sprintf(outp, "\tPkg%%pc9");
549 outp += sprintf(outp, "\tPk%%pc10");
552 if (do_rapl && !rapl_joules) {
553 if (DO_BIC(BIC_PkgWatt))
554 outp += sprintf(outp, "\tPkgWatt");
555 if (DO_BIC(BIC_CorWatt))
556 outp += sprintf(outp, "\tCorWatt");
557 if (DO_BIC(BIC_GFXWatt))
558 outp += sprintf(outp, "\tGFXWatt");
559 if (DO_BIC(BIC_RAMWatt))
560 outp += sprintf(outp, "\tRAMWatt");
561 if (DO_BIC(BIC_PKG__))
562 outp += sprintf(outp, "\tPKG_%%");
563 if (DO_BIC(BIC_RAM__))
564 outp += sprintf(outp, "\tRAM_%%");
565 } else if (do_rapl && rapl_joules) {
566 if (DO_BIC(BIC_Pkg_J))
567 outp += sprintf(outp, "\tPkg_J");
568 if (DO_BIC(BIC_Cor_J))
569 outp += sprintf(outp, "\tCor_J");
570 if (DO_BIC(BIC_GFX_J))
571 outp += sprintf(outp, "\tGFX_J");
572 if (DO_BIC(BIC_RAM_J))
573 outp += sprintf(outp, "\tRAM_J");
574 if (DO_BIC(BIC_PKG__))
575 outp += sprintf(outp, "\tPKG_%%");
576 if (DO_BIC(BIC_RAM__))
577 outp += sprintf(outp, "\tRAM_%%");
579 for (mp = sys.pp; mp; mp = mp->next) {
580 if (mp->format == FORMAT_RAW) {
582 outp += sprintf(outp, "\t%18.18s", mp->name);
584 outp += sprintf(outp, "\t%10.10s", mp->name);
586 outp += sprintf(outp, "\t%-7.7s", mp->name);
591 outp += sprintf(outp, "\n");
594 int dump_counters(struct thread_data *t, struct core_data *c,
598 struct msr_counter *mp;
600 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
603 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
604 t->cpu_id, t->flags);
605 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
606 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
607 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
608 outp += sprintf(outp, "c1: %016llX\n", t->c1);
611 outp += sprintf(outp, "IRQ: %08X\n", t->irq_count);
613 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
615 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
616 outp += sprintf(outp, "tADDED [%d] msr0x%x: %08llX\n",
617 i, mp->msr_num, t->counter[i]);
622 outp += sprintf(outp, "core: %d\n", c->core_id);
623 outp += sprintf(outp, "c3: %016llX\n", c->c3);
624 outp += sprintf(outp, "c6: %016llX\n", c->c6);
625 outp += sprintf(outp, "c7: %016llX\n", c->c7);
626 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
628 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
629 outp += sprintf(outp, "cADDED [%d] msr0x%x: %08llX\n",
630 i, mp->msr_num, c->counter[i]);
635 outp += sprintf(outp, "package: %d\n", p->package_id);
637 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
638 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
639 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
640 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
642 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
644 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
646 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
648 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
649 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
650 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
651 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
652 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
653 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
654 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
655 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
656 outp += sprintf(outp, "Throttle PKG: %0X\n",
657 p->rapl_pkg_perf_status);
658 outp += sprintf(outp, "Throttle RAM: %0X\n",
659 p->rapl_dram_perf_status);
660 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
662 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
663 outp += sprintf(outp, "pADDED [%d] msr0x%x: %08llX\n",
664 i, mp->msr_num, p->counter[i]);
668 outp += sprintf(outp, "\n");
674 * column formatting convention & formats
676 int format_counters(struct thread_data *t, struct core_data *c,
679 double interval_float;
682 struct msr_counter *mp;
684 /* if showing only 1st thread in core and this isn't one, bail out */
685 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
688 /* if showing only 1st thread in pkg and this isn't one, bail out */
689 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
692 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
694 /* topo columns, print blanks on 1st (average) line */
695 if (t == &average.threads) {
696 if (DO_BIC(BIC_Package))
697 outp += sprintf(outp, "\t-");
698 if (DO_BIC(BIC_Core))
699 outp += sprintf(outp, "\t-");
701 outp += sprintf(outp, "\t-");
703 if (DO_BIC(BIC_Package)) {
705 outp += sprintf(outp, "\t%d", p->package_id);
707 outp += sprintf(outp, "\t-");
709 if (DO_BIC(BIC_Core)) {
711 outp += sprintf(outp, "\t%d", c->core_id);
713 outp += sprintf(outp, "\t-");
716 outp += sprintf(outp, "\t%d", t->cpu_id);
719 if (DO_BIC(BIC_Avg_MHz))
720 outp += sprintf(outp, "\t%.0f",
721 1.0 / units * t->aperf / interval_float);
723 if (DO_BIC(BIC_Busy))
724 outp += sprintf(outp, "\t%.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
726 if (DO_BIC(BIC_Bzy_MHz)) {
728 outp += sprintf(outp, "\t%.0f", base_hz / units * t->aperf / t->mperf);
730 outp += sprintf(outp, "\t%.0f",
731 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
734 if (DO_BIC(BIC_TSC_MHz))
735 outp += sprintf(outp, "\t%.0f", 1.0 * t->tsc/units/interval_float);
742 outp += sprintf(outp, "\t%d", t->irq_count);
746 outp += sprintf(outp, "\t%d", t->smi_count);
749 if (DO_BIC(BIC_CPU_c1))
750 outp += sprintf(outp, "\t%.2f", 100.0 * t->c1/t->tsc);
753 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
754 if (mp->format == FORMAT_RAW) {
756 outp += sprintf(outp, "\t0x%08lx", (unsigned long) t->counter[i]);
758 outp += sprintf(outp, "\t0x%016llx", t->counter[i]);
759 } else if (mp->format == FORMAT_DELTA) {
760 outp += sprintf(outp, "\t%lld", t->counter[i]);
761 } else if (mp->format == FORMAT_PERCENT) {
762 outp += sprintf(outp, "\t%.2f", 100.0 * t->counter[i]/t->tsc);
766 /* print per-core data only for 1st thread in core */
767 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
770 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates)
771 outp += sprintf(outp, "\t%.2f", 100.0 * c->c3/t->tsc);
772 if (DO_BIC(BIC_CPU_c6))
773 outp += sprintf(outp, "\t%.2f", 100.0 * c->c6/t->tsc);
774 if (DO_BIC(BIC_CPU_c7))
775 outp += sprintf(outp, "\t%.2f", 100.0 * c->c7/t->tsc);
777 if (DO_BIC(BIC_CoreTmp))
778 outp += sprintf(outp, "\t%d", c->core_temp_c);
780 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
781 if (mp->format == FORMAT_RAW) {
783 outp += sprintf(outp, "\t0x%08lx", (unsigned long) c->counter[i]);
785 outp += sprintf(outp, "\t0x%016llx", c->counter[i]);
786 } else if (mp->format == FORMAT_DELTA) {
787 outp += sprintf(outp, "\t%lld", c->counter[i]);
788 } else if (mp->format == FORMAT_PERCENT) {
789 outp += sprintf(outp, "\t%.2f", 100.0 * c->counter[i]/t->tsc);
793 /* print per-package data only for 1st core in package */
794 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
798 if (DO_BIC(BIC_PkgTmp))
799 outp += sprintf(outp, "\t%d", p->pkg_temp_c);
802 if (DO_BIC(BIC_GFX_rc6)) {
803 if (p->gfx_rc6_ms == -1) { /* detect GFX counter reset */
804 outp += sprintf(outp, "\t**.**");
806 outp += sprintf(outp, "\t%.2f",
807 p->gfx_rc6_ms / 10.0 / interval_float);
812 if (DO_BIC(BIC_GFXMHz))
813 outp += sprintf(outp, "\t%d", p->gfx_mhz);
815 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
816 if (do_skl_residency) {
817 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
818 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
819 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
820 outp += sprintf(outp, "\t%.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
824 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc2/t->tsc);
826 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc3/t->tsc);
828 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc6/t->tsc);
830 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc7/t->tsc);
832 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc8/t->tsc);
833 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc9/t->tsc);
834 outp += sprintf(outp, "\t%.2f", 100.0 * p->pc10/t->tsc);
838 * If measurement interval exceeds minimum RAPL Joule Counter range,
839 * indicate that results are suspect by printing "**" in fraction place.
841 if (interval_float < rapl_joule_counter_range)
846 if (DO_BIC(BIC_PkgWatt))
847 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
848 if (DO_BIC(BIC_CorWatt))
849 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
850 if (DO_BIC(BIC_GFXWatt))
851 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
852 if (DO_BIC(BIC_RAMWatt))
853 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
854 if (DO_BIC(BIC_Pkg_J))
855 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units);
856 if (DO_BIC(BIC_Cor_J))
857 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units);
858 if (DO_BIC(BIC_GFX_J))
859 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units);
860 if (DO_BIC(BIC_RAM_J))
861 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units);
862 if (DO_BIC(BIC_PKG__))
863 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
864 if (DO_BIC(BIC_RAM__))
865 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
867 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
868 if (mp->format == FORMAT_RAW) {
870 outp += sprintf(outp, "\t0x%08lx", (unsigned long) p->counter[i]);
872 outp += sprintf(outp, "\t0x%016llx", p->counter[i]);
873 } else if (mp->format == FORMAT_DELTA) {
874 outp += sprintf(outp, "\t%lld", p->counter[i]);
875 } else if (mp->format == FORMAT_PERCENT) {
876 outp += sprintf(outp, "\t%.2f", 100.0 * p->counter[i]/t->tsc);
881 outp += sprintf(outp, "\n");
886 void flush_output_stdout(void)
895 fputs(output_buffer, filep);
898 outp = output_buffer;
900 void flush_output_stderr(void)
902 fputs(output_buffer, outf);
904 outp = output_buffer;
906 void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
910 if (!printed || !summary_only)
913 if (topo.num_cpus > 1)
914 format_counters(&average.threads, &average.cores,
922 for_all_cpus(format_counters, t, c, p);
925 #define DELTA_WRAP32(new, old) \
929 old = 0x100000000 + new - old; \
933 delta_package(struct pkg_data *new, struct pkg_data *old)
936 struct msr_counter *mp;
938 if (do_skl_residency) {
939 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
940 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
941 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
942 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
944 old->pc2 = new->pc2 - old->pc2;
946 old->pc3 = new->pc3 - old->pc3;
948 old->pc6 = new->pc6 - old->pc6;
950 old->pc7 = new->pc7 - old->pc7;
951 old->pc8 = new->pc8 - old->pc8;
952 old->pc9 = new->pc9 - old->pc9;
953 old->pc10 = new->pc10 - old->pc10;
954 old->pkg_temp_c = new->pkg_temp_c;
956 /* flag an error when rc6 counter resets/wraps */
957 if (old->gfx_rc6_ms > new->gfx_rc6_ms)
958 old->gfx_rc6_ms = -1;
960 old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms;
962 old->gfx_mhz = new->gfx_mhz;
964 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
965 DELTA_WRAP32(new->energy_cores, old->energy_cores);
966 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
967 DELTA_WRAP32(new->energy_dram, old->energy_dram);
968 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
969 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
971 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
972 if (mp->format == FORMAT_RAW)
973 old->counter[i] = new->counter[i];
975 old->counter[i] = new->counter[i] - old->counter[i];
982 delta_core(struct core_data *new, struct core_data *old)
985 struct msr_counter *mp;
987 old->c3 = new->c3 - old->c3;
988 old->c6 = new->c6 - old->c6;
989 old->c7 = new->c7 - old->c7;
990 old->core_temp_c = new->core_temp_c;
992 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
993 if (mp->format == FORMAT_RAW)
994 old->counter[i] = new->counter[i];
996 old->counter[i] = new->counter[i] - old->counter[i];
1004 delta_thread(struct thread_data *new, struct thread_data *old,
1005 struct core_data *core_delta)
1008 struct msr_counter *mp;
1010 old->tsc = new->tsc - old->tsc;
1012 /* check for TSC < 1 Mcycles over interval */
1013 if (old->tsc < (1000 * 1000))
1014 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
1015 "You can disable all c-states by booting with \"idle=poll\"\n"
1016 "or just the deep ones with \"processor.max_cstate=1\"");
1018 old->c1 = new->c1 - old->c1;
1020 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1021 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
1022 old->aperf = new->aperf - old->aperf;
1023 old->mperf = new->mperf - old->mperf;
1030 if (use_c1_residency_msr) {
1032 * Some models have a dedicated C1 residency MSR,
1033 * which should be more accurate than the derivation below.
1037 * As counter collection is not atomic,
1038 * it is possible for mperf's non-halted cycles + idle states
1039 * to exceed TSC's all cycles: show c1 = 0% in that case.
1041 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
1044 /* normal case, derive c1 */
1045 old->c1 = old->tsc - old->mperf - core_delta->c3
1046 - core_delta->c6 - core_delta->c7;
1050 if (old->mperf == 0) {
1052 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
1053 old->mperf = 1; /* divide by 0 protection */
1056 if (DO_BIC(BIC_IRQ))
1057 old->irq_count = new->irq_count - old->irq_count;
1059 if (DO_BIC(BIC_SMI))
1060 old->smi_count = new->smi_count - old->smi_count;
1062 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1063 if (mp->format == FORMAT_RAW)
1064 old->counter[i] = new->counter[i];
1066 old->counter[i] = new->counter[i] - old->counter[i];
1071 int delta_cpu(struct thread_data *t, struct core_data *c,
1072 struct pkg_data *p, struct thread_data *t2,
1073 struct core_data *c2, struct pkg_data *p2)
1077 /* calculate core delta only for 1st thread in core */
1078 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
1081 /* always calculate thread delta */
1082 retval = delta_thread(t, t2, c2); /* c2 is core delta */
1086 /* calculate package delta only for 1st core in package */
1087 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
1088 retval = delta_package(p, p2);
1093 void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1096 struct msr_counter *mp;
1106 /* tells format_counters to dump all fields from this set */
1107 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
1114 p->pkg_wtd_core_c0 = 0;
1115 p->pkg_any_core_c0 = 0;
1116 p->pkg_any_gfxe_c0 = 0;
1117 p->pkg_both_core_gfxe_c0 = 0;
1132 p->energy_cores = 0;
1134 p->rapl_pkg_perf_status = 0;
1135 p->rapl_dram_perf_status = 0;
1140 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next)
1143 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next)
1146 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next)
1149 int sum_counters(struct thread_data *t, struct core_data *c,
1153 struct msr_counter *mp;
1155 average.threads.tsc += t->tsc;
1156 average.threads.aperf += t->aperf;
1157 average.threads.mperf += t->mperf;
1158 average.threads.c1 += t->c1;
1160 average.threads.irq_count += t->irq_count;
1161 average.threads.smi_count += t->smi_count;
1163 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1164 if (mp->format == FORMAT_RAW)
1166 average.threads.counter[i] += t->counter[i];
1169 /* sum per-core values only for 1st thread in core */
1170 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1173 average.cores.c3 += c->c3;
1174 average.cores.c6 += c->c6;
1175 average.cores.c7 += c->c7;
1177 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
1179 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1180 if (mp->format == FORMAT_RAW)
1182 average.cores.counter[i] += c->counter[i];
1185 /* sum per-pkg values only for 1st core in pkg */
1186 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1189 if (do_skl_residency) {
1190 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
1191 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
1192 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
1193 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
1196 average.packages.pc2 += p->pc2;
1198 average.packages.pc3 += p->pc3;
1200 average.packages.pc6 += p->pc6;
1202 average.packages.pc7 += p->pc7;
1203 average.packages.pc8 += p->pc8;
1204 average.packages.pc9 += p->pc9;
1205 average.packages.pc10 += p->pc10;
1207 average.packages.energy_pkg += p->energy_pkg;
1208 average.packages.energy_dram += p->energy_dram;
1209 average.packages.energy_cores += p->energy_cores;
1210 average.packages.energy_gfx += p->energy_gfx;
1212 average.packages.gfx_rc6_ms = p->gfx_rc6_ms;
1213 average.packages.gfx_mhz = p->gfx_mhz;
1215 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
1217 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
1218 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
1220 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1221 if (mp->format == FORMAT_RAW)
1223 average.packages.counter[i] += p->counter[i];
1228 * sum the counters for all cpus in the system
1229 * compute the weighted average
1231 void compute_average(struct thread_data *t, struct core_data *c,
1235 struct msr_counter *mp;
1237 clear_counters(&average.threads, &average.cores, &average.packages);
1239 for_all_cpus(sum_counters, t, c, p);
1241 average.threads.tsc /= topo.num_cpus;
1242 average.threads.aperf /= topo.num_cpus;
1243 average.threads.mperf /= topo.num_cpus;
1244 average.threads.c1 /= topo.num_cpus;
1246 average.cores.c3 /= topo.num_cores;
1247 average.cores.c6 /= topo.num_cores;
1248 average.cores.c7 /= topo.num_cores;
1250 if (do_skl_residency) {
1251 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
1252 average.packages.pkg_any_core_c0 /= topo.num_packages;
1253 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
1254 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
1257 average.packages.pc2 /= topo.num_packages;
1259 average.packages.pc3 /= topo.num_packages;
1261 average.packages.pc6 /= topo.num_packages;
1263 average.packages.pc7 /= topo.num_packages;
1265 average.packages.pc8 /= topo.num_packages;
1266 average.packages.pc9 /= topo.num_packages;
1267 average.packages.pc10 /= topo.num_packages;
1269 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1270 if (mp->format == FORMAT_RAW)
1272 average.threads.counter[i] /= topo.num_cpus;
1274 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1275 if (mp->format == FORMAT_RAW)
1277 average.cores.counter[i] /= topo.num_cores;
1279 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1280 if (mp->format == FORMAT_RAW)
1282 average.packages.counter[i] /= topo.num_packages;
1286 static unsigned long long rdtsc(void)
1288 unsigned int low, high;
1290 asm volatile("rdtsc" : "=a" (low), "=d" (high));
1292 return low | ((unsigned long long)high) << 32;
1298 * acquire and record local counters for that cpu
1300 int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
1302 int cpu = t->cpu_id;
1303 unsigned long long msr;
1304 int aperf_mperf_retry_count = 0;
1305 struct msr_counter *mp;
1308 if (cpu_migrate(cpu)) {
1309 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
1314 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1316 if (DO_BIC(BIC_Avg_MHz) || DO_BIC(BIC_Busy) || DO_BIC(BIC_Bzy_MHz)) {
1317 unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time;
1320 * The TSC, APERF and MPERF must be read together for
1321 * APERF/MPERF and MPERF/TSC to give accurate results.
1323 * Unfortunately, APERF and MPERF are read by
1324 * individual system call, so delays may occur
1325 * between them. If the time to read them
1326 * varies by a large amount, we re-read them.
1330 * This initial dummy APERF read has been seen to
1331 * reduce jitter in the subsequent reads.
1334 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1337 t->tsc = rdtsc(); /* re-read close to APERF */
1339 tsc_before = t->tsc;
1341 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
1344 tsc_between = rdtsc();
1346 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
1349 tsc_after = rdtsc();
1351 aperf_time = tsc_between - tsc_before;
1352 mperf_time = tsc_after - tsc_between;
1355 * If the system call latency to read APERF and MPERF
1356 * differ by more than 2x, then try again.
1358 if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) {
1359 aperf_mperf_retry_count++;
1360 if (aperf_mperf_retry_count < 5)
1363 warnx("cpu%d jitter %lld %lld",
1364 cpu, aperf_time, mperf_time);
1366 aperf_mperf_retry_count = 0;
1368 t->aperf = t->aperf * aperf_mperf_multiplier;
1369 t->mperf = t->mperf * aperf_mperf_multiplier;
1372 if (DO_BIC(BIC_IRQ))
1373 t->irq_count = irqs_per_cpu[cpu];
1374 if (DO_BIC(BIC_SMI)) {
1375 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1377 t->smi_count = msr & 0xFFFFFFFF;
1380 if (use_c1_residency_msr) {
1381 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1385 for (i = 0, mp = sys.tp; mp; i++, mp = mp->next) {
1386 if (get_msr(cpu, mp->msr_num, &t->counter[i]))
1391 /* collect core counters only for 1st thread in core */
1392 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1395 if (DO_BIC(BIC_CPU_c3) && !do_slm_cstates && !do_knl_cstates) {
1396 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1400 if (DO_BIC(BIC_CPU_c6) && !do_knl_cstates) {
1401 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1403 } else if (do_knl_cstates) {
1404 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1408 if (DO_BIC(BIC_CPU_c7))
1409 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1412 if (DO_BIC(BIC_CoreTmp)) {
1413 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1415 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1418 for (i = 0, mp = sys.cp; mp; i++, mp = mp->next) {
1419 if (get_msr(cpu, mp->msr_num, &c->counter[i]))
1423 /* collect package counters only for 1st core in package */
1424 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1427 if (do_skl_residency) {
1428 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1430 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1432 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1434 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1438 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1441 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1444 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1447 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1450 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1452 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1454 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1457 if (do_rapl & RAPL_PKG) {
1458 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1460 p->energy_pkg = msr & 0xFFFFFFFF;
1462 if (do_rapl & RAPL_CORES_ENERGY_STATUS) {
1463 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1465 p->energy_cores = msr & 0xFFFFFFFF;
1467 if (do_rapl & RAPL_DRAM) {
1468 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1470 p->energy_dram = msr & 0xFFFFFFFF;
1472 if (do_rapl & RAPL_GFX) {
1473 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1475 p->energy_gfx = msr & 0xFFFFFFFF;
1477 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1478 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1480 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1482 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1483 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1485 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1487 if (DO_BIC(BIC_PkgTmp)) {
1488 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1490 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1493 if (DO_BIC(BIC_GFX_rc6))
1494 p->gfx_rc6_ms = gfx_cur_rc6_ms;
1496 if (DO_BIC(BIC_GFXMHz))
1497 p->gfx_mhz = gfx_cur_mhz;
1499 for (i = 0, mp = sys.pp; mp; i++, mp = mp->next) {
1500 if (get_msr(cpu, mp->msr_num, &p->counter[i]))
1508 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1509 * If you change the values, note they are used both in comparisons
1510 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1513 #define PCLUKN 0 /* Unknown */
1514 #define PCLRSV 1 /* Reserved */
1515 #define PCL__0 2 /* PC0 */
1516 #define PCL__1 3 /* PC1 */
1517 #define PCL__2 4 /* PC2 */
1518 #define PCL__3 5 /* PC3 */
1519 #define PCL__4 6 /* PC4 */
1520 #define PCL__6 7 /* PC6 */
1521 #define PCL_6N 8 /* PC6 No Retention */
1522 #define PCL_6R 9 /* PC6 Retention */
1523 #define PCL__7 10 /* PC7 */
1524 #define PCL_7S 11 /* PC7 Shrink */
1525 #define PCL__8 12 /* PC8 */
1526 #define PCL__9 13 /* PC9 */
1527 #define PCLUNL 14 /* Unlimited */
1529 int pkg_cstate_limit = PCLUKN;
1530 char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
1531 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
1533 int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1534 int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1535 int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1536 int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1537 int amt_pkg_cstate_limits[16] = {PCLUNL, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1538 int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1539 int bxt_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1540 int skx_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1544 calculate_tsc_tweak()
1546 tsc_tweak = base_hz / tsc_hz;
1550 dump_nhm_platform_info(void)
1552 unsigned long long msr;
1555 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
1557 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
1559 ratio = (msr >> 40) & 0xFF;
1560 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n",
1561 ratio, bclk, ratio * bclk);
1563 ratio = (msr >> 8) & 0xFF;
1564 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n",
1565 ratio, bclk, ratio * bclk);
1567 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
1568 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
1569 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
1575 dump_hsw_turbo_ratio_limits(void)
1577 unsigned long long msr;
1580 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
1582 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
1584 ratio = (msr >> 8) & 0xFF;
1586 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n",
1587 ratio, bclk, ratio * bclk);
1589 ratio = (msr >> 0) & 0xFF;
1591 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n",
1592 ratio, bclk, ratio * bclk);
1597 dump_ivt_turbo_ratio_limits(void)
1599 unsigned long long msr;
1602 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
1604 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
1606 ratio = (msr >> 56) & 0xFF;
1608 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n",
1609 ratio, bclk, ratio * bclk);
1611 ratio = (msr >> 48) & 0xFF;
1613 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n",
1614 ratio, bclk, ratio * bclk);
1616 ratio = (msr >> 40) & 0xFF;
1618 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n",
1619 ratio, bclk, ratio * bclk);
1621 ratio = (msr >> 32) & 0xFF;
1623 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n",
1624 ratio, bclk, ratio * bclk);
1626 ratio = (msr >> 24) & 0xFF;
1628 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n",
1629 ratio, bclk, ratio * bclk);
1631 ratio = (msr >> 16) & 0xFF;
1633 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n",
1634 ratio, bclk, ratio * bclk);
1636 ratio = (msr >> 8) & 0xFF;
1638 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n",
1639 ratio, bclk, ratio * bclk);
1641 ratio = (msr >> 0) & 0xFF;
1643 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n",
1644 ratio, bclk, ratio * bclk);
1649 dump_nhm_turbo_ratio_limits(void)
1651 unsigned long long msr;
1654 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1656 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
1658 ratio = (msr >> 56) & 0xFF;
1660 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n",
1661 ratio, bclk, ratio * bclk);
1663 ratio = (msr >> 48) & 0xFF;
1665 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n",
1666 ratio, bclk, ratio * bclk);
1668 ratio = (msr >> 40) & 0xFF;
1670 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n",
1671 ratio, bclk, ratio * bclk);
1673 ratio = (msr >> 32) & 0xFF;
1675 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n",
1676 ratio, bclk, ratio * bclk);
1678 ratio = (msr >> 24) & 0xFF;
1680 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n",
1681 ratio, bclk, ratio * bclk);
1683 ratio = (msr >> 16) & 0xFF;
1685 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n",
1686 ratio, bclk, ratio * bclk);
1688 ratio = (msr >> 8) & 0xFF;
1690 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n",
1691 ratio, bclk, ratio * bclk);
1693 ratio = (msr >> 0) & 0xFF;
1695 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n",
1696 ratio, bclk, ratio * bclk);
1701 dump_knl_turbo_ratio_limits(void)
1703 const unsigned int buckets_no = 7;
1705 unsigned long long msr;
1706 int delta_cores, delta_ratio;
1708 unsigned int cores[buckets_no];
1709 unsigned int ratio[buckets_no];
1711 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
1713 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
1717 * Turbo encoding in KNL is as follows:
1719 * [7:1] -- Base value of number of active cores of bucket 1.
1720 * [15:8] -- Base value of freq ratio of bucket 1.
1721 * [20:16] -- +ve delta of number of active cores of bucket 2.
1722 * i.e. active cores of bucket 2 =
1723 * active cores of bucket 1 + delta
1724 * [23:21] -- Negative delta of freq ratio of bucket 2.
1725 * i.e. freq ratio of bucket 2 =
1726 * freq ratio of bucket 1 - delta
1727 * [28:24]-- +ve delta of number of active cores of bucket 3.
1728 * [31:29]-- -ve delta of freq ratio of bucket 3.
1729 * [36:32]-- +ve delta of number of active cores of bucket 4.
1730 * [39:37]-- -ve delta of freq ratio of bucket 4.
1731 * [44:40]-- +ve delta of number of active cores of bucket 5.
1732 * [47:45]-- -ve delta of freq ratio of bucket 5.
1733 * [52:48]-- +ve delta of number of active cores of bucket 6.
1734 * [55:53]-- -ve delta of freq ratio of bucket 6.
1735 * [60:56]-- +ve delta of number of active cores of bucket 7.
1736 * [63:61]-- -ve delta of freq ratio of bucket 7.
1740 cores[b_nr] = (msr & 0xFF) >> 1;
1741 ratio[b_nr] = (msr >> 8) & 0xFF;
1743 for (i = 16; i < 64; i += 8) {
1744 delta_cores = (msr >> i) & 0x1F;
1745 delta_ratio = (msr >> (i + 5)) & 0x7;
1747 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1748 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1752 for (i = buckets_no - 1; i >= 0; i--)
1753 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
1755 "%d * %.0f = %.0f MHz max turbo %d active cores\n",
1756 ratio[i], bclk, ratio[i] * bclk, cores[i]);
1760 dump_nhm_cst_cfg(void)
1762 unsigned long long msr;
1764 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
1766 #define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1767 #define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1769 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr);
1771 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
1772 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1773 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1774 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1775 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1776 (msr & (1 << 15)) ? "" : "UN",
1777 (unsigned int)msr & 0xF,
1778 pkg_cstate_limit_strings[pkg_cstate_limit]);
1783 dump_config_tdp(void)
1785 unsigned long long msr;
1787 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
1788 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
1789 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF);
1791 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
1792 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
1794 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1795 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1796 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1797 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF);
1799 fprintf(outf, ")\n");
1801 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
1802 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
1804 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF);
1805 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF);
1806 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF);
1807 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF);
1809 fprintf(outf, ")\n");
1811 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
1812 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
1814 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1815 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1816 fprintf(outf, ")\n");
1818 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
1819 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
1820 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF);
1821 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1822 fprintf(outf, ")\n");
1825 unsigned int irtl_time_units[] = {1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1827 void print_irtl(void)
1829 unsigned long long msr;
1831 get_msr(base_cpu, MSR_PKGC3_IRTL, &msr);
1832 fprintf(outf, "cpu%d: MSR_PKGC3_IRTL: 0x%08llx (", base_cpu, msr);
1833 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1834 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1836 get_msr(base_cpu, MSR_PKGC6_IRTL, &msr);
1837 fprintf(outf, "cpu%d: MSR_PKGC6_IRTL: 0x%08llx (", base_cpu, msr);
1838 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1839 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1841 get_msr(base_cpu, MSR_PKGC7_IRTL, &msr);
1842 fprintf(outf, "cpu%d: MSR_PKGC7_IRTL: 0x%08llx (", base_cpu, msr);
1843 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1844 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1849 get_msr(base_cpu, MSR_PKGC8_IRTL, &msr);
1850 fprintf(outf, "cpu%d: MSR_PKGC8_IRTL: 0x%08llx (", base_cpu, msr);
1851 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1852 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1854 get_msr(base_cpu, MSR_PKGC9_IRTL, &msr);
1855 fprintf(outf, "cpu%d: MSR_PKGC9_IRTL: 0x%08llx (", base_cpu, msr);
1856 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1857 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1859 get_msr(base_cpu, MSR_PKGC10_IRTL, &msr);
1860 fprintf(outf, "cpu%d: MSR_PKGC10_IRTL: 0x%08llx (", base_cpu, msr);
1861 fprintf(outf, "%svalid, %lld ns)\n", msr & (1 << 15) ? "" : "NOT",
1862 (msr & 0x3FF) * irtl_time_units[(msr >> 10) & 0x3]);
1865 void free_fd_percpu(void)
1869 for (i = 0; i < topo.max_cpu_num + 1; ++i) {
1870 if (fd_percpu[i] != 0)
1871 close(fd_percpu[i]);
1877 void free_all_buffers(void)
1879 CPU_FREE(cpu_present_set);
1880 cpu_present_set = NULL;
1881 cpu_present_setsize = 0;
1883 CPU_FREE(cpu_affinity_set);
1884 cpu_affinity_set = NULL;
1885 cpu_affinity_setsize = 0;
1893 package_even = NULL;
1903 free(output_buffer);
1904 output_buffer = NULL;
1909 free(irq_column_2_cpu);
1914 * Open a file, and exit on failure
1916 FILE *fopen_or_die(const char *path, const char *mode)
1918 FILE *filep = fopen(path, mode);
1920 err(1, "%s: open failed", path);
1925 * Parse a file containing a single int.
1927 int parse_int_file(const char *fmt, ...)
1930 char path[PATH_MAX];
1934 va_start(args, fmt);
1935 vsnprintf(path, sizeof(path), fmt, args);
1937 filep = fopen_or_die(path, "r");
1938 if (fscanf(filep, "%d", &value) != 1)
1939 err(1, "%s: failed to parse number from file", path);
1945 * get_cpu_position_in_core(cpu)
1946 * return the position of the CPU among its HT siblings in the core
1947 * return -1 if the sibling is not in list
1949 int get_cpu_position_in_core(int cpu)
1958 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
1960 filep = fopen(path, "r");
1961 if (filep == NULL) {
1966 for (i = 0; i < topo.num_threads_per_core; i++) {
1967 fscanf(filep, "%d", &this_cpu);
1968 if (this_cpu == cpu) {
1973 /* Account for no separator after last thread*/
1974 if (i != (topo.num_threads_per_core - 1))
1975 fscanf(filep, "%c", &character);
1983 * cpu_is_first_core_in_package(cpu)
1984 * return 1 if given CPU is 1st core in package
1986 int cpu_is_first_core_in_package(int cpu)
1988 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
1991 int get_physical_package_id(int cpu)
1993 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
1996 int get_core_id(int cpu)
1998 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
2001 int get_num_ht_siblings(int cpu)
2011 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
2012 filep = fopen_or_die(path, "r");
2016 * A ',' separated or '-' separated set of numbers
2017 * (eg 1-2 or 1,3,4,5)
2019 fscanf(filep, "%d%c\n", &sib1, &character);
2020 fseek(filep, 0, SEEK_SET);
2021 fgets(str, 100, filep);
2022 ch = strchr(str, character);
2023 while (ch != NULL) {
2025 ch = strchr(ch+1, character);
2033 * run func(thread, core, package) in topology order
2034 * skip non-present cpus
2037 int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
2038 struct pkg_data *, struct thread_data *, struct core_data *,
2039 struct pkg_data *), struct thread_data *thread_base,
2040 struct core_data *core_base, struct pkg_data *pkg_base,
2041 struct thread_data *thread_base2, struct core_data *core_base2,
2042 struct pkg_data *pkg_base2)
2044 int retval, pkg_no, core_no, thread_no;
2046 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
2047 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
2048 for (thread_no = 0; thread_no <
2049 topo.num_threads_per_core; ++thread_no) {
2050 struct thread_data *t, *t2;
2051 struct core_data *c, *c2;
2052 struct pkg_data *p, *p2;
2054 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
2056 if (cpu_is_not_present(t->cpu_id))
2059 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
2061 c = GET_CORE(core_base, core_no, pkg_no);
2062 c2 = GET_CORE(core_base2, core_no, pkg_no);
2064 p = GET_PKG(pkg_base, pkg_no);
2065 p2 = GET_PKG(pkg_base2, pkg_no);
2067 retval = func(t, c, p, t2, c2, p2);
2077 * run func(cpu) on every cpu in /proc/stat
2078 * return max_cpu number
2080 int for_all_proc_cpus(int (func)(int))
2086 fp = fopen_or_die(proc_stat, "r");
2088 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
2090 err(1, "%s: failed to parse format", proc_stat);
2093 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
2097 retval = func(cpu_num);
2107 void re_initialize(void)
2110 setup_all_buffers();
2111 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
2117 * remember the last one seen, it will be the max
2119 int count_cpus(int cpu)
2121 if (topo.max_cpu_num < cpu)
2122 topo.max_cpu_num = cpu;
2127 int mark_cpu_present(int cpu)
2129 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
2134 * snapshot_proc_interrupts()
2136 * read and record summary of /proc/interrupts
2138 * return 1 if config change requires a restart, else return 0
2140 int snapshot_proc_interrupts(void)
2146 fp = fopen_or_die("/proc/interrupts", "r");
2150 /* read 1st line of /proc/interrupts to get cpu* name for each column */
2151 for (column = 0; column < topo.num_cpus; ++column) {
2154 retval = fscanf(fp, " CPU%d", &cpu_number);
2158 if (cpu_number > topo.max_cpu_num) {
2159 warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num);
2163 irq_column_2_cpu[column] = cpu_number;
2164 irqs_per_cpu[cpu_number] = 0;
2167 /* read /proc/interrupt count lines and sum up irqs per cpu */
2172 retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */
2176 /* read the count per cpu */
2177 for (column = 0; column < topo.num_cpus; ++column) {
2179 int cpu_number, irq_count;
2181 retval = fscanf(fp, " %d", &irq_count);
2185 cpu_number = irq_column_2_cpu[column];
2186 irqs_per_cpu[cpu_number] += irq_count;
2190 while (getc(fp) != '\n')
2191 ; /* flush interrupt description */
2197 * snapshot_gfx_rc6_ms()
2199 * record snapshot of
2200 * /sys/class/drm/card0/power/rc6_residency_ms
2202 * return 1 if config change requires a restart, else return 0
2204 int snapshot_gfx_rc6_ms(void)
2209 fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r");
2211 retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms);
2220 * snapshot_gfx_mhz()
2222 * record snapshot of
2223 * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz
2225 * return 1 if config change requires a restart, else return 0
2227 int snapshot_gfx_mhz(void)
2233 fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r");
2237 retval = fscanf(fp, "%d", &gfx_cur_mhz);
2245 * snapshot /proc and /sys files
2247 * return 1 if configuration restart needed, else return 0
2249 int snapshot_proc_sysfs_files(void)
2251 if (snapshot_proc_interrupts())
2254 if (DO_BIC(BIC_GFX_rc6))
2255 snapshot_gfx_rc6_ms();
2257 if (DO_BIC(BIC_GFXMHz))
2263 void turbostat_loop()
2271 snapshot_proc_sysfs_files();
2272 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2275 } else if (retval == -1) {
2276 if (restarted > 1) {
2283 gettimeofday(&tv_even, (struct timezone *)NULL);
2286 if (for_all_proc_cpus(cpu_is_not_present)) {
2290 nanosleep(&interval_ts, NULL);
2291 if (snapshot_proc_sysfs_files())
2293 retval = for_all_cpus(get_counters, ODD_COUNTERS);
2296 } else if (retval == -1) {
2300 gettimeofday(&tv_odd, (struct timezone *)NULL);
2301 timersub(&tv_odd, &tv_even, &tv_delta);
2302 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS)) {
2306 compute_average(EVEN_COUNTERS);
2307 format_all_counters(EVEN_COUNTERS);
2308 flush_output_stdout();
2309 nanosleep(&interval_ts, NULL);
2310 if (snapshot_proc_sysfs_files())
2312 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
2315 } else if (retval == -1) {
2319 gettimeofday(&tv_even, (struct timezone *)NULL);
2320 timersub(&tv_even, &tv_odd, &tv_delta);
2321 if (for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS)) {
2325 compute_average(ODD_COUNTERS);
2326 format_all_counters(ODD_COUNTERS);
2327 flush_output_stdout();
2331 void check_dev_msr()
2336 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2337 if (stat(pathname, &sb))
2338 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
2339 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
2342 void check_permissions()
2344 struct __user_cap_header_struct cap_header_data;
2345 cap_user_header_t cap_header = &cap_header_data;
2346 struct __user_cap_data_struct cap_data_data;
2347 cap_user_data_t cap_data = &cap_data_data;
2348 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
2352 /* check for CAP_SYS_RAWIO */
2353 cap_header->pid = getpid();
2354 cap_header->version = _LINUX_CAPABILITY_VERSION;
2355 if (capget(cap_header, cap_data) < 0)
2356 err(-6, "capget(2) failed");
2358 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
2360 warnx("capget(CAP_SYS_RAWIO) failed,"
2361 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
2364 /* test file permissions */
2365 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
2366 if (euidaccess(pathname, R_OK)) {
2368 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
2371 /* if all else fails, thell them to be root */
2374 warnx("... or simply run as root");
2381 * NHM adds support for additional MSRs:
2383 * MSR_SMI_COUNT 0x00000034
2385 * MSR_PLATFORM_INFO 0x000000ce
2386 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
2388 * MSR_MISC_PWR_MGMT 0x000001aa
2390 * MSR_PKG_C3_RESIDENCY 0x000003f8
2391 * MSR_PKG_C6_RESIDENCY 0x000003f9
2392 * MSR_CORE_C3_RESIDENCY 0x000003fc
2393 * MSR_CORE_C6_RESIDENCY 0x000003fd
2396 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
2398 int probe_nhm_msrs(unsigned int family, unsigned int model)
2400 unsigned long long msr;
2401 unsigned int base_ratio;
2402 int *pkg_cstate_limits;
2410 bclk = discover_bclk(family, model);
2413 case INTEL_FAM6_NEHALEM_EP: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
2414 case INTEL_FAM6_NEHALEM: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
2415 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
2416 case INTEL_FAM6_WESTMERE: /* Westmere Client - Clarkdale, Arrandale */
2417 case INTEL_FAM6_WESTMERE_EP: /* Westmere EP - Gulftown */
2418 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2419 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2420 pkg_cstate_limits = nhm_pkg_cstate_limits;
2422 case INTEL_FAM6_SANDYBRIDGE: /* SNB */
2423 case INTEL_FAM6_SANDYBRIDGE_X: /* SNB Xeon */
2424 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2425 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2426 pkg_cstate_limits = snb_pkg_cstate_limits;
2428 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2429 case INTEL_FAM6_HASWELL_X: /* HSX */
2430 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2431 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2432 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2433 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2434 case INTEL_FAM6_BROADWELL_X: /* BDX */
2435 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2436 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2437 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2438 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2439 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2440 pkg_cstate_limits = hsw_pkg_cstate_limits;
2442 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2443 pkg_cstate_limits = skx_pkg_cstate_limits;
2445 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
2446 no_MSR_MISC_PWR_MGMT = 1;
2447 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
2448 pkg_cstate_limits = slv_pkg_cstate_limits;
2450 case INTEL_FAM6_ATOM_AIRMONT: /* AMT */
2451 pkg_cstate_limits = amt_pkg_cstate_limits;
2452 no_MSR_MISC_PWR_MGMT = 1;
2454 case INTEL_FAM6_XEON_PHI_KNL: /* PHI */
2455 case INTEL_FAM6_XEON_PHI_KNM:
2456 pkg_cstate_limits = phi_pkg_cstate_limits;
2458 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2459 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
2460 pkg_cstate_limits = bxt_pkg_cstate_limits;
2465 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
2466 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
2468 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
2469 base_ratio = (msr >> 8) & 0xFF;
2471 base_hz = base_ratio * bclk * 1000000;
2475 int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
2478 /* Nehalem compatible, but do not include turbo-ratio limit support */
2479 case INTEL_FAM6_NEHALEM_EX: /* Nehalem-EX Xeon - Beckton */
2480 case INTEL_FAM6_WESTMERE_EX: /* Westmere-EX Xeon - Eagleton */
2481 case INTEL_FAM6_XEON_PHI_KNL: /* PHI - Knights Landing (different MSR definition) */
2482 case INTEL_FAM6_XEON_PHI_KNM:
2488 int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
2497 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
2498 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2504 int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
2513 case INTEL_FAM6_HASWELL_X: /* HSW Xeon */
2520 int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
2529 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2530 case INTEL_FAM6_XEON_PHI_KNM:
2536 int has_config_tdp(unsigned int family, unsigned int model)
2545 case INTEL_FAM6_IVYBRIDGE: /* IVB */
2546 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2547 case INTEL_FAM6_HASWELL_X: /* HSX */
2548 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2549 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2550 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2551 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2552 case INTEL_FAM6_BROADWELL_X: /* BDX */
2553 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2554 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2555 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2556 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2557 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2558 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2560 case INTEL_FAM6_XEON_PHI_KNL: /* Knights Landing */
2561 case INTEL_FAM6_XEON_PHI_KNM:
2569 dump_cstate_pstate_config_info(unsigned int family, unsigned int model)
2571 if (!do_nhm_platform_info)
2574 dump_nhm_platform_info();
2576 if (has_hsw_turbo_ratio_limit(family, model))
2577 dump_hsw_turbo_ratio_limits();
2579 if (has_ivt_turbo_ratio_limit(family, model))
2580 dump_ivt_turbo_ratio_limits();
2582 if (has_nhm_turbo_ratio_limit(family, model))
2583 dump_nhm_turbo_ratio_limits();
2585 if (has_knl_turbo_ratio_limit(family, model))
2586 dump_knl_turbo_ratio_limits();
2588 if (has_config_tdp(family, model))
2597 * Decode the ENERGY_PERF_BIAS MSR
2599 int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2601 unsigned long long msr;
2610 /* EPB is per-package */
2611 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2614 if (cpu_migrate(cpu)) {
2615 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2619 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2622 switch (msr & 0xF) {
2623 case ENERGY_PERF_BIAS_PERFORMANCE:
2624 epb_string = "performance";
2626 case ENERGY_PERF_BIAS_NORMAL:
2627 epb_string = "balanced";
2629 case ENERGY_PERF_BIAS_POWERSAVE:
2630 epb_string = "powersave";
2633 epb_string = "custom";
2636 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
2642 * Decode the MSR_HWP_CAPABILITIES
2644 int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2646 unsigned long long msr;
2654 /* MSR_HWP_CAPABILITIES is per-package */
2655 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2658 if (cpu_migrate(cpu)) {
2659 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2663 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2666 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
2667 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2669 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2670 if ((msr & (1 << 0)) == 0)
2673 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2676 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
2677 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2679 (unsigned int)HWP_HIGHEST_PERF(msr),
2680 (unsigned int)HWP_GUARANTEED_PERF(msr),
2681 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2682 (unsigned int)HWP_LOWEST_PERF(msr));
2684 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2687 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
2688 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2690 (unsigned int)(((msr) >> 0) & 0xff),
2691 (unsigned int)(((msr) >> 8) & 0xff),
2692 (unsigned int)(((msr) >> 16) & 0xff),
2693 (unsigned int)(((msr) >> 24) & 0xff),
2694 (unsigned int)(((msr) >> 32) & 0xff3),
2695 (unsigned int)(((msr) >> 42) & 0x1));
2698 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2701 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
2702 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2704 (unsigned int)(((msr) >> 0) & 0xff),
2705 (unsigned int)(((msr) >> 8) & 0xff),
2706 (unsigned int)(((msr) >> 16) & 0xff),
2707 (unsigned int)(((msr) >> 24) & 0xff),
2708 (unsigned int)(((msr) >> 32) & 0xff3));
2710 if (has_hwp_notify) {
2711 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2714 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
2715 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2717 ((msr) & 0x1) ? "EN" : "Dis",
2718 ((msr) & 0x2) ? "EN" : "Dis");
2720 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2723 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
2724 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2726 ((msr) & 0x1) ? "" : "No-",
2727 ((msr) & 0x2) ? "" : "No-");
2733 * print_perf_limit()
2735 int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2737 unsigned long long msr;
2743 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2746 if (cpu_migrate(cpu)) {
2747 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
2751 if (do_core_perf_limit_reasons) {
2752 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
2753 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2754 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
2755 (msr & 1 << 15) ? "bit15, " : "",
2756 (msr & 1 << 14) ? "bit14, " : "",
2757 (msr & 1 << 13) ? "Transitions, " : "",
2758 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2759 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2760 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2761 (msr & 1 << 9) ? "CorePwr, " : "",
2762 (msr & 1 << 8) ? "Amps, " : "",
2763 (msr & 1 << 6) ? "VR-Therm, " : "",
2764 (msr & 1 << 5) ? "Auto-HWP, " : "",
2765 (msr & 1 << 4) ? "Graphics, " : "",
2766 (msr & 1 << 2) ? "bit2, " : "",
2767 (msr & 1 << 1) ? "ThermStatus, " : "",
2768 (msr & 1 << 0) ? "PROCHOT, " : "");
2769 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
2770 (msr & 1 << 31) ? "bit31, " : "",
2771 (msr & 1 << 30) ? "bit30, " : "",
2772 (msr & 1 << 29) ? "Transitions, " : "",
2773 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2774 (msr & 1 << 27) ? "PkgPwrL2, " : "",
2775 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2776 (msr & 1 << 25) ? "CorePwr, " : "",
2777 (msr & 1 << 24) ? "Amps, " : "",
2778 (msr & 1 << 22) ? "VR-Therm, " : "",
2779 (msr & 1 << 21) ? "Auto-HWP, " : "",
2780 (msr & 1 << 20) ? "Graphics, " : "",
2781 (msr & 1 << 18) ? "bit18, " : "",
2782 (msr & 1 << 17) ? "ThermStatus, " : "",
2783 (msr & 1 << 16) ? "PROCHOT, " : "");
2786 if (do_gfx_perf_limit_reasons) {
2787 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
2788 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2789 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
2790 (msr & 1 << 0) ? "PROCHOT, " : "",
2791 (msr & 1 << 1) ? "ThermStatus, " : "",
2792 (msr & 1 << 4) ? "Graphics, " : "",
2793 (msr & 1 << 6) ? "VR-Therm, " : "",
2794 (msr & 1 << 8) ? "Amps, " : "",
2795 (msr & 1 << 9) ? "GFXPwr, " : "",
2796 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2797 (msr & 1 << 11) ? "PkgPwrL2, " : "");
2798 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
2799 (msr & 1 << 16) ? "PROCHOT, " : "",
2800 (msr & 1 << 17) ? "ThermStatus, " : "",
2801 (msr & 1 << 20) ? "Graphics, " : "",
2802 (msr & 1 << 22) ? "VR-Therm, " : "",
2803 (msr & 1 << 24) ? "Amps, " : "",
2804 (msr & 1 << 25) ? "GFXPwr, " : "",
2805 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2806 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2808 if (do_ring_perf_limit_reasons) {
2809 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
2810 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2811 fprintf(outf, " (Active: %s%s%s%s%s%s)",
2812 (msr & 1 << 0) ? "PROCHOT, " : "",
2813 (msr & 1 << 1) ? "ThermStatus, " : "",
2814 (msr & 1 << 6) ? "VR-Therm, " : "",
2815 (msr & 1 << 8) ? "Amps, " : "",
2816 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2817 (msr & 1 << 11) ? "PkgPwrL2, " : "");
2818 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
2819 (msr & 1 << 16) ? "PROCHOT, " : "",
2820 (msr & 1 << 17) ? "ThermStatus, " : "",
2821 (msr & 1 << 22) ? "VR-Therm, " : "",
2822 (msr & 1 << 24) ? "Amps, " : "",
2823 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2824 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2829 #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
2830 #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
2832 double get_tdp(unsigned int model)
2834 unsigned long long msr;
2836 if (do_rapl & RAPL_PKG_POWER_INFO)
2837 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
2838 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2841 case INTEL_FAM6_ATOM_SILVERMONT1:
2842 case INTEL_FAM6_ATOM_SILVERMONT2:
2850 * rapl_dram_energy_units_probe()
2851 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2854 rapl_dram_energy_units_probe(int model, double rapl_energy_units)
2856 /* only called for genuine_intel, family 6 */
2859 case INTEL_FAM6_HASWELL_X: /* HSX */
2860 case INTEL_FAM6_BROADWELL_X: /* BDX */
2861 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2862 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
2863 case INTEL_FAM6_XEON_PHI_KNM:
2864 return (rapl_dram_energy_units = 15.3 / 1000000);
2866 return (rapl_energy_units);
2874 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
2876 void rapl_probe(unsigned int family, unsigned int model)
2878 unsigned long long msr;
2879 unsigned int time_unit;
2889 case INTEL_FAM6_SANDYBRIDGE:
2890 case INTEL_FAM6_IVYBRIDGE:
2891 case INTEL_FAM6_HASWELL_CORE: /* HSW */
2892 case INTEL_FAM6_HASWELL_ULT: /* HSW */
2893 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
2894 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
2895 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
2896 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
2898 BIC_PRESENT(BIC_Pkg_J);
2899 BIC_PRESENT(BIC_Cor_J);
2900 BIC_PRESENT(BIC_GFX_J);
2902 BIC_PRESENT(BIC_PkgWatt);
2903 BIC_PRESENT(BIC_CorWatt);
2904 BIC_PRESENT(BIC_GFXWatt);
2907 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
2908 do_rapl = RAPL_PKG | RAPL_PKG_POWER_INFO;
2910 BIC_PRESENT(BIC_Pkg_J);
2912 BIC_PRESENT(BIC_PkgWatt);
2914 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
2915 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
2916 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
2917 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
2918 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2919 BIC_PRESENT(BIC_PKG__);
2920 BIC_PRESENT(BIC_RAM__);
2922 BIC_PRESENT(BIC_Pkg_J);
2923 BIC_PRESENT(BIC_Cor_J);
2924 BIC_PRESENT(BIC_RAM_J);
2926 BIC_PRESENT(BIC_PkgWatt);
2927 BIC_PRESENT(BIC_CorWatt);
2928 BIC_PRESENT(BIC_RAMWatt);
2931 case INTEL_FAM6_HASWELL_X: /* HSX */
2932 case INTEL_FAM6_BROADWELL_X: /* BDX */
2933 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
2934 case INTEL_FAM6_SKYLAKE_X: /* SKX */
2935 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
2936 case INTEL_FAM6_XEON_PHI_KNM:
2937 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2938 BIC_PRESENT(BIC_PKG__);
2939 BIC_PRESENT(BIC_RAM__);
2941 BIC_PRESENT(BIC_Pkg_J);
2942 BIC_PRESENT(BIC_RAM_J);
2944 BIC_PRESENT(BIC_PkgWatt);
2945 BIC_PRESENT(BIC_RAMWatt);
2948 case INTEL_FAM6_SANDYBRIDGE_X:
2949 case INTEL_FAM6_IVYBRIDGE_X:
2950 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
2951 BIC_PRESENT(BIC_PKG__);
2952 BIC_PRESENT(BIC_RAM__);
2954 BIC_PRESENT(BIC_Pkg_J);
2955 BIC_PRESENT(BIC_Cor_J);
2956 BIC_PRESENT(BIC_RAM_J);
2958 BIC_PRESENT(BIC_PkgWatt);
2959 BIC_PRESENT(BIC_CorWatt);
2960 BIC_PRESENT(BIC_RAMWatt);
2963 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
2964 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
2965 do_rapl = RAPL_PKG | RAPL_CORES;
2967 BIC_PRESENT(BIC_Pkg_J);
2968 BIC_PRESENT(BIC_Cor_J);
2970 BIC_PRESENT(BIC_PkgWatt);
2971 BIC_PRESENT(BIC_CorWatt);
2974 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
2975 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO | RAPL_CORES_ENERGY_STATUS;
2976 BIC_PRESENT(BIC_PKG__);
2977 BIC_PRESENT(BIC_RAM__);
2979 BIC_PRESENT(BIC_Pkg_J);
2980 BIC_PRESENT(BIC_Cor_J);
2981 BIC_PRESENT(BIC_RAM_J);
2983 BIC_PRESENT(BIC_PkgWatt);
2984 BIC_PRESENT(BIC_CorWatt);
2985 BIC_PRESENT(BIC_RAMWatt);
2992 /* units on package 0, verify later other packages match */
2993 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
2996 rapl_power_units = 1.0 / (1 << (msr & 0xF));
2997 if (model == INTEL_FAM6_ATOM_SILVERMONT1)
2998 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
3000 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
3002 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
3004 time_unit = msr >> 16 & 0xF;
3008 rapl_time_units = 1.0 / (1 << (time_unit));
3010 tdp = get_tdp(model);
3012 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
3014 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
3019 void perf_limit_reasons_probe(unsigned int family, unsigned int model)
3028 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3029 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3030 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3031 do_gfx_perf_limit_reasons = 1;
3032 case INTEL_FAM6_HASWELL_X: /* HSX */
3033 do_core_perf_limit_reasons = 1;
3034 do_ring_perf_limit_reasons = 1;
3040 int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3042 unsigned long long msr;
3046 if (!(do_dts || do_ptm))
3051 /* DTS is per-core, no need to print for each thread */
3052 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
3055 if (cpu_migrate(cpu)) {
3056 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3060 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
3061 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
3064 dts = (msr >> 16) & 0x7F;
3065 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
3066 cpu, msr, tcc_activation_temp - dts);
3069 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
3072 dts = (msr >> 16) & 0x7F;
3073 dts2 = (msr >> 8) & 0x7F;
3074 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3075 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3081 unsigned int resolution;
3083 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
3086 dts = (msr >> 16) & 0x7F;
3087 resolution = (msr >> 27) & 0xF;
3088 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
3089 cpu, msr, tcc_activation_temp - dts, resolution);
3092 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
3095 dts = (msr >> 16) & 0x7F;
3096 dts2 = (msr >> 8) & 0x7F;
3097 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
3098 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
3105 void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
3107 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
3109 ((msr >> 15) & 1) ? "EN" : "DIS",
3110 ((msr >> 0) & 0x7FFF) * rapl_power_units,
3111 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
3112 (((msr >> 16) & 1) ? "EN" : "DIS"));
3117 int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3119 unsigned long long msr;
3125 /* RAPL counters are per package, so print only for 1st thread/package */
3126 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3130 if (cpu_migrate(cpu)) {
3131 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3135 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
3139 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
3140 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
3141 rapl_power_units, rapl_energy_units, rapl_time_units);
3143 if (do_rapl & RAPL_PKG_POWER_INFO) {
3145 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
3149 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3151 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3152 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3153 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3154 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3157 if (do_rapl & RAPL_PKG) {
3159 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
3162 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
3163 cpu, msr, (msr >> 63) & 1 ? "": "UN");
3165 print_power_limit_msr(cpu, msr, "PKG Limit #1");
3166 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
3168 ((msr >> 47) & 1) ? "EN" : "DIS",
3169 ((msr >> 32) & 0x7FFF) * rapl_power_units,
3170 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
3171 ((msr >> 48) & 1) ? "EN" : "DIS");
3174 if (do_rapl & RAPL_DRAM_POWER_INFO) {
3175 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
3178 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
3180 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3181 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3182 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
3183 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
3185 if (do_rapl & RAPL_DRAM) {
3186 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
3188 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
3189 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3191 print_power_limit_msr(cpu, msr, "DRAM Limit");
3193 if (do_rapl & RAPL_CORE_POLICY) {
3195 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
3198 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
3201 if (do_rapl & RAPL_CORES_POWER_LIMIT) {
3203 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
3205 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
3206 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3207 print_power_limit_msr(cpu, msr, "Cores Limit");
3210 if (do_rapl & RAPL_GFX) {
3212 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
3215 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
3217 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
3219 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
3220 cpu, msr, (msr >> 31) & 1 ? "": "UN");
3221 print_power_limit_msr(cpu, msr, "GFX Limit");
3228 * SNB adds support for additional MSRs:
3230 * MSR_PKG_C7_RESIDENCY 0x000003fa
3231 * MSR_CORE_C7_RESIDENCY 0x000003fe
3232 * MSR_PKG_C2_RESIDENCY 0x0000060d
3235 int has_snb_msrs(unsigned int family, unsigned int model)
3241 case INTEL_FAM6_SANDYBRIDGE:
3242 case INTEL_FAM6_SANDYBRIDGE_X:
3243 case INTEL_FAM6_IVYBRIDGE: /* IVB */
3244 case INTEL_FAM6_IVYBRIDGE_X: /* IVB Xeon */
3245 case INTEL_FAM6_HASWELL_CORE: /* HSW */
3246 case INTEL_FAM6_HASWELL_X: /* HSW */
3247 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3248 case INTEL_FAM6_HASWELL_GT3E: /* HSW */
3249 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3250 case INTEL_FAM6_BROADWELL_GT3E: /* BDW */
3251 case INTEL_FAM6_BROADWELL_X: /* BDX */
3252 case INTEL_FAM6_BROADWELL_XEON_D: /* BDX-DE */
3253 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3254 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3255 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3256 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3257 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3258 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3259 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3266 * SLV client has supporet for unique MSRs:
3268 * MSR_CC6_DEMOTION_POLICY_CONFIG
3269 * MSR_MC6_DEMOTION_POLICY_CONFIG
3272 int has_slv_msrs(unsigned int family, unsigned int model)
3278 case INTEL_FAM6_ATOM_SILVERMONT1:
3279 case INTEL_FAM6_ATOM_MERRIFIELD:
3280 case INTEL_FAM6_ATOM_MOOREFIELD:
3287 * HSW adds support for additional MSRs:
3289 * MSR_PKG_C8_RESIDENCY 0x00000630
3290 * MSR_PKG_C9_RESIDENCY 0x00000631
3291 * MSR_PKG_C10_RESIDENCY 0x00000632
3293 * MSR_PKGC8_IRTL 0x00000633
3294 * MSR_PKGC9_IRTL 0x00000634
3295 * MSR_PKGC10_IRTL 0x00000635
3298 int has_hsw_msrs(unsigned int family, unsigned int model)
3304 case INTEL_FAM6_HASWELL_ULT: /* HSW */
3305 case INTEL_FAM6_BROADWELL_CORE: /* BDW */
3306 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3307 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3308 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3309 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3310 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3317 * SKL adds support for additional MSRS:
3319 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
3320 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
3321 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
3322 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
3324 int has_skl_msrs(unsigned int family, unsigned int model)
3330 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3331 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3332 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3333 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3341 int is_slm(unsigned int family, unsigned int model)
3346 case INTEL_FAM6_ATOM_SILVERMONT1: /* BYT */
3347 case INTEL_FAM6_ATOM_SILVERMONT2: /* AVN */
3353 int is_knl(unsigned int family, unsigned int model)
3358 case INTEL_FAM6_XEON_PHI_KNL: /* KNL */
3359 case INTEL_FAM6_XEON_PHI_KNM:
3365 unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
3367 if (is_knl(family, model))
3372 #define SLM_BCLK_FREQS 5
3373 double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
3375 double slm_bclk(void)
3377 unsigned long long msr = 3;
3381 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
3382 fprintf(outf, "SLM BCLK: unknown\n");
3385 if (i >= SLM_BCLK_FREQS) {
3386 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
3389 freq = slm_freq_table[i];
3392 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
3397 double discover_bclk(unsigned int family, unsigned int model)
3399 if (has_snb_msrs(family, model) || is_knl(family, model))
3401 else if (is_slm(family, model))
3408 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
3409 * the Thermal Control Circuit (TCC) activates.
3410 * This is usually equal to tjMax.
3412 * Older processors do not have this MSR, so there we guess,
3413 * but also allow cmdline over-ride with -T.
3415 * Several MSR temperature values are in units of degrees-C
3416 * below this value, including the Digital Thermal Sensor (DTS),
3417 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
3419 int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
3421 unsigned long long msr;
3422 unsigned int target_c_local;
3425 /* tcc_activation_temp is used only for dts or ptm */
3426 if (!(do_dts || do_ptm))
3429 /* this is a per-package concept */
3430 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
3434 if (cpu_migrate(cpu)) {
3435 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3439 if (tcc_activation_temp_override != 0) {
3440 tcc_activation_temp = tcc_activation_temp_override;
3441 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
3442 cpu, tcc_activation_temp);
3446 /* Temperature Target MSR is Nehalem and newer only */
3447 if (!do_nhm_platform_info)
3450 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
3453 target_c_local = (msr >> 16) & 0xFF;
3456 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
3457 cpu, msr, target_c_local);
3459 if (!target_c_local)
3462 tcc_activation_temp = target_c_local;
3467 tcc_activation_temp = TJMAX_DEFAULT;
3468 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
3469 cpu, tcc_activation_temp);
3474 void decode_feature_control_msr(void)
3476 unsigned long long msr;
3478 if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr))
3479 fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n",
3481 msr & FEATURE_CONTROL_LOCKED ? "" : "UN-",
3482 msr & (1 << 18) ? "SGX" : "");
3485 void decode_misc_enable_msr(void)
3487 unsigned long long msr;
3489 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
3490 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
3492 msr & (1 << 3) ? "TCC" : "",
3493 msr & (1 << 16) ? "EIST" : "",
3494 msr & (1 << 18) ? "MONITOR" : "");
3498 * Decode MSR_MISC_PWR_MGMT
3500 * Decode the bits according to the Nehalem documentation
3501 * bit[0] seems to continue to have same meaning going forward
3504 void decode_misc_pwr_mgmt_msr(void)
3506 unsigned long long msr;
3508 if (!do_nhm_platform_info)
3511 if (no_MSR_MISC_PWR_MGMT)
3514 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
3515 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB %sable-OOB)\n",
3517 msr & (1 << 0) ? "DIS" : "EN",
3518 msr & (1 << 1) ? "EN" : "DIS",
3519 msr & (1 << 8) ? "EN" : "DIS");
3522 * Decode MSR_CC6_DEMOTION_POLICY_CONFIG, MSR_MC6_DEMOTION_POLICY_CONFIG
3524 * This MSRs are present on Silvermont processors,
3525 * Intel Atom processor E3000 series (Baytrail), and friends.
3527 void decode_c6_demotion_policy_msr(void)
3529 unsigned long long msr;
3531 if (!get_msr(base_cpu, MSR_CC6_DEMOTION_POLICY_CONFIG, &msr))
3532 fprintf(outf, "cpu%d: MSR_CC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-CC6-Demotion)\n",
3533 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3535 if (!get_msr(base_cpu, MSR_MC6_DEMOTION_POLICY_CONFIG, &msr))
3536 fprintf(outf, "cpu%d: MSR_MC6_DEMOTION_POLICY_CONFIG: 0x%08llx (%sable-MC6-Demotion)\n",
3537 base_cpu, msr, msr & (1 << 0) ? "EN" : "DIS");
3540 void process_cpuid()
3542 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
3543 unsigned int fms, family, model, stepping;
3545 eax = ebx = ecx = edx = 0;
3547 __cpuid(0, max_level, ebx, ecx, edx);
3549 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
3553 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
3554 (char *)&ebx, (char *)&edx, (char *)&ecx);
3556 __cpuid(1, fms, ebx, ecx, edx);
3557 family = (fms >> 8) & 0xf;
3558 model = (fms >> 4) & 0xf;
3559 stepping = fms & 0xf;
3560 if (family == 6 || family == 0xf)
3561 model += ((fms >> 16) & 0xf) << 4;
3564 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
3565 max_level, family, model, stepping, family, model, stepping);
3566 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n",
3567 ecx & (1 << 0) ? "SSE3" : "-",
3568 ecx & (1 << 3) ? "MONITOR" : "-",
3569 ecx & (1 << 6) ? "SMX" : "-",
3570 ecx & (1 << 7) ? "EIST" : "-",
3571 ecx & (1 << 8) ? "TM2" : "-",
3572 edx & (1 << 4) ? "TSC" : "-",
3573 edx & (1 << 5) ? "MSR" : "-",
3574 edx & (1 << 22) ? "ACPI-TM" : "-",
3575 edx & (1 << 29) ? "TM" : "-");
3578 if (!(edx & (1 << 5)))
3579 errx(1, "CPUID: no MSR");
3582 * check max extended function levels of CPUID.
3583 * This is needed to check for invariant TSC.
3584 * This check is valid for both Intel and AMD.
3586 ebx = ecx = edx = 0;
3587 __cpuid(0x80000000, max_extended_level, ebx, ecx, edx);
3589 if (max_extended_level >= 0x80000007) {
3592 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
3593 * this check is valid for both Intel and AMD
3595 __cpuid(0x80000007, eax, ebx, ecx, edx);
3596 has_invariant_tsc = edx & (1 << 8);
3600 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
3601 * this check is valid for both Intel and AMD
3604 __cpuid(0x6, eax, ebx, ecx, edx);
3605 has_aperf = ecx & (1 << 0);
3607 BIC_PRESENT(BIC_Avg_MHz);
3608 BIC_PRESENT(BIC_Busy);
3609 BIC_PRESENT(BIC_Bzy_MHz);
3611 do_dts = eax & (1 << 0);
3613 BIC_PRESENT(BIC_CoreTmp);
3614 do_ptm = eax & (1 << 6);
3616 BIC_PRESENT(BIC_PkgTmp);
3617 has_hwp = eax & (1 << 7);
3618 has_hwp_notify = eax & (1 << 8);
3619 has_hwp_activity_window = eax & (1 << 9);
3620 has_hwp_epp = eax & (1 << 10);
3621 has_hwp_pkg = eax & (1 << 11);
3622 has_epb = ecx & (1 << 3);
3625 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
3626 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
3627 has_aperf ? "" : "No-",
3628 do_dts ? "" : "No-",
3629 do_ptm ? "" : "No-",
3630 has_hwp ? "" : "No-",
3631 has_hwp_notify ? "" : "No-",
3632 has_hwp_activity_window ? "" : "No-",
3633 has_hwp_epp ? "" : "No-",
3634 has_hwp_pkg ? "" : "No-",
3635 has_epb ? "" : "No-");
3638 decode_misc_enable_msr();
3640 if (max_level >= 0x7 && debug) {
3645 __cpuid_count(0x7, 0, eax, ebx, ecx, edx);
3647 has_sgx = ebx & (1 << 2);
3648 fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-");
3651 decode_feature_control_msr();
3654 if (max_level >= 0x15) {
3655 unsigned int eax_crystal;
3656 unsigned int ebx_tsc;
3659 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
3661 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
3662 __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx);
3666 if (debug && (ebx != 0))
3667 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
3668 eax_crystal, ebx_tsc, crystal_hz);
3670 if (crystal_hz == 0)
3672 case INTEL_FAM6_SKYLAKE_MOBILE: /* SKL */
3673 case INTEL_FAM6_SKYLAKE_DESKTOP: /* SKL */
3674 case INTEL_FAM6_KABYLAKE_MOBILE: /* KBL */
3675 case INTEL_FAM6_KABYLAKE_DESKTOP: /* KBL */
3676 crystal_hz = 24000000; /* 24.0 MHz */
3678 case INTEL_FAM6_SKYLAKE_X: /* SKX */
3679 case INTEL_FAM6_ATOM_DENVERTON: /* DNV */
3680 crystal_hz = 25000000; /* 25.0 MHz */
3682 case INTEL_FAM6_ATOM_GOLDMONT: /* BXT */
3683 crystal_hz = 19200000; /* 19.2 MHz */
3690 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
3692 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
3693 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
3697 if (max_level >= 0x16) {
3698 unsigned int base_mhz, max_mhz, bus_mhz, edx;
3701 * CPUID 16H Base MHz, Max MHz, Bus MHz
3703 base_mhz = max_mhz = bus_mhz = edx = 0;
3705 __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx);
3707 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
3708 base_mhz, max_mhz, bus_mhz);
3712 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
3714 BIC_PRESENT(BIC_IRQ);
3715 BIC_PRESENT(BIC_TSC_MHz);
3717 if (probe_nhm_msrs(family, model)) {
3718 do_nhm_platform_info = 1;
3719 BIC_PRESENT(BIC_CPU_c1);
3720 BIC_PRESENT(BIC_CPU_c3);
3721 BIC_PRESENT(BIC_CPU_c6);
3722 BIC_PRESENT(BIC_SMI);
3724 do_snb_cstates = has_snb_msrs(family, model);
3727 BIC_PRESENT(BIC_CPU_c7);
3729 do_irtl_snb = has_snb_msrs(family, model);
3730 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
3731 do_pc3 = (pkg_cstate_limit >= PCL__3);
3732 do_pc6 = (pkg_cstate_limit >= PCL__6);
3733 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
3734 do_c8_c9_c10 = has_hsw_msrs(family, model);
3735 do_irtl_hsw = has_hsw_msrs(family, model);
3736 do_skl_residency = has_skl_msrs(family, model);
3737 do_slm_cstates = is_slm(family, model);
3738 do_knl_cstates = is_knl(family, model);
3741 decode_misc_pwr_mgmt_msr();
3743 if (debug && has_slv_msrs(family, model))
3744 decode_c6_demotion_policy_msr();
3746 rapl_probe(family, model);
3747 perf_limit_reasons_probe(family, model);
3750 dump_cstate_pstate_config_info(family, model);
3752 if (has_skl_msrs(family, model))
3753 calculate_tsc_tweak();
3755 if (!access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK))
3756 BIC_PRESENT(BIC_GFX_rc6);
3758 if (!access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK))
3759 BIC_PRESENT(BIC_GFXMHz);
3767 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
3769 "Turbostat forks the specified COMMAND and prints statistics\n"
3770 "when COMMAND completes.\n"
3771 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
3772 "to print statistics, until interrupted.\n"
3773 "--add add a counter\n"
3774 " eg. --add msr0x10,u64,cpu,delta,MY_TSC\n"
3775 "--debug run in \"debug\" mode\n"
3776 "--interval sec Override default 5-second measurement interval\n"
3777 "--help print this help message\n"
3778 "--out file create or truncate \"file\" for all output\n"
3779 "--version print version information\n"
3781 "For more help, run \"man turbostat\"\n");
3786 * in /dev/cpu/ return success for names that are numbers
3787 * ie. filter out ".", "..", "microcode".
3789 int dir_filter(const struct dirent *dirp)
3791 if (isdigit(dirp->d_name[0]))
3797 int open_dev_cpu_msr(int dummy1)
3802 void topology_probe()
3805 int max_core_id = 0;
3806 int max_package_id = 0;
3807 int max_siblings = 0;
3808 struct cpu_topology {
3810 int physical_package_id;
3813 /* Initialize num_cpus, max_cpu_num */
3815 topo.max_cpu_num = 0;
3816 for_all_proc_cpus(count_cpus);
3817 if (!summary_only && topo.num_cpus > 1)
3818 BIC_PRESENT(BIC_CPU);
3821 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
3823 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
3825 err(1, "calloc cpus");
3828 * Allocate and initialize cpu_present_set
3830 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
3831 if (cpu_present_set == NULL)
3832 err(3, "CPU_ALLOC");
3833 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3834 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3835 for_all_proc_cpus(mark_cpu_present);
3838 * Allocate and initialize cpu_affinity_set
3840 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
3841 if (cpu_affinity_set == NULL)
3842 err(3, "CPU_ALLOC");
3843 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3844 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3849 * find max_core_id, max_package_id
3851 for (i = 0; i <= topo.max_cpu_num; ++i) {
3854 if (cpu_is_not_present(i)) {
3856 fprintf(outf, "cpu%d NOT PRESENT\n", i);
3859 cpus[i].core_id = get_core_id(i);
3860 if (cpus[i].core_id > max_core_id)
3861 max_core_id = cpus[i].core_id;
3863 cpus[i].physical_package_id = get_physical_package_id(i);
3864 if (cpus[i].physical_package_id > max_package_id)
3865 max_package_id = cpus[i].physical_package_id;
3867 siblings = get_num_ht_siblings(i);
3868 if (siblings > max_siblings)
3869 max_siblings = siblings;
3871 fprintf(outf, "cpu %d pkg %d core %d\n",
3872 i, cpus[i].physical_package_id, cpus[i].core_id);
3874 topo.num_cores_per_pkg = max_core_id + 1;
3876 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
3877 max_core_id, topo.num_cores_per_pkg);
3878 if (debug && !summary_only && topo.num_cores_per_pkg > 1)
3879 BIC_PRESENT(BIC_Core);
3881 topo.num_packages = max_package_id + 1;
3883 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
3884 max_package_id, topo.num_packages);
3885 if (debug && !summary_only && topo.num_packages > 1)
3886 BIC_PRESENT(BIC_Package);
3888 topo.num_threads_per_core = max_siblings;
3890 fprintf(outf, "max_siblings %d\n", max_siblings);
3896 allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3900 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
3901 topo.num_packages, sizeof(struct thread_data));
3905 for (i = 0; i < topo.num_threads_per_core *
3906 topo.num_cores_per_pkg * topo.num_packages; i++)
3907 (*t)[i].cpu_id = -1;
3909 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
3910 sizeof(struct core_data));
3914 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
3915 (*c)[i].core_id = -1;
3917 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
3921 for (i = 0; i < topo.num_packages; i++)
3922 (*p)[i].package_id = i;
3926 err(1, "calloc counters");
3931 * set cpu_id, core_num, pkg_num
3932 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
3934 * increment topo.num_cores when 1st core in pkg seen
3936 void init_counter(struct thread_data *thread_base, struct core_data *core_base,
3937 struct pkg_data *pkg_base, int thread_num, int core_num,
3938 int pkg_num, int cpu_id)
3940 struct thread_data *t;
3941 struct core_data *c;
3944 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
3945 c = GET_CORE(core_base, core_num, pkg_num);
3946 p = GET_PKG(pkg_base, pkg_num);
3949 if (thread_num == 0) {
3950 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
3951 if (cpu_is_first_core_in_package(cpu_id))
3952 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
3955 c->core_id = core_num;
3956 p->package_id = pkg_num;
3960 int initialize_counters(int cpu_id)
3962 int my_thread_id, my_core_id, my_package_id;
3964 my_package_id = get_physical_package_id(cpu_id);
3965 my_core_id = get_core_id(cpu_id);
3966 my_thread_id = get_cpu_position_in_core(cpu_id);
3970 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3971 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3975 void allocate_output_buffer()
3977 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
3978 outp = output_buffer;
3980 err(-1, "calloc output buffer");
3982 void allocate_fd_percpu(void)
3984 fd_percpu = calloc(topo.max_cpu_num + 1, sizeof(int));
3985 if (fd_percpu == NULL)
3986 err(-1, "calloc fd_percpu");
3988 void allocate_irq_buffers(void)
3990 irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int));
3991 if (irq_column_2_cpu == NULL)
3992 err(-1, "calloc %d", topo.num_cpus);
3994 irqs_per_cpu = calloc(topo.max_cpu_num + 1, sizeof(int));
3995 if (irqs_per_cpu == NULL)
3996 err(-1, "calloc %d", topo.max_cpu_num + 1);
3998 void setup_all_buffers(void)
4001 allocate_irq_buffers();
4002 allocate_fd_percpu();
4003 allocate_counters(&thread_even, &core_even, &package_even);
4004 allocate_counters(&thread_odd, &core_odd, &package_odd);
4005 allocate_output_buffer();
4006 for_all_proc_cpus(initialize_counters);
4009 void set_base_cpu(void)
4011 base_cpu = sched_getcpu();
4013 err(-ENODEV, "No valid cpus found");
4016 fprintf(outf, "base_cpu = %d\n", base_cpu);
4019 void turbostat_init()
4021 setup_all_buffers();
4024 check_permissions();
4029 for_all_cpus(print_hwp, ODD_COUNTERS);
4032 for_all_cpus(print_epb, ODD_COUNTERS);
4035 for_all_cpus(print_perf_limit, ODD_COUNTERS);
4038 for_all_cpus(print_rapl, ODD_COUNTERS);
4040 for_all_cpus(set_temperature_target, ODD_COUNTERS);
4043 for_all_cpus(print_thermal, ODD_COUNTERS);
4045 if (debug && do_irtl_snb)
4049 int fork_it(char **argv)
4054 status = for_all_cpus(get_counters, EVEN_COUNTERS);
4057 /* clear affinity side-effect of get_counters() */
4058 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
4059 gettimeofday(&tv_even, (struct timezone *)NULL);
4064 execvp(argv[0], argv);
4068 if (child_pid == -1)
4071 signal(SIGINT, SIG_IGN);
4072 signal(SIGQUIT, SIG_IGN);
4073 if (waitpid(child_pid, &status, 0) == -1)
4074 err(status, "waitpid");
4077 * n.b. fork_it() does not check for errors from for_all_cpus()
4078 * because re-starting is problematic when forking
4080 for_all_cpus(get_counters, ODD_COUNTERS);
4081 gettimeofday(&tv_odd, (struct timezone *)NULL);
4082 timersub(&tv_odd, &tv_even, &tv_delta);
4083 if (for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS))
4084 fprintf(outf, "%s: Counter reset detected\n", progname);
4086 compute_average(EVEN_COUNTERS);
4087 format_all_counters(EVEN_COUNTERS);
4090 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
4092 flush_output_stderr();
4097 int get_and_dump_counters(void)
4101 status = for_all_cpus(get_counters, ODD_COUNTERS);
4105 status = for_all_cpus(dump_counters, ODD_COUNTERS);
4109 flush_output_stdout();
4114 void print_version() {
4115 fprintf(outf, "turbostat version 4.17 1 Jan 2017"
4116 " - Len Brown <lenb@kernel.org>\n");
4119 int add_counter(unsigned int msr_num, char *name, unsigned int width,
4120 enum counter_scope scope, enum counter_type type,
4121 enum counter_format format)
4123 struct msr_counter *msrp;
4125 msrp = calloc(1, sizeof(struct msr_counter));
4131 msrp->msr_num = msr_num;
4132 strncpy(msrp->name, name, NAME_BYTES);
4133 msrp->width = width;
4135 msrp->format = format;
4140 msrp->next = sys.tp;
4142 sys.added_thread_counters++;
4143 if (sys.added_thread_counters > MAX_ADDED_COUNTERS) {
4144 fprintf(stderr, "exceeded max %d added thread counters\n",
4145 MAX_ADDED_COUNTERS);
4151 msrp->next = sys.cp;
4153 sys.added_core_counters++;
4154 if (sys.added_core_counters > MAX_ADDED_COUNTERS) {
4155 fprintf(stderr, "exceeded max %d added core counters\n",
4156 MAX_ADDED_COUNTERS);
4162 msrp->next = sys.pp;
4164 sys.added_package_counters++;
4165 if (sys.added_package_counters > MAX_ADDED_COUNTERS) {
4166 fprintf(stderr, "exceeded max %d added package counters\n",
4167 MAX_ADDED_COUNTERS);
4176 void parse_add_command(char *add_command)
4179 char name_buffer[NAME_BYTES];
4182 enum counter_scope scope = SCOPE_CPU;
4183 enum counter_type type = COUNTER_CYCLES;
4184 enum counter_format format = FORMAT_DELTA;
4186 while (add_command) {
4188 if (sscanf(add_command, "msr0x%x", &msr_num) == 1)
4191 if (sscanf(add_command, "msr%d", &msr_num) == 1)
4194 if (sscanf(add_command, "u%d", &width) == 1) {
4195 if ((width == 32) || (width == 64))
4199 if (!strncmp(add_command, "cpu", strlen("cpu"))) {
4203 if (!strncmp(add_command, "core", strlen("core"))) {
4207 if (!strncmp(add_command, "package", strlen("package"))) {
4208 scope = SCOPE_PACKAGE;
4211 if (!strncmp(add_command, "cycles", strlen("cycles"))) {
4212 type = COUNTER_CYCLES;
4215 if (!strncmp(add_command, "seconds", strlen("seconds"))) {
4216 type = COUNTER_SECONDS;
4219 if (!strncmp(add_command, "raw", strlen("raw"))) {
4220 format = FORMAT_RAW;
4223 if (!strncmp(add_command, "delta", strlen("delta"))) {
4224 format = FORMAT_DELTA;
4227 if (!strncmp(add_command, "percent", strlen("percent"))) {
4228 format = FORMAT_PERCENT;
4232 if (sscanf(add_command, "%18s,%*s", name_buffer) == 1) { /* 18 < NAME_BYTES */
4235 eos = strchr(name_buffer, ',');
4242 add_command = strchr(add_command, ',');
4248 fprintf(stderr, "--add: (msrDDD | msr0xXXX) required\n");
4252 /* generate default column header */
4253 if (*name_buffer == '\0') {
4254 if (format == FORMAT_RAW) {
4256 sprintf(name_buffer, "msr%d", msr_num);
4258 sprintf(name_buffer, "MSR%d", msr_num);
4259 } else if (format == FORMAT_DELTA) {
4261 sprintf(name_buffer, "cnt%d", msr_num);
4263 sprintf(name_buffer, "CNT%d", msr_num);
4264 } else if (format == FORMAT_PERCENT) {
4266 sprintf(name_buffer, "msr%d%%", msr_num);
4268 sprintf(name_buffer, "MSR%d%%", msr_num);
4272 if (add_counter(msr_num, name_buffer, width, scope, type, format))
4281 * HIDE_LIST - hide this list of counters, show the rest [default]
4282 * SHOW_LIST - show this list of counters, hide the rest
4284 enum show_hide_mode { SHOW_LIST, HIDE_LIST } global_show_hide_mode = HIDE_LIST;
4288 * parse_show_hide() - process cmdline to set default counter action
4290 void parse_show_hide(char *optarg, enum show_hide_mode new_mode)
4293 * --show: show only those specified
4294 * The 1st invocation will clear and replace the enabled mask
4295 * subsequent invocations can add to it.
4297 if (new_mode == SHOW_LIST) {
4299 bic_enabled = bic_lookup(optarg);
4301 bic_enabled |= bic_lookup(optarg);
4308 * --hide: do not show those specified
4309 * multiple invocations simply clear more bits in enabled mask
4311 bic_enabled &= ~bic_lookup(optarg);
4314 void cmdline(int argc, char **argv)
4317 int option_index = 0;
4318 static struct option long_options[] = {
4319 {"add", required_argument, 0, 'a'},
4320 {"Dump", no_argument, 0, 'D'},
4321 {"debug", no_argument, 0, 'd'},
4322 {"interval", required_argument, 0, 'i'},
4323 {"help", no_argument, 0, 'h'},
4324 {"hide", required_argument, 0, 'H'}, // meh, -h taken by --help
4325 {"Joules", no_argument, 0, 'J'},
4326 {"out", required_argument, 0, 'o'},
4327 {"Package", no_argument, 0, 'p'},
4328 {"processor", no_argument, 0, 'p'},
4329 {"show", required_argument, 0, 's'},
4330 {"Summary", no_argument, 0, 'S'},
4331 {"TCC", required_argument, 0, 'T'},
4332 {"version", no_argument, 0, 'v' },
4338 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
4339 long_options, &option_index)) != -1) {
4342 parse_add_command(optarg);
4351 parse_show_hide(optarg, HIDE_LIST);
4359 double interval = strtod(optarg, NULL);
4361 if (interval < 0.001) {
4362 fprintf(outf, "interval %f seconds is too small\n",
4367 interval_ts.tv_sec = interval;
4368 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
4375 outf = fopen_or_die(optarg, "w");
4384 parse_show_hide(optarg, SHOW_LIST);
4390 tcc_activation_temp_override = atoi(optarg);
4400 int main(int argc, char **argv)
4404 cmdline(argc, argv);
4411 /* dump counters and exit */
4413 return get_and_dump_counters();
4416 * if any params left, it must be a command to fork
4419 return fork_it(argv + optind);