3 "PublicDescription": "Counts cycles the IDQ is empty.",
7 "EventName": "IDQ.EMPTY",
8 "SampleAfterValue": "2000003",
9 "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
10 "CounterHTOff": "0,1,2,3"
13 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MITE path. Set Cmask = 1 to count cycles.",
17 "EventName": "IDQ.MITE_UOPS",
18 "SampleAfterValue": "2000003",
19 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
20 "CounterHTOff": "0,1,2,3,4,5,6,7"
23 "PublicDescription": "Increment each cycle. # of uops delivered to IDQ from DSB path. Set Cmask = 1 to count cycles.",
27 "EventName": "IDQ.DSB_UOPS",
28 "SampleAfterValue": "2000003",
29 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
30 "CounterHTOff": "0,1,2,3,4,5,6,7"
33 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by DSB. Set Cmask = 1 to count cycles. Add Edge=1 to count # of delivery.",
37 "EventName": "IDQ.MS_DSB_UOPS",
38 "SampleAfterValue": "2000003",
39 "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
40 "CounterHTOff": "0,1,2,3,4,5,6,7"
43 "PublicDescription": "Increment each cycle # of uops delivered to IDQ when MS_busy by MITE. Set Cmask = 1 to count cycles.",
47 "EventName": "IDQ.MS_MITE_UOPS",
48 "SampleAfterValue": "2000003",
49 "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
50 "CounterHTOff": "0,1,2,3,4,5,6,7"
53 "PublicDescription": "Increment each cycle # of uops delivered to IDQ from MS by either DSB or MITE. Set Cmask = 1 to count cycles.",
57 "EventName": "IDQ.MS_UOPS",
58 "SampleAfterValue": "2000003",
59 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
60 "CounterHTOff": "0,1,2,3,4,5,6,7"
63 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
67 "EventName": "IDQ.MS_CYCLES",
68 "SampleAfterValue": "2000003",
69 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
71 "CounterHTOff": "0,1,2,3,4,5,6,7"
74 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path.",
78 "EventName": "IDQ.MITE_CYCLES",
79 "SampleAfterValue": "2000003",
80 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
82 "CounterHTOff": "0,1,2,3,4,5,6,7"
85 "PublicDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.",
89 "EventName": "IDQ.DSB_CYCLES",
90 "SampleAfterValue": "2000003",
91 "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
93 "CounterHTOff": "0,1,2,3,4,5,6,7"
96 "PublicDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy.",
100 "EventName": "IDQ.MS_DSB_CYCLES",
101 "SampleAfterValue": "2000003",
102 "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
104 "CounterHTOff": "0,1,2,3,4,5,6,7"
107 "PublicDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy.",
109 "Counter": "0,1,2,3",
112 "EventName": "IDQ.MS_DSB_OCCUR",
113 "SampleAfterValue": "2000003",
114 "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
116 "CounterHTOff": "0,1,2,3,4,5,6,7"
119 "PublicDescription": "Counts cycles DSB is delivered four uops. Set Cmask = 4.",
121 "Counter": "0,1,2,3",
123 "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
124 "SampleAfterValue": "2000003",
125 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
127 "CounterHTOff": "0,1,2,3,4,5,6,7"
130 "PublicDescription": "Counts cycles DSB is delivered at least one uops. Set Cmask = 1.",
132 "Counter": "0,1,2,3",
134 "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
135 "SampleAfterValue": "2000003",
136 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
138 "CounterHTOff": "0,1,2,3,4,5,6,7"
141 "PublicDescription": "Counts cycles MITE is delivered four uops. Set Cmask = 4.",
143 "Counter": "0,1,2,3",
145 "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
146 "SampleAfterValue": "2000003",
147 "BriefDescription": "Cycles MITE is delivering 4 Uops",
149 "CounterHTOff": "0,1,2,3,4,5,6,7"
152 "PublicDescription": "Counts cycles MITE is delivered at least one uops. Set Cmask = 1.",
154 "Counter": "0,1,2,3",
156 "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
157 "SampleAfterValue": "2000003",
158 "BriefDescription": "Cycles MITE is delivering any Uop",
160 "CounterHTOff": "0,1,2,3,4,5,6,7"
163 "PublicDescription": "Number of uops delivered to IDQ from any path.",
165 "Counter": "0,1,2,3",
167 "EventName": "IDQ.MITE_ALL_UOPS",
168 "SampleAfterValue": "2000003",
169 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
170 "CounterHTOff": "0,1,2,3,4,5,6,7"
173 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches.",
175 "Counter": "0,1,2,3",
177 "EventName": "ICACHE.HIT",
178 "SampleAfterValue": "2000003",
179 "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
180 "CounterHTOff": "0,1,2,3,4,5,6,7"
183 "PublicDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes UC accesses.",
185 "Counter": "0,1,2,3",
187 "EventName": "ICACHE.MISSES",
188 "SampleAfterValue": "200003",
189 "BriefDescription": "Instruction cache, streaming buffer and victim cache misses",
190 "CounterHTOff": "0,1,2,3,4,5,6,7"
193 "PublicDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss.",
195 "Counter": "0,1,2,3",
197 "EventName": "ICACHE.IFETCH_STALL",
198 "SampleAfterValue": "2000003",
199 "BriefDescription": "Cycles where a code-fetch stalled due to L1 instruction-cache miss or an iTLB miss",
200 "CounterHTOff": "0,1,2,3,4,5,6,7"
203 "PublicDescription": "Count issue pipeline slots where no uop was delivered from the front end to the back end when there is no back-end stall.",
205 "Counter": "0,1,2,3",
207 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
208 "SampleAfterValue": "2000003",
209 "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled ",
210 "CounterHTOff": "0,1,2,3"
214 "Counter": "0,1,2,3",
216 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
217 "SampleAfterValue": "2000003",
218 "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
220 "CounterHTOff": "0,1,2,3"
224 "Counter": "0,1,2,3",
226 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
227 "SampleAfterValue": "2000003",
228 "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled.",
230 "CounterHTOff": "0,1,2,3"
234 "Counter": "0,1,2,3",
236 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
237 "SampleAfterValue": "2000003",
238 "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
240 "CounterHTOff": "0,1,2,3"
244 "Counter": "0,1,2,3",
246 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
247 "SampleAfterValue": "2000003",
248 "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
250 "CounterHTOff": "0,1,2,3"
255 "Counter": "0,1,2,3",
257 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
258 "SampleAfterValue": "2000003",
259 "BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
261 "CounterHTOff": "0,1,2,3"
264 "PublicDescription": "Number of DSB to MITE switches.",
266 "Counter": "0,1,2,3",
268 "EventName": "DSB2MITE_SWITCHES.COUNT",
269 "SampleAfterValue": "2000003",
270 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches",
271 "CounterHTOff": "0,1,2,3,4,5,6,7"
274 "PublicDescription": "Cycles DSB to MITE switches caused delay.",
276 "Counter": "0,1,2,3",
278 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
279 "SampleAfterValue": "2000003",
280 "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles",
281 "CounterHTOff": "0,1,2,3,4,5,6,7"
284 "PublicDescription": "DSB Fill encountered > 3 DSB lines.",
286 "Counter": "0,1,2,3",
288 "EventName": "DSB_FILL.EXCEED_DSB_LINES",
289 "SampleAfterValue": "2000003",
290 "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill encounter more than 3 Decode Stream Buffer (DSB) lines",
291 "CounterHTOff": "0,1,2,3,4,5,6,7"
294 "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
296 "Counter": "0,1,2,3",
299 "EventName": "IDQ.MS_SWITCHES",
300 "SampleAfterValue": "2000003",
301 "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer",
303 "CounterHTOff": "0,1,2,3,4,5,6,7"