tools/perf/pmu-events/arch/x86/amdzen3/recommended.json

   1 [
   2   {
   3     "MetricName": "branch_misprediction_ratio",
   4     "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
   5     "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
   6     "MetricGroup": "branch_prediction",
   7     "ScaleUnit": "100%"
   8   },
   9   {
  10     "EventName": "all_data_cache_accesses",
  11     "EventCode": "0x29",
  12     "BriefDescription": "All L1 Data Cache Accesses",
  13     "UMask": "0x07"
  14   },
  15   {
  16     "MetricName": "all_l2_cache_accesses",
  17     "BriefDescription": "All L2 Cache Accesses",
  18     "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
  19     "MetricGroup": "l2_cache"
  20   },
  21   {
  22     "EventName": "l2_cache_accesses_from_ic_misses",
  23     "EventCode": "0x60",
  24     "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
  25     "UMask": "0x10"
  26   },
  27   {
  28     "EventName": "l2_cache_accesses_from_dc_misses",
  29     "EventCode": "0x60",
  30     "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
  31     "UMask": "0xe8"
  32   },
  33   {
  34     "MetricName": "l2_cache_accesses_from_l2_hwpf",
  35     "BriefDescription": "L2 Cache Accesses from L2 HWPF",
  36     "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
  37     "MetricGroup": "l2_cache"
  38   },
  39   {
  40     "MetricName": "all_l2_cache_misses",
  41     "BriefDescription": "All L2 Cache Misses",
  42     "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
  43     "MetricGroup": "l2_cache"
  44   },
  45   {
  46     "EventName": "l2_cache_misses_from_ic_miss",
  47     "EventCode": "0x64",
  48     "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
  49     "UMask": "0x01"
  50   },
  51   {
  52     "EventName": "l2_cache_misses_from_dc_misses",
  53     "EventCode": "0x64",
  54     "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
  55     "UMask": "0x08"
  56   },
  57   {
  58     "MetricName": "l2_cache_misses_from_l2_hwpf",
  59     "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
  60     "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
  61     "MetricGroup": "l2_cache"
  62   },
  63   {
  64     "MetricName": "all_l2_cache_hits",
  65     "BriefDescription": "All L2 Cache Hits",
  66     "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
  67     "MetricGroup": "l2_cache"
  68   },
  69   {
  70     "EventName": "l2_cache_hits_from_ic_misses",
  71     "EventCode": "0x64",
  72     "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
  73     "UMask": "0x06"
  74   },
  75   {
  76     "EventName": "l2_cache_hits_from_dc_misses",
  77     "EventCode": "0x64",
  78     "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
  79     "UMask": "0xf0"
  80   },
  81   {
  82     "EventName": "l2_cache_hits_from_l2_hwpf",
  83     "EventCode": "0x70",
  84     "BriefDescription": "L2 Cache Hits from L2 Cache HWPF",
  85     "UMask": "0xff"
  86   },
  87   {
  88     "EventName": "l3_cache_accesses",
  89     "EventCode": "0x04",
  90     "BriefDescription": "L3 Cache Accesses",
  91     "UMask": "0xff",
  92     "Unit": "L3PMC"
  93   },
  94   {
  95     "EventName": "l3_misses",
  96     "EventCode": "0x04",
  97     "BriefDescription": "L3 Misses (includes cacheline state change requests)",
  98     "UMask": "0x01",
  99     "Unit": "L3PMC"
 100   },
 101   {
 102     "MetricName": "l3_read_miss_latency",
 103     "BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
 104     "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1",
 105     "MetricGroup": "l3_cache",
 106     "ScaleUnit": "1core clocks"
 107   },
 108   {
 109     "MetricName": "op_cache_fetch_miss_ratio",
 110     "BriefDescription": "Op Cache (64B) Fetch Miss Ratio",
 111     "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
 112     "MetricGroup": "l2_cache"
 113   },
 114   {
 115     "MetricName": "ic_fetch_miss_ratio",
 116     "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio",
 117     "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
 118     "MetricGroup": "l2_cache",
 119     "ScaleUnit": "100%"
 120   },
 121   {
 122     "EventName": "l1_data_cache_fills_from_memory",
 123     "EventCode": "0x44",
 124     "BriefDescription": "L1 Data Cache Fills: From Memory",
 125     "UMask": "0x48"
 126   },
 127   {
 128     "EventName": "l1_data_cache_fills_from_remote_node",
 129     "EventCode": "0x44",
 130     "BriefDescription": "L1 Data Cache Fills: From Remote Node",
 131     "UMask": "0x50"
 132   },
 133   {
 134     "EventName": "l1_data_cache_fills_from_within_same_ccx",
 135     "EventCode": "0x44",
 136     "BriefDescription": "L1 Data Cache Fills: From within same CCX",
 137     "UMask": "0x03"
 138   },
 139   {
 140     "EventName": "l1_data_cache_fills_from_external_ccx_cache",
 141     "EventCode": "0x44",
 142     "BriefDescription": "L1 Data Cache Fills: From External CCX Cache",
 143     "UMask": "0x14"
 144   },
 145   {
 146     "EventName": "l1_data_cache_fills_all",
 147     "EventCode": "0x44",
 148     "BriefDescription": "L1 Data Cache Fills: All",
 149     "UMask": "0xff"
 150   },
 151   {
 152     "MetricName": "l1_itlb_misses",
 153     "BriefDescription": "L1 ITLB Misses",
 154     "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss",
 155     "MetricGroup": "tlb"
 156   },
 157   {
 158     "EventName": "l2_itlb_misses",
 159     "EventCode": "0x85",
 160     "BriefDescription": "L2 ITLB Misses & Instruction page walks",
 161     "UMask": "0x07"
 162   },
 163   {
 164     "EventName": "l1_dtlb_misses",
 165     "EventCode": "0x45",
 166     "BriefDescription": "L1 DTLB Misses",
 167     "UMask": "0xff"
 168   },
 169   {
 170     "EventName": "l2_dtlb_misses",
 171     "EventCode": "0x45",
 172     "BriefDescription": "L2 DTLB Misses & Data page walks",
 173     "UMask": "0xf0"
 174   },
 175   {
 176     "EventName": "all_tlbs_flushed",
 177     "EventCode": "0x78",
 178     "BriefDescription": "All TLBs Flushed",
 179     "UMask": "0xff"
 180   },
 181   {
 182     "MetricName": "macro_ops_dispatched",
 183     "BriefDescription": "Macro-ops Dispatched",
 184     "MetricExpr": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch",
 185     "MetricGroup": "decoder"
 186   },
 187   {
 188     "EventName": "sse_avx_stalls",
 189     "EventCode": "0x0e",
 190     "BriefDescription": "Mixed SSE/AVX Stalls",
 191     "UMask": "0x0e"
 192   },
 193   {
 194     "EventName": "macro_ops_retired",
 195     "EventCode": "0xc1",
 196     "BriefDescription": "Macro-ops Retired"
 197   },
 198   {
 199     "MetricName": "all_remote_links_outbound",
 200     "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
 201     "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
 202     "MetricGroup": "data_fabric",
 203     "PerPkg": "1",
 204     "ScaleUnit": "3e-5MiB"
 205   },
 206   {
 207     "MetricName": "nps1_die_to_dram",
 208     "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
 209     "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
 210     "MetricGroup": "data_fabric",
 211     "PerPkg": "1",
 212     "ScaleUnit": "6.1e-5MiB"
 213   }
 214 ]