tools/perf/pmu-events/arch/arm64/arm/cortex-a65/instruction.json

   1 [
   2     {
   3         "ArchStdEvent": "SW_INCR"
   4     },
   5     {
   6         "ArchStdEvent": "LD_RETIRED"
   7     },
   8     {
   9         "ArchStdEvent": "ST_RETIRED"
  10     },
  11     {
  12         "ArchStdEvent": "INST_RETIRED"
  13     },
  14     {
  15         "ArchStdEvent": "EXC_RETURN"
  16     },
  17     {
  18         "ArchStdEvent": "CID_WRITE_RETIRED"
  19     },
  20     {
  21         "ArchStdEvent": "PC_WRITE_RETIRED"
  22     },
  23     {
  24         "ArchStdEvent": "BR_IMMED_RETIRED"
  25     },
  26     {
  27         "ArchStdEvent": "BR_RETURN_RETIRED"
  28     },
  29     {
  30         "ArchStdEvent": "INST_SPEC"
  31     },
  32     {
  33         "ArchStdEvent": "TTBR_WRITE_RETIRED"
  34     },
  35     {
  36         "ArchStdEvent": "BR_RETIRED"
  37     },
  38     {
  39         "ArchStdEvent": "BR_MIS_PRED_RETIRED"
  40     },
  41     {
  42         "ArchStdEvent": "LD_SPEC"
  43     },
  44     {
  45         "ArchStdEvent": "ST_SPEC"
  46     },
  47     {
  48         "ArchStdEvent": "LDST_SPEC"
  49     },
  50     {
  51         "ArchStdEvent": "DP_SPEC"
  52     },
  53     {
  54         "ArchStdEvent": "ASE_SPEC"
  55     },
  56     {
  57         "ArchStdEvent": "VFP_SPEC"
  58     },
  59     {
  60         "ArchStdEvent": "CRYPTO_SPEC"
  61     },
  62     {
  63         "ArchStdEvent": "ISB_SPEC"
  64     },
  65     {
  66         "PublicDescription": "Instruction retired, conditional branch",
  67         "EventCode": "0xE8",
  68         "EventName": "DPU_BR_COND_RETIRED",
  69         "BriefDescription": "Instruction retired, conditional branch"
  70     }
  71 ]