1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Socionext UniPhier AIO ALSA driver.
5 * Copyright (c) 2016-2018 Socionext Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #ifndef SND_UNIPHIER_AIO_REG_H__
22 #define SND_UNIPHIER_AIO_REG_H__
24 #include <linux/bitops.h>
27 #define SG_AOUTEN 0x1c04
30 #define A2CHNMAPCTR0(n) (0x00000 + 0x40 * (n))
31 #define A2RBNMAPCTR0(n) (0x01000 + 0x40 * (n))
32 #define A2IPORTNMAPCTR0(n) (0x02000 + 0x40 * (n))
33 #define A2IPORTNMAPCTR1(n) (0x02004 + 0x40 * (n))
34 #define A2IIFNMAPCTR0(n) (0x03000 + 0x40 * (n))
35 #define A2OPORTNMAPCTR0(n) (0x04000 + 0x40 * (n))
36 #define A2OPORTNMAPCTR1(n) (0x04004 + 0x40 * (n))
37 #define A2OPORTNMAPCTR2(n) (0x04008 + 0x40 * (n))
38 #define A2OIFNMAPCTR0(n) (0x05000 + 0x40 * (n))
39 #define A2ATNMAPCTR0(n) (0x06000 + 0x40 * (n))
41 #define MAPCTR0_EN 0x80000000
44 #define A2APLLCTR0 0x07000
45 #define A2APLLCTR0_APLLXPOW_MASK GENMASK(3, 0)
46 #define A2APLLCTR0_APLLXPOW_PWOFF (0x0 << 0)
47 #define A2APLLCTR0_APLLXPOW_PWON (0xf << 0)
48 #define A2APLLCTR1 0x07004
49 #define A2APLLCTR1_APLLX_MASK 0x00010101
50 #define A2APLLCTR1_APLLX_36MHZ 0x00000000
51 #define A2APLLCTR1_APLLX_33MHZ 0x00000001
52 #define A2EXMCLKSEL0 0x07030
53 #define A2EXMCLKSEL0_EXMCLK_MASK GENMASK(2, 0)
54 #define A2EXMCLKSEL0_EXMCLK_OUTPUT (0x0 << 0)
55 #define A2EXMCLKSEL0_EXMCLK_INPUT (0x7 << 0)
56 #define A2SSIFSW 0x07050
57 #define A2CH22_2CTR 0x07054
58 #define A2AIOINPUTSEL 0x070e0
59 #define A2AIOINPUTSEL_RXSEL_PCMI1_MASK GENMASK(2, 0)
60 #define A2AIOINPUTSEL_RXSEL_PCMI1_HDMIRX1 (0x2 << 0)
61 #define A2AIOINPUTSEL_RXSEL_PCMI2_MASK GENMASK(6, 4)
62 #define A2AIOINPUTSEL_RXSEL_PCMI2_SIF (0x7 << 4)
63 #define A2AIOINPUTSEL_RXSEL_PCMI3_MASK GENMASK(10, 8)
64 #define A2AIOINPUTSEL_RXSEL_PCMI3_EVEA (0x1 << 8)
65 #define A2AIOINPUTSEL_RXSEL_IECI1_MASK GENMASK(14, 12)
66 #define A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1 (0x2 << 12)
67 #define A2AIOINPUTSEL_RXSEL_MASK (A2AIOINPUTSEL_RXSEL_PCMI1_MASK | \
68 A2AIOINPUTSEL_RXSEL_PCMI2_MASK | \
69 A2AIOINPUTSEL_RXSEL_PCMI3_MASK | \
70 A2AIOINPUTSEL_RXSEL_IECI1_HDMIRX1)
73 #define INTCHIM(m) (0x9028 + 0x80 * (m))
74 #define INTRBIM(m) (0x9030 + 0x80 * (m))
75 #define INTCHID(m) (0xa028 + 0x80 * (m))
76 #define INTRBID(m) (0xa030 + 0x80 * (m))
79 #define IPORTMXCTR1(n) (0x22000 + 0x400 * (n))
80 #define IPORTMXCTR1_LRSEL_MASK GENMASK(11, 10)
81 #define IPORTMXCTR1_LRSEL_RIGHT (0x0 << 10)
82 #define IPORTMXCTR1_LRSEL_LEFT (0x1 << 10)
83 #define IPORTMXCTR1_LRSEL_I2S (0x2 << 10)
84 #define IPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8)
85 #define IPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8)
86 #define IPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8)
87 #define IPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8)
88 #define IPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8)
89 #define IPORTMXCTR1_CHSEL_MASK GENMASK(6, 4)
90 #define IPORTMXCTR1_CHSEL_ALL (0x0 << 4)
91 #define IPORTMXCTR1_CHSEL_D0_D2 (0x1 << 4)
92 #define IPORTMXCTR1_CHSEL_D0 (0x2 << 4)
93 #define IPORTMXCTR1_CHSEL_D1 (0x3 << 4)
94 #define IPORTMXCTR1_CHSEL_D2 (0x4 << 4)
95 #define IPORTMXCTR1_CHSEL_DMIX (0x5 << 4)
96 #define IPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)
97 #define IPORTMXCTR1_FSSEL_48 (0x0 << 0)
98 #define IPORTMXCTR1_FSSEL_96 (0x1 << 0)
99 #define IPORTMXCTR1_FSSEL_192 (0x2 << 0)
100 #define IPORTMXCTR1_FSSEL_32 (0x3 << 0)
101 #define IPORTMXCTR1_FSSEL_44_1 (0x4 << 0)
102 #define IPORTMXCTR1_FSSEL_88_2 (0x5 << 0)
103 #define IPORTMXCTR1_FSSEL_176_4 (0x6 << 0)
104 #define IPORTMXCTR1_FSSEL_16 (0x8 << 0)
105 #define IPORTMXCTR1_FSSEL_22_05 (0x9 << 0)
106 #define IPORTMXCTR1_FSSEL_24 (0xa << 0)
107 #define IPORTMXCTR1_FSSEL_8 (0xb << 0)
108 #define IPORTMXCTR1_FSSEL_11_025 (0xc << 0)
109 #define IPORTMXCTR1_FSSEL_12 (0xd << 0)
110 #define IPORTMXCTR2(n) (0x22004 + 0x400 * (n))
111 #define IPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)
112 #define IPORTMXCTR2_ACLKSEL_A1 (0x0 << 16)
113 #define IPORTMXCTR2_ACLKSEL_F1 (0x1 << 16)
114 #define IPORTMXCTR2_ACLKSEL_A2 (0x2 << 16)
115 #define IPORTMXCTR2_ACLKSEL_F2 (0x3 << 16)
116 #define IPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16)
117 #define IPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16)
118 #define IPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16)
119 #define IPORTMXCTR2_MSSEL_MASK BIT(15)
120 #define IPORTMXCTR2_MSSEL_SLAVE (0x0 << 15)
121 #define IPORTMXCTR2_MSSEL_MASTER (0x1 << 15)
122 #define IPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14)
123 #define IPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14)
124 #define IPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14)
125 #define IPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)
126 #define IPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8)
127 #define IPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8)
128 #define IPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8)
129 #define IPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8)
130 #define IPORTMXCTR2_REQEN_MASK BIT(0)
131 #define IPORTMXCTR2_REQEN_DISABLE (0x0 << 0)
132 #define IPORTMXCTR2_REQEN_ENABLE (0x1 << 0)
133 #define IPORTMXCNTCTR(n) (0x22010 + 0x400 * (n))
134 #define IPORTMXCOUNTER(n) (0x22014 + 0x400 * (n))
135 #define IPORTMXCNTMONI(n) (0x22018 + 0x400 * (n))
136 #define IPORTMXACLKSEL0EX(n) (0x22020 + 0x400 * (n))
137 #define IPORTMXACLKSEL0EX_ACLKSEL0EX_MASK GENMASK(3, 0)
138 #define IPORTMXACLKSEL0EX_ACLKSEL0EX_INTERNAL (0x0 << 0)
139 #define IPORTMXACLKSEL0EX_ACLKSEL0EX_EXTERNAL (0xf << 0)
140 #define IPORTMXEXNOE(n) (0x22070 + 0x400 * (n))
141 #define IPORTMXEXNOE_PCMINOE_MASK BIT(0)
142 #define IPORTMXEXNOE_PCMINOE_OUTPUT (0x0 << 0)
143 #define IPORTMXEXNOE_PCMINOE_INPUT (0x1 << 0)
144 #define IPORTMXMASK(n) (0x22078 + 0x400 * (n))
145 #define IPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)
146 #define IPORTMXMASK_IUXCKMSK_ON (0x0 << 16)
147 #define IPORTMXMASK_IUXCKMSK_OFF (0x7 << 16)
148 #define IPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)
149 #define IPORTMXMASK_XCKMSK_ON (0x0 << 0)
150 #define IPORTMXMASK_XCKMSK_OFF (0x7 << 0)
151 #define IPORTMXRSTCTR(n) (0x2207c + 0x400 * (n))
152 #define IPORTMXRSTCTR_RSTPI_MASK BIT(7)
153 #define IPORTMXRSTCTR_RSTPI_RELEASE (0x0 << 7)
154 #define IPORTMXRSTCTR_RSTPI_RESET (0x1 << 7)
157 #define PBINMXCTR(n) (0x20200 + 0x40 * (n))
158 #define PBINMXCTR_NCONNECT_MASK BIT(15)
159 #define PBINMXCTR_NCONNECT_CONNECT (0x0 << 15)
160 #define PBINMXCTR_NCONNECT_DISCONNECT (0x1 << 15)
161 #define PBINMXCTR_INOUTSEL_MASK BIT(14)
162 #define PBINMXCTR_INOUTSEL_IN (0x0 << 14)
163 #define PBINMXCTR_INOUTSEL_OUT (0x1 << 14)
164 #define PBINMXCTR_PBINSEL_SHIFT (8)
165 #define PBINMXCTR_ENDIAN_MASK GENMASK(5, 4)
166 #define PBINMXCTR_ENDIAN_3210 (0x0 << 4)
167 #define PBINMXCTR_ENDIAN_0123 (0x1 << 4)
168 #define PBINMXCTR_ENDIAN_1032 (0x2 << 4)
169 #define PBINMXCTR_ENDIAN_2301 (0x3 << 4)
170 #define PBINMXCTR_MEMFMT_MASK GENMASK(3, 0)
171 #define PBINMXCTR_MEMFMT_D0 (0x0 << 0)
172 #define PBINMXCTR_MEMFMT_5_1CH_DMIX (0x1 << 0)
173 #define PBINMXCTR_MEMFMT_6CH (0x2 << 0)
174 #define PBINMXCTR_MEMFMT_4CH (0x3 << 0)
175 #define PBINMXCTR_MEMFMT_DMIX (0x4 << 0)
176 #define PBINMXCTR_MEMFMT_1CH (0x5 << 0)
177 #define PBINMXCTR_MEMFMT_16LR (0x6 << 0)
178 #define PBINMXCTR_MEMFMT_7_1CH (0x7 << 0)
179 #define PBINMXCTR_MEMFMT_7_1CH_DMIX (0x8 << 0)
180 #define PBINMXCTR_MEMFMT_STREAM (0xf << 0)
181 #define PBINMXPAUSECTR0(n) (0x20204 + 0x40 * (n))
182 #define PBINMXPAUSECTR1(n) (0x20208 + 0x40 * (n))
185 #define AOUTENCTR0 0x40040
186 #define AOUTENCTR1 0x40044
187 #define AOUTENCTR2 0x40048
188 #define AOUTRSTCTR0 0x40060
189 #define AOUTRSTCTR1 0x40064
190 #define AOUTRSTCTR2 0x40068
191 #define AOUTSRCRSTCTR0 0x400c0
192 #define AOUTSRCRSTCTR1 0x400c4
193 #define AOUTSRCRSTCTR2 0x400c8
196 #define OPORTMXCTR1(n) (0x42000 + 0x400 * (n))
197 #define OPORTMXCTR1_I2SLRSEL_MASK (0x11 << 10)
198 #define OPORTMXCTR1_I2SLRSEL_RIGHT (0x00 << 10)
199 #define OPORTMXCTR1_I2SLRSEL_LEFT (0x01 << 10)
200 #define OPORTMXCTR1_I2SLRSEL_I2S (0x11 << 10)
201 #define OPORTMXCTR1_OUTBITSEL_MASK (0x800003U << 8)
202 #define OPORTMXCTR1_OUTBITSEL_32 (0x800000U << 8)
203 #define OPORTMXCTR1_OUTBITSEL_24 (0x000000U << 8)
204 #define OPORTMXCTR1_OUTBITSEL_20 (0x000001U << 8)
205 #define OPORTMXCTR1_OUTBITSEL_16 (0x000002U << 8)
206 #define OPORTMXCTR1_FSSEL_MASK GENMASK(3, 0)
207 #define OPORTMXCTR1_FSSEL_48 (0x0 << 0)
208 #define OPORTMXCTR1_FSSEL_96 (0x1 << 0)
209 #define OPORTMXCTR1_FSSEL_192 (0x2 << 0)
210 #define OPORTMXCTR1_FSSEL_32 (0x3 << 0)
211 #define OPORTMXCTR1_FSSEL_44_1 (0x4 << 0)
212 #define OPORTMXCTR1_FSSEL_88_2 (0x5 << 0)
213 #define OPORTMXCTR1_FSSEL_176_4 (0x6 << 0)
214 #define OPORTMXCTR1_FSSEL_16 (0x8 << 0)
215 #define OPORTMXCTR1_FSSEL_22_05 (0x9 << 0)
216 #define OPORTMXCTR1_FSSEL_24 (0xa << 0)
217 #define OPORTMXCTR1_FSSEL_8 (0xb << 0)
218 #define OPORTMXCTR1_FSSEL_11_025 (0xc << 0)
219 #define OPORTMXCTR1_FSSEL_12 (0xd << 0)
220 #define OPORTMXCTR2(n) (0x42004 + 0x400 * (n))
221 #define OPORTMXCTR2_ACLKSEL_MASK GENMASK(19, 16)
222 #define OPORTMXCTR2_ACLKSEL_A1 (0x0 << 16)
223 #define OPORTMXCTR2_ACLKSEL_F1 (0x1 << 16)
224 #define OPORTMXCTR2_ACLKSEL_A2 (0x2 << 16)
225 #define OPORTMXCTR2_ACLKSEL_F2 (0x3 << 16)
226 #define OPORTMXCTR2_ACLKSEL_A2PLL (0x4 << 16)
227 #define OPORTMXCTR2_ACLKSEL_RX1 (0x5 << 16)
228 #define OPORTMXCTR2_ACLKSEL_RX2 (0x6 << 16)
229 #define OPORTMXCTR2_MSSEL_MASK BIT(15)
230 #define OPORTMXCTR2_MSSEL_SLAVE (0x0 << 15)
231 #define OPORTMXCTR2_MSSEL_MASTER (0x1 << 15)
232 #define OPORTMXCTR2_EXTLSIFSSEL_MASK BIT(14)
233 #define OPORTMXCTR2_EXTLSIFSSEL_36 (0x0 << 14)
234 #define OPORTMXCTR2_EXTLSIFSSEL_24 (0x1 << 14)
235 #define OPORTMXCTR2_DACCKSEL_MASK GENMASK(9, 8)
236 #define OPORTMXCTR2_DACCKSEL_1_2 (0x0 << 8)
237 #define OPORTMXCTR2_DACCKSEL_1_3 (0x1 << 8)
238 #define OPORTMXCTR2_DACCKSEL_1_1 (0x2 << 8)
239 #define OPORTMXCTR2_DACCKSEL_2_3 (0x3 << 8)
240 #define OPORTMXCTR3(n) (0x42008 + 0x400 * (n))
241 #define OPORTMXCTR3_IECTHUR_MASK BIT(19)
242 #define OPORTMXCTR3_IECTHUR_IECOUT (0x0 << 19)
243 #define OPORTMXCTR3_IECTHUR_IECIN (0x1 << 19)
244 #define OPORTMXCTR3_SRCSEL_MASK GENMASK(18, 16)
245 #define OPORTMXCTR3_SRCSEL_PCM (0x0 << 16)
246 #define OPORTMXCTR3_SRCSEL_STREAM (0x1 << 16)
247 #define OPORTMXCTR3_SRCSEL_CDDTS (0x2 << 16)
248 #define OPORTMXCTR3_VALID_MASK BIT(12)
249 #define OPORTMXCTR3_VALID_PCM (0x0 << 12)
250 #define OPORTMXCTR3_VALID_STREAM (0x1 << 12)
251 #define OPORTMXCTR3_PMSEL_MASK BIT(3)
252 #define OPORTMXCTR3_PMSEL_MUTE (0x0 << 3)
253 #define OPORTMXCTR3_PMSEL_PAUSE (0x1 << 3)
254 #define OPORTMXCTR3_PMSW_MASK BIT(2)
255 #define OPORTMXCTR3_PMSW_MUTE_OFF (0x0 << 2)
256 #define OPORTMXCTR3_PMSW_MUTE_ON (0x1 << 2)
257 #define OPORTMXSRC1CTR(n) (0x4200c + 0x400 * (n))
258 #define OPORTMXSRC1CTR_FSIIPNUM_SHIFT (24)
259 #define OPORTMXSRC1CTR_THMODE_MASK BIT(23)
260 #define OPORTMXSRC1CTR_THMODE_SRC (0x0 << 23)
261 #define OPORTMXSRC1CTR_THMODE_BYPASS (0x1 << 23)
262 #define OPORTMXSRC1CTR_LOCK_MASK BIT(16)
263 #define OPORTMXSRC1CTR_LOCK_UNLOCK (0x0 << 16)
264 #define OPORTMXSRC1CTR_LOCK_LOCK (0x1 << 16)
265 #define OPORTMXSRC1CTR_SRCPATH_MASK BIT(15)
266 #define OPORTMXSRC1CTR_SRCPATH_BYPASS (0x0 << 15)
267 #define OPORTMXSRC1CTR_SRCPATH_CALC (0x1 << 15)
268 #define OPORTMXSRC1CTR_SYNC_MASK BIT(14)
269 #define OPORTMXSRC1CTR_SYNC_ASYNC (0x0 << 14)
270 #define OPORTMXSRC1CTR_SYNC_SYNC (0x1 << 14)
271 #define OPORTMXSRC1CTR_FSOCK_MASK GENMASK(11, 10)
272 #define OPORTMXSRC1CTR_FSOCK_44_1 (0x0 << 10)
273 #define OPORTMXSRC1CTR_FSOCK_48 (0x1 << 10)
274 #define OPORTMXSRC1CTR_FSOCK_32 (0x2 << 10)
275 #define OPORTMXSRC1CTR_FSICK_MASK GENMASK(9, 8)
276 #define OPORTMXSRC1CTR_FSICK_44_1 (0x0 << 8)
277 #define OPORTMXSRC1CTR_FSICK_48 (0x1 << 8)
278 #define OPORTMXSRC1CTR_FSICK_32 (0x2 << 8)
279 #define OPORTMXSRC1CTR_FSIIPSEL_MASK GENMASK(5, 4)
280 #define OPORTMXSRC1CTR_FSIIPSEL_INNER (0x0 << 4)
281 #define OPORTMXSRC1CTR_FSIIPSEL_OUTER (0x1 << 4)
282 #define OPORTMXSRC1CTR_FSISEL_MASK GENMASK(3, 0)
283 #define OPORTMXSRC1CTR_FSISEL_ACLK (0x0 << 0)
284 #define OPORTMXSRC1CTR_FSISEL_DD (0x1 << 0)
285 #define OPORTMXDSDMUTEDAT(n) (0x42020 + 0x400 * (n))
286 #define OPORTMXDXDFREQMODE(n) (0x42024 + 0x400 * (n))
287 #define OPORTMXDSDSEL(n) (0x42028 + 0x400 * (n))
288 #define OPORTMXDSDPORT(n) (0x4202c + 0x400 * (n))
289 #define OPORTMXACLKSEL0EX(n) (0x42030 + 0x400 * (n))
290 #define OPORTMXPATH(n) (0x42040 + 0x400 * (n))
291 #define OPORTMXSYNC(n) (0x42044 + 0x400 * (n))
292 #define OPORTMXREPET(n) (0x42050 + 0x400 * (n))
293 #define OPORTMXREPET_STRLENGTH_AC3 SBF_(IEC61937_FRM_STR_AC3, 16)
294 #define OPORTMXREPET_STRLENGTH_MPA SBF_(IEC61937_FRM_STR_MPA, 16)
295 #define OPORTMXREPET_STRLENGTH_MP3 SBF_(IEC61937_FRM_STR_MP3, 16)
296 #define OPORTMXREPET_STRLENGTH_DTS1 SBF_(IEC61937_FRM_STR_DTS1, 16)
297 #define OPORTMXREPET_STRLENGTH_DTS2 SBF_(IEC61937_FRM_STR_DTS2, 16)
298 #define OPORTMXREPET_STRLENGTH_DTS3 SBF_(IEC61937_FRM_STR_DTS3, 16)
299 #define OPORTMXREPET_STRLENGTH_AAC SBF_(IEC61937_FRM_STR_AAC, 16)
300 #define OPORTMXREPET_PMLENGTH_AC3 SBF_(IEC61937_FRM_PAU_AC3, 0)
301 #define OPORTMXREPET_PMLENGTH_MPA SBF_(IEC61937_FRM_PAU_MPA, 0)
302 #define OPORTMXREPET_PMLENGTH_MP3 SBF_(IEC61937_FRM_PAU_MP3, 0)
303 #define OPORTMXREPET_PMLENGTH_DTS1 SBF_(IEC61937_FRM_PAU_DTS1, 0)
304 #define OPORTMXREPET_PMLENGTH_DTS2 SBF_(IEC61937_FRM_PAU_DTS2, 0)
305 #define OPORTMXREPET_PMLENGTH_DTS3 SBF_(IEC61937_FRM_PAU_DTS3, 0)
306 #define OPORTMXREPET_PMLENGTH_AAC SBF_(IEC61937_FRM_PAU_AAC, 0)
307 #define OPORTMXPAUDAT(n) (0x42054 + 0x400 * (n))
308 #define OPORTMXPAUDAT_PAUSEPC_CMN (IEC61937_PC_PAUSE << 16)
309 #define OPORTMXPAUDAT_PAUSEPD_AC3 (IEC61937_FRM_PAU_AC3 * 4)
310 #define OPORTMXPAUDAT_PAUSEPD_MPA (IEC61937_FRM_PAU_MPA * 4)
311 #define OPORTMXPAUDAT_PAUSEPD_MP3 (IEC61937_FRM_PAU_MP3 * 4)
312 #define OPORTMXPAUDAT_PAUSEPD_DTS1 (IEC61937_FRM_PAU_DTS1 * 4)
313 #define OPORTMXPAUDAT_PAUSEPD_DTS2 (IEC61937_FRM_PAU_DTS2 * 4)
314 #define OPORTMXPAUDAT_PAUSEPD_DTS3 (IEC61937_FRM_PAU_DTS3 * 4)
315 #define OPORTMXPAUDAT_PAUSEPD_AAC (IEC61937_FRM_PAU_AAC * 4)
316 #define OPORTMXRATE_I(n) (0x420e4 + 0x400 * (n))
317 #define OPORTMXRATE_I_EQU_MASK BIT(31)
318 #define OPORTMXRATE_I_EQU_NOTEQUAL (0x0 << 31)
319 #define OPORTMXRATE_I_EQU_EQUAL (0x1 << 31)
320 #define OPORTMXRATE_I_SRCBPMD_MASK BIT(29)
321 #define OPORTMXRATE_I_SRCBPMD_BYPASS (0x0 << 29)
322 #define OPORTMXRATE_I_SRCBPMD_SRC (0x1 << 29)
323 #define OPORTMXRATE_I_LRCKSTP_MASK BIT(24)
324 #define OPORTMXRATE_I_LRCKSTP_START (0x0 << 24)
325 #define OPORTMXRATE_I_LRCKSTP_STOP (0x1 << 24)
326 #define OPORTMXRATE_I_ACLKSRC_MASK GENMASK(15, 12)
327 #define OPORTMXRATE_I_ACLKSRC_APLL (0x0 << 12)
328 #define OPORTMXRATE_I_ACLKSRC_USB (0x1 << 12)
329 #define OPORTMXRATE_I_ACLKSRC_HSC (0x3 << 12)
330 /* if OPORTMXRATE_I_ACLKSRC_APLL */
331 #define OPORTMXRATE_I_ACLKSEL_MASK GENMASK(11, 8)
332 #define OPORTMXRATE_I_ACLKSEL_APLLA1 (0x0 << 8)
333 #define OPORTMXRATE_I_ACLKSEL_APLLF1 (0x1 << 8)
334 #define OPORTMXRATE_I_ACLKSEL_APLLA2 (0x2 << 8)
335 #define OPORTMXRATE_I_ACLKSEL_APLLF2 (0x3 << 8)
336 #define OPORTMXRATE_I_ACLKSEL_APLL (0x4 << 8)
337 #define OPORTMXRATE_I_ACLKSEL_HDMI1 (0x5 << 8)
338 #define OPORTMXRATE_I_ACLKSEL_HDMI2 (0x6 << 8)
339 #define OPORTMXRATE_I_ACLKSEL_AI1ADCCK (0xc << 8)
340 #define OPORTMXRATE_I_ACLKSEL_AI2ADCCK (0xd << 8)
341 #define OPORTMXRATE_I_ACLKSEL_AI3ADCCK (0xe << 8)
342 #define OPORTMXRATE_I_MCKSEL_MASK GENMASK(7, 4)
343 #define OPORTMXRATE_I_MCKSEL_36 (0x0 << 4)
344 #define OPORTMXRATE_I_MCKSEL_33 (0x1 << 4)
345 #define OPORTMXRATE_I_MCKSEL_HSC27 (0xb << 4)
346 #define OPORTMXRATE_I_FSSEL_MASK GENMASK(3, 0)
347 #define OPORTMXRATE_I_FSSEL_48 (0x0 << 0)
348 #define OPORTMXRATE_I_FSSEL_96 (0x1 << 0)
349 #define OPORTMXRATE_I_FSSEL_192 (0x2 << 0)
350 #define OPORTMXRATE_I_FSSEL_32 (0x3 << 0)
351 #define OPORTMXRATE_I_FSSEL_44_1 (0x4 << 0)
352 #define OPORTMXRATE_I_FSSEL_88_2 (0x5 << 0)
353 #define OPORTMXRATE_I_FSSEL_176_4 (0x6 << 0)
354 #define OPORTMXRATE_I_FSSEL_16 (0x8 << 0)
355 #define OPORTMXRATE_I_FSSEL_22_05 (0x9 << 0)
356 #define OPORTMXRATE_I_FSSEL_24 (0xa << 0)
357 #define OPORTMXRATE_I_FSSEL_8 (0xb << 0)
358 #define OPORTMXRATE_I_FSSEL_11_025 (0xc << 0)
359 #define OPORTMXRATE_I_FSSEL_12 (0xd << 0)
360 #define OPORTMXEXNOE(n) (0x420f0 + 0x400 * (n))
361 #define OPORTMXMASK(n) (0x420f8 + 0x400 * (n))
362 #define OPORTMXMASK_IUDXMSK_MASK GENMASK(28, 24)
363 #define OPORTMXMASK_IUDXMSK_ON (0x00 << 24)
364 #define OPORTMXMASK_IUDXMSK_OFF (0x1f << 24)
365 #define OPORTMXMASK_IUXCKMSK_MASK GENMASK(18, 16)
366 #define OPORTMXMASK_IUXCKMSK_ON (0x0 << 16)
367 #define OPORTMXMASK_IUXCKMSK_OFF (0x7 << 16)
368 #define OPORTMXMASK_DXMSK_MASK GENMASK(12, 8)
369 #define OPORTMXMASK_DXMSK_ON (0x00 << 8)
370 #define OPORTMXMASK_DXMSK_OFF (0x1f << 8)
371 #define OPORTMXMASK_XCKMSK_MASK GENMASK(2, 0)
372 #define OPORTMXMASK_XCKMSK_ON (0x0 << 0)
373 #define OPORTMXMASK_XCKMSK_OFF (0x7 << 0)
374 #define OPORTMXDEBUG(n) (0x420fc + 0x400 * (n))
375 #define OPORTMXT0RSTCTR(n) (0x4211c + 0x400 * (n))
376 #define OPORTMXT1RSTCTR(n) (0x4213c + 0x400 * (n))
377 #define OPORTMXT2RSTCTR(n) (0x4215c + 0x400 * (n))
378 #define OPORTMXT3RSTCTR(n) (0x4217c + 0x400 * (n))
379 #define OPORTMXT4RSTCTR(n) (0x4219c + 0x400 * (n))
381 #define SBF_(frame, shift) (((frame) * 2 - 1) << shift)
384 #define PBOUTMXCTR0(n) (0x40200 + 0x40 * (n))
385 #define PBOUTMXCTR0_ENDIAN_MASK GENMASK(5, 4)
386 #define PBOUTMXCTR0_ENDIAN_3210 (0x0 << 4)
387 #define PBOUTMXCTR0_ENDIAN_0123 (0x1 << 4)
388 #define PBOUTMXCTR0_ENDIAN_1032 (0x2 << 4)
389 #define PBOUTMXCTR0_ENDIAN_2301 (0x3 << 4)
390 #define PBOUTMXCTR0_MEMFMT_MASK GENMASK(3, 0)
391 #define PBOUTMXCTR0_MEMFMT_10CH (0x0 << 0)
392 #define PBOUTMXCTR0_MEMFMT_8CH (0x1 << 0)
393 #define PBOUTMXCTR0_MEMFMT_6CH (0x2 << 0)
394 #define PBOUTMXCTR0_MEMFMT_4CH (0x3 << 0)
395 #define PBOUTMXCTR0_MEMFMT_2CH (0x4 << 0)
396 #define PBOUTMXCTR0_MEMFMT_STREAM (0x5 << 0)
397 #define PBOUTMXCTR0_MEMFMT_1CH (0x6 << 0)
398 #define PBOUTMXCTR1(n) (0x40204 + 0x40 * (n))
399 #define PBOUTMXINTCTR(n) (0x40208 + 0x40 * (n))
402 #define CDA2D_STRT0 0x10000
403 #define CDA2D_STRT0_STOP_MASK BIT(31)
404 #define CDA2D_STRT0_STOP_START (0x0 << 31)
405 #define CDA2D_STRT0_STOP_STOP (0x1 << 31)
406 #define CDA2D_STAT0 0x10020
407 #define CDA2D_TEST 0x100a0
408 #define CDA2D_TEST_DDR_MODE_MASK GENMASK(3, 2)
409 #define CDA2D_TEST_DDR_MODE_EXTON0 (0x0 << 2)
410 #define CDA2D_TEST_DDR_MODE_EXTOFF1 (0x3 << 2)
411 #define CDA2D_STRTADRSLOAD 0x100b0
413 #define CDA2D_CHMXCTRL1(n) (0x12000 + 0x80 * (n))
414 #define CDA2D_CHMXCTRL1_INDSIZE_MASK BIT(0)
415 #define CDA2D_CHMXCTRL1_INDSIZE_FINITE (0x0 << 0)
416 #define CDA2D_CHMXCTRL1_INDSIZE_INFINITE (0x1 << 0)
417 #define CDA2D_CHMXCTRL2(n) (0x12004 + 0x80 * (n))
418 #define CDA2D_CHMXSRCAMODE(n) (0x12020 + 0x80 * (n))
419 #define CDA2D_CHMXDSTAMODE(n) (0x12024 + 0x80 * (n))
420 #define CDA2D_CHMXAMODE_ENDIAN_MASK GENMASK(17, 16)
421 #define CDA2D_CHMXAMODE_ENDIAN_3210 (0x0 << 16)
422 #define CDA2D_CHMXAMODE_ENDIAN_0123 (0x1 << 16)
423 #define CDA2D_CHMXAMODE_ENDIAN_1032 (0x2 << 16)
424 #define CDA2D_CHMXAMODE_ENDIAN_2301 (0x3 << 16)
425 #define CDA2D_CHMXAMODE_RSSEL_SHIFT (8)
426 #define CDA2D_CHMXAMODE_AUPDT_MASK GENMASK(5, 4)
427 #define CDA2D_CHMXAMODE_AUPDT_INC (0x0 << 4)
428 #define CDA2D_CHMXAMODE_AUPDT_FIX (0x2 << 4)
429 #define CDA2D_CHMXAMODE_TYPE_MASK GENMASK(3, 2)
430 #define CDA2D_CHMXAMODE_TYPE_NORMAL (0x0 << 2)
431 #define CDA2D_CHMXAMODE_TYPE_RING (0x1 << 2)
432 #define CDA2D_CHMXSRCSTRTADRS(n) (0x12030 + 0x80 * (n))
433 #define CDA2D_CHMXSRCSTRTADRSU(n) (0x12034 + 0x80 * (n))
434 #define CDA2D_CHMXDSTSTRTADRS(n) (0x12038 + 0x80 * (n))
435 #define CDA2D_CHMXDSTSTRTADRSU(n) (0x1203c + 0x80 * (n))
437 /* A2D(ring buffer) */
438 #define CDA2D_RBFLUSH0 0x10040
439 #define CDA2D_RBADRSLOAD 0x100b4
440 #define CDA2D_RDPTRLOAD 0x100b8
441 #define CDA2D_RDPTRLOAD_LSFLAG_LOAD (0x0 << 31)
442 #define CDA2D_RDPTRLOAD_LSFLAG_STORE (0x1 << 31)
443 #define CDA2D_WRPTRLOAD 0x100bc
444 #define CDA2D_WRPTRLOAD_LSFLAG_LOAD (0x0 << 31)
445 #define CDA2D_WRPTRLOAD_LSFLAG_STORE (0x1 << 31)
447 #define CDA2D_RBMXBGNADRS(n) (0x14000 + 0x80 * (n))
448 #define CDA2D_RBMXBGNADRSU(n) (0x14004 + 0x80 * (n))
449 #define CDA2D_RBMXENDADRS(n) (0x14008 + 0x80 * (n))
450 #define CDA2D_RBMXENDADRSU(n) (0x1400c + 0x80 * (n))
451 #define CDA2D_RBMXBTH(n) (0x14038 + 0x80 * (n))
452 #define CDA2D_RBMXRTH(n) (0x1403c + 0x80 * (n))
453 #define CDA2D_RBMXRDPTR(n) (0x14020 + 0x80 * (n))
454 #define CDA2D_RBMXRDPTRU(n) (0x14024 + 0x80 * (n))
455 #define CDA2D_RBMXWRPTR(n) (0x14028 + 0x80 * (n))
456 #define CDA2D_RBMXWRPTRU(n) (0x1402c + 0x80 * (n))
457 #define CDA2D_RBMXPTRU_PTRU_MASK GENMASK(1, 0)
458 #define CDA2D_RBMXCNFG(n) (0x14030 + 0x80 * (n))
459 #define CDA2D_RBMXIR(n) (0x14014 + 0x80 * (n))
460 #define CDA2D_RBMXIE(n) (0x14018 + 0x80 * (n))
461 #define CDA2D_RBMXID(n) (0x1401c + 0x80 * (n))
462 #define CDA2D_RBMXIX_SPACE BIT(3)
463 #define CDA2D_RBMXIX_REMAIN BIT(4)
465 #endif /* SND_UNIPHIER_AIO_REG_H__ */