1 // SPDX-License-Identifier: GPL-2.0-only
3 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
8 * Suresh Rajashekara <suresh.r@ti.com>
9 * Steve Chen <schen@.mvista.com>
11 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
12 * Copyright: (C) 2009 Texas Instruments, India
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/delay.h>
21 #include <linux/clk.h>
22 #include <linux/pm_runtime.h>
24 #include <linux/of_platform.h>
25 #include <linux/of_device.h>
26 #include <linux/platform_data/davinci_asp.h>
27 #include <linux/math64.h>
28 #include <linux/bitmap.h>
29 #include <linux/gpio/driver.h>
31 #include <sound/asoundef.h>
32 #include <sound/core.h>
33 #include <sound/pcm.h>
34 #include <sound/pcm_params.h>
35 #include <sound/initval.h>
36 #include <sound/soc.h>
37 #include <sound/dmaengine_pcm.h>
42 #include "davinci-mcasp.h"
44 #define MCASP_MAX_AFIFO_DEPTH 64
47 static u32 context_regs[] = {
48 DAVINCI_MCASP_TXFMCTL_REG,
49 DAVINCI_MCASP_RXFMCTL_REG,
50 DAVINCI_MCASP_TXFMT_REG,
51 DAVINCI_MCASP_RXFMT_REG,
52 DAVINCI_MCASP_ACLKXCTL_REG,
53 DAVINCI_MCASP_ACLKRCTL_REG,
54 DAVINCI_MCASP_AHCLKXCTL_REG,
55 DAVINCI_MCASP_AHCLKRCTL_REG,
56 DAVINCI_MCASP_PDIR_REG,
57 DAVINCI_MCASP_PFUNC_REG,
58 DAVINCI_MCASP_RXMASK_REG,
59 DAVINCI_MCASP_TXMASK_REG,
60 DAVINCI_MCASP_RXTDM_REG,
61 DAVINCI_MCASP_TXTDM_REG,
64 struct davinci_mcasp_context {
65 u32 config_regs[ARRAY_SIZE(context_regs)];
66 u32 afifo_regs[2]; /* for read/write fifo control registers */
67 u32 *xrsr_regs; /* for serializer configuration */
72 struct davinci_mcasp_ruledata {
73 struct davinci_mcasp *mcasp;
77 struct davinci_mcasp {
78 struct snd_dmaengine_dai_dma_data dma_data[2];
82 struct snd_pcm_substream *substreams[2];
85 /* McASP specific data */
103 unsigned long pdir; /* Pin direction bitfield */
105 /* McASP FIFO related */
111 /* Used for comstraint setting on the second stream */
113 int max_format_width;
114 u8 active_serializers[2];
116 #ifdef CONFIG_GPIOLIB
117 struct gpio_chip gpio_chip;
121 struct davinci_mcasp_context context;
124 struct davinci_mcasp_ruledata ruledata[2];
125 struct snd_pcm_hw_constraint_list chconstr[2];
128 static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
131 void __iomem *reg = mcasp->base + offset;
132 __raw_writel(__raw_readl(reg) | val, reg);
135 static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
138 void __iomem *reg = mcasp->base + offset;
139 __raw_writel((__raw_readl(reg) & ~(val)), reg);
142 static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
145 void __iomem *reg = mcasp->base + offset;
146 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
149 static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
152 __raw_writel(val, mcasp->base + offset);
155 static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
157 return (u32)__raw_readl(mcasp->base + offset);
160 static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
164 mcasp_set_bits(mcasp, ctl_reg, val);
166 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
167 /* loop count is to avoid the lock-up */
168 for (i = 0; i < 1000; i++) {
169 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
173 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
174 printk(KERN_ERR "GBLCTL write error\n");
177 static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
179 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
180 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
182 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
185 static inline void mcasp_set_clk_pdir(struct davinci_mcasp *mcasp, bool enable)
187 u32 bit = PIN_BIT_AMUTE;
189 for_each_set_bit_from(bit, &mcasp->pdir, PIN_BIT_AFSR + 1) {
191 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
193 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
197 static inline void mcasp_set_axr_pdir(struct davinci_mcasp *mcasp, bool enable)
201 for_each_set_bit(bit, &mcasp->pdir, PIN_BIT_AMUTE) {
203 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
205 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(bit));
209 static void mcasp_start_rx(struct davinci_mcasp *mcasp)
211 if (mcasp->rxnumevt) { /* enable FIFO */
212 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
214 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
215 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
219 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
220 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
222 * When ASYNC == 0 the transmit and receive sections operate
223 * synchronously from the transmit clock and frame sync. We need to make
224 * sure that the TX signlas are enabled when starting reception.
226 if (mcasp_is_synchronous(mcasp)) {
227 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
228 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
229 mcasp_set_clk_pdir(mcasp, true);
232 /* Activate serializer(s) */
233 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
234 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
235 /* Release RX state machine */
236 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
237 /* Release Frame Sync generator */
238 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
239 if (mcasp_is_synchronous(mcasp))
240 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
242 /* enable receive IRQs */
243 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
244 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
247 static void mcasp_start_tx(struct davinci_mcasp *mcasp)
251 if (mcasp->txnumevt) { /* enable FIFO */
252 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
254 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
255 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
259 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
260 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
261 mcasp_set_clk_pdir(mcasp, true);
263 /* Activate serializer(s) */
264 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
265 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
267 /* wait for XDATA to be cleared */
269 while ((mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG) & XRDATA) &&
273 mcasp_set_axr_pdir(mcasp, true);
275 /* Release TX state machine */
276 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
277 /* Release Frame Sync generator */
278 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
280 /* enable transmit IRQs */
281 mcasp_set_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
282 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
285 static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
289 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
290 mcasp_start_tx(mcasp);
292 mcasp_start_rx(mcasp);
295 static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
297 /* disable IRQ sources */
298 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLR_REG,
299 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE]);
302 * In synchronous mode stop the TX clocks if no other stream is
305 if (mcasp_is_synchronous(mcasp) && !mcasp->streams) {
306 mcasp_set_clk_pdir(mcasp, false);
307 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
310 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
311 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
313 if (mcasp->rxnumevt) { /* disable FIFO */
314 u32 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
316 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
320 static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
324 /* disable IRQ sources */
325 mcasp_clr_bits(mcasp, DAVINCI_MCASP_EVTCTLX_REG,
326 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK]);
329 * In synchronous mode keep TX clocks running if the capture stream is
332 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
333 val = TXHCLKRST | TXCLKRST | TXFSRST;
335 mcasp_set_clk_pdir(mcasp, false);
338 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
339 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
341 if (mcasp->txnumevt) { /* disable FIFO */
342 u32 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
344 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
347 mcasp_set_axr_pdir(mcasp, false);
350 static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
354 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
355 mcasp_stop_tx(mcasp);
357 mcasp_stop_rx(mcasp);
360 static irqreturn_t davinci_mcasp_tx_irq_handler(int irq, void *data)
362 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
363 struct snd_pcm_substream *substream;
364 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK];
365 u32 handled_mask = 0;
368 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG);
369 if (stat & XUNDRN & irq_mask) {
370 dev_warn(mcasp->dev, "Transmit buffer underflow\n");
371 handled_mask |= XUNDRN;
373 substream = mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK];
375 snd_pcm_stop_xrun(substream);
379 dev_warn(mcasp->dev, "unhandled tx event. txstat: 0x%08x\n",
383 handled_mask |= XRERR;
385 /* Ack the handled event only */
386 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, handled_mask);
388 return IRQ_RETVAL(handled_mask);
391 static irqreturn_t davinci_mcasp_rx_irq_handler(int irq, void *data)
393 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
394 struct snd_pcm_substream *substream;
395 u32 irq_mask = mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE];
396 u32 handled_mask = 0;
399 stat = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG);
400 if (stat & ROVRN & irq_mask) {
401 dev_warn(mcasp->dev, "Receive buffer overflow\n");
402 handled_mask |= ROVRN;
404 substream = mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE];
406 snd_pcm_stop_xrun(substream);
410 dev_warn(mcasp->dev, "unhandled rx event. rxstat: 0x%08x\n",
414 handled_mask |= XRERR;
416 /* Ack the handled event only */
417 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, handled_mask);
419 return IRQ_RETVAL(handled_mask);
422 static irqreturn_t davinci_mcasp_common_irq_handler(int irq, void *data)
424 struct davinci_mcasp *mcasp = (struct davinci_mcasp *)data;
425 irqreturn_t ret = IRQ_NONE;
427 if (mcasp->substreams[SNDRV_PCM_STREAM_PLAYBACK])
428 ret = davinci_mcasp_tx_irq_handler(irq, data);
430 if (mcasp->substreams[SNDRV_PCM_STREAM_CAPTURE])
431 ret |= davinci_mcasp_rx_irq_handler(irq, data);
436 static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
439 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
448 pm_runtime_get_sync(mcasp->dev);
449 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
450 case SND_SOC_DAIFMT_DSP_A:
451 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
452 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
453 /* 1st data bit occur one ACLK cycle after the frame sync */
456 case SND_SOC_DAIFMT_DSP_B:
457 case SND_SOC_DAIFMT_AC97:
458 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
459 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
460 /* No delay after FS */
463 case SND_SOC_DAIFMT_I2S:
464 /* configure a full-word SYNC pulse (LRCLK) */
465 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
466 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
467 /* 1st data bit occur one ACLK cycle after the frame sync */
469 /* FS need to be inverted */
472 case SND_SOC_DAIFMT_RIGHT_J:
473 case SND_SOC_DAIFMT_LEFT_J:
474 /* configure a full-word SYNC pulse (LRCLK) */
475 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
476 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
477 /* No delay after FS */
485 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
487 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
490 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
491 case SND_SOC_DAIFMT_CBS_CFS:
492 /* codec is clock and frame slave */
493 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
494 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
496 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
497 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
500 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
501 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
503 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
504 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
506 mcasp->bclk_master = 1;
508 case SND_SOC_DAIFMT_CBS_CFM:
509 /* codec is clock slave and frame master */
510 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
511 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
513 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
514 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
517 set_bit(PIN_BIT_ACLKX, &mcasp->pdir);
518 set_bit(PIN_BIT_ACLKR, &mcasp->pdir);
520 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
521 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
523 mcasp->bclk_master = 1;
525 case SND_SOC_DAIFMT_CBM_CFS:
526 /* codec is clock master and frame slave */
527 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
528 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
530 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
531 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
534 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
535 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
537 set_bit(PIN_BIT_AFSX, &mcasp->pdir);
538 set_bit(PIN_BIT_AFSR, &mcasp->pdir);
540 mcasp->bclk_master = 0;
542 case SND_SOC_DAIFMT_CBM_CFM:
543 /* codec is clock and frame master */
544 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
545 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
547 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
548 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
551 clear_bit(PIN_BIT_ACLKX, &mcasp->pdir);
552 clear_bit(PIN_BIT_ACLKR, &mcasp->pdir);
554 clear_bit(PIN_BIT_AFSX, &mcasp->pdir);
555 clear_bit(PIN_BIT_AFSR, &mcasp->pdir);
557 mcasp->bclk_master = 0;
564 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
565 case SND_SOC_DAIFMT_IB_NF:
566 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
567 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
568 fs_pol_rising = true;
570 case SND_SOC_DAIFMT_NB_IF:
571 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
572 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
573 fs_pol_rising = false;
575 case SND_SOC_DAIFMT_IB_IF:
576 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
577 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
578 fs_pol_rising = false;
580 case SND_SOC_DAIFMT_NB_NF:
581 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
582 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
583 fs_pol_rising = true;
591 fs_pol_rising = !fs_pol_rising;
594 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
595 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
597 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
598 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
601 mcasp->dai_fmt = fmt;
603 pm_runtime_put(mcasp->dev);
607 static int __davinci_mcasp_set_clkdiv(struct davinci_mcasp *mcasp, int div_id,
608 int div, bool explicit)
610 pm_runtime_get_sync(mcasp->dev);
612 case MCASP_CLKDIV_AUXCLK: /* MCLK divider */
613 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
614 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
615 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
616 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
619 case MCASP_CLKDIV_BCLK: /* BCLK divider */
620 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
621 ACLKXDIV(div - 1), ACLKXDIV_MASK);
622 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
623 ACLKRDIV(div - 1), ACLKRDIV_MASK);
625 mcasp->bclk_div = div;
628 case MCASP_CLKDIV_BCLK_FS_RATIO:
630 * BCLK/LRCLK ratio descries how many bit-clock cycles
631 * fit into one frame. The clock ratio is given for a
632 * full period of data (for I2S format both left and
633 * right channels), so it has to be divided by number
634 * of tdm-slots (for I2S - divided by 2).
635 * Instead of storing this ratio, we calculate a new
636 * tdm_slot width by dividing the the ratio by the
637 * number of configured tdm slots.
639 mcasp->slot_width = div / mcasp->tdm_slots;
640 if (div % mcasp->tdm_slots)
642 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots",
643 __func__, div, mcasp->tdm_slots);
650 pm_runtime_put(mcasp->dev);
654 static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id,
657 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
659 return __davinci_mcasp_set_clkdiv(mcasp, div_id, div, 1);
662 static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
663 unsigned int freq, int dir)
665 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
667 pm_runtime_get_sync(mcasp->dev);
669 if (dir == SND_SOC_CLOCK_IN) {
671 case MCASP_CLK_HCLK_AHCLK:
672 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
674 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
676 clear_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
678 case MCASP_CLK_HCLK_AUXCLK:
679 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
681 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
683 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
686 dev_err(mcasp->dev, "Invalid clk id: %d\n", clk_id);
690 /* Select AUXCLK as HCLK */
691 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
692 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
693 set_bit(PIN_BIT_AHCLKX, &mcasp->pdir);
696 * When AHCLK X/R is selected to be output it means that the HCLK is
697 * the same clock - coming via AUXCLK.
699 mcasp->sysclk_freq = freq;
701 pm_runtime_put(mcasp->dev);
705 /* All serializers must have equal number of channels */
706 static int davinci_mcasp_ch_constraint(struct davinci_mcasp *mcasp, int stream,
709 struct snd_pcm_hw_constraint_list *cl = &mcasp->chconstr[stream];
710 unsigned int *list = (unsigned int *) cl->list;
711 int slots = mcasp->tdm_slots;
714 if (mcasp->tdm_mask[stream])
715 slots = hweight32(mcasp->tdm_mask[stream]);
717 for (i = 1; i <= slots; i++)
720 for (i = 2; i <= serializers; i++)
721 list[count++] = i*slots;
728 static int davinci_mcasp_set_ch_constraints(struct davinci_mcasp *mcasp)
730 int rx_serializers = 0, tx_serializers = 0, ret, i;
732 for (i = 0; i < mcasp->num_serializer; i++)
733 if (mcasp->serial_dir[i] == TX_MODE)
735 else if (mcasp->serial_dir[i] == RX_MODE)
738 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_PLAYBACK,
743 ret = davinci_mcasp_ch_constraint(mcasp, SNDRV_PCM_STREAM_CAPTURE,
750 static int davinci_mcasp_set_tdm_slot(struct snd_soc_dai *dai,
751 unsigned int tx_mask,
752 unsigned int rx_mask,
753 int slots, int slot_width)
755 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
758 "%s() tx_mask 0x%08x rx_mask 0x%08x slots %d width %d\n",
759 __func__, tx_mask, rx_mask, slots, slot_width);
761 if (tx_mask >= (1<<slots) || rx_mask >= (1<<slots)) {
763 "Bad tdm mask tx: 0x%08x rx: 0x%08x slots %d\n",
764 tx_mask, rx_mask, slots);
769 (slot_width < 8 || slot_width > 32 || slot_width % 4 != 0)) {
770 dev_err(mcasp->dev, "%s: Unsupported slot_width %d\n",
771 __func__, slot_width);
775 mcasp->tdm_slots = slots;
776 mcasp->tdm_mask[SNDRV_PCM_STREAM_PLAYBACK] = tx_mask;
777 mcasp->tdm_mask[SNDRV_PCM_STREAM_CAPTURE] = rx_mask;
778 mcasp->slot_width = slot_width;
780 return davinci_mcasp_set_ch_constraints(mcasp);
783 static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
787 u32 tx_rotate, rx_rotate, slot_width;
788 u32 mask = (1ULL << sample_width) - 1;
790 if (mcasp->slot_width)
791 slot_width = mcasp->slot_width;
792 else if (mcasp->max_format_width)
793 slot_width = mcasp->max_format_width;
795 slot_width = sample_width;
798 * right aligned formats: rotate w/ slot_width
799 * left aligned formats: rotate w/ sample_width
802 * right aligned formats: no rotation needed
803 * left aligned formats: rotate w/ (slot_width - sample_width)
805 if ((mcasp->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) ==
806 SND_SOC_DAIFMT_RIGHT_J) {
807 tx_rotate = (slot_width / 4) & 0x7;
810 tx_rotate = (sample_width / 4) & 0x7;
811 rx_rotate = (slot_width - sample_width) / 4;
814 /* mapping of the XSSZ bit-field as described in the datasheet */
815 fmt = (slot_width >> 1) - 1;
817 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
818 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
820 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
822 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
824 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
826 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
829 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
834 static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
835 int period_words, int channels)
837 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
841 u8 slots = mcasp->tdm_slots;
842 u8 max_active_serializers = (channels + slots - 1) / slots;
843 u8 max_rx_serializers, max_tx_serializers;
844 int active_serializers, numevt;
846 /* Default configuration */
847 if (mcasp->version < MCASP_VERSION_3)
848 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
850 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
851 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
852 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
853 max_tx_serializers = max_active_serializers;
855 mcasp->active_serializers[SNDRV_PCM_STREAM_CAPTURE];
857 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
858 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
860 mcasp->active_serializers[SNDRV_PCM_STREAM_PLAYBACK];
861 max_rx_serializers = max_active_serializers;
864 for (i = 0; i < mcasp->num_serializer; i++) {
865 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
866 mcasp->serial_dir[i]);
867 if (mcasp->serial_dir[i] == TX_MODE &&
868 tx_ser < max_tx_serializers) {
869 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
870 mcasp->dismod, DISMOD_MASK);
871 set_bit(PIN_BIT_AXR(i), &mcasp->pdir);
873 } else if (mcasp->serial_dir[i] == RX_MODE &&
874 rx_ser < max_rx_serializers) {
875 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
878 /* Inactive or unused pin, set it to inactive */
879 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
880 SRMOD_INACTIVE, SRMOD_MASK);
881 /* If unused, set DISMOD for the pin */
882 if (mcasp->serial_dir[i] != INACTIVE_MODE)
883 mcasp_mod_bits(mcasp,
884 DAVINCI_MCASP_XRSRCTL_REG(i),
885 mcasp->dismod, DISMOD_MASK);
886 clear_bit(PIN_BIT_AXR(i), &mcasp->pdir);
890 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
891 active_serializers = tx_ser;
892 numevt = mcasp->txnumevt;
893 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
895 active_serializers = rx_ser;
896 numevt = mcasp->rxnumevt;
897 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
900 if (active_serializers < max_active_serializers) {
901 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
902 "enabled in mcasp (%d)\n", channels,
903 active_serializers * slots);
907 /* AFIFO is not in use */
909 /* Configure the burst size for platform drivers */
910 if (active_serializers > 1) {
912 * If more than one serializers are in use we have one
913 * DMA request to provide data for all serializers.
914 * For example if three serializers are enabled the DMA
915 * need to transfer three words per DMA request.
917 dma_data->maxburst = active_serializers;
919 dma_data->maxburst = 0;
925 if (period_words % active_serializers) {
926 dev_err(mcasp->dev, "Invalid combination of period words and "
927 "active serializers: %d, %d\n", period_words,
933 * Calculate the optimal AFIFO depth for platform side:
934 * The number of words for numevt need to be in steps of active
937 numevt = (numevt / active_serializers) * active_serializers;
939 while (period_words % numevt && numevt > 0)
940 numevt -= active_serializers;
942 numevt = active_serializers;
944 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
945 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
947 /* Configure the burst size for platform drivers */
950 dma_data->maxburst = numevt;
953 mcasp->active_serializers[stream] = active_serializers;
958 static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream,
963 int active_serializers;
967 total_slots = mcasp->tdm_slots;
970 * If more than one serializer is needed, then use them with
971 * all the specified tdm_slots. Otherwise, one serializer can
972 * cope with the transaction using just as many slots as there
973 * are channels in the stream.
975 if (mcasp->tdm_mask[stream]) {
976 active_slots = hweight32(mcasp->tdm_mask[stream]);
977 active_serializers = (channels + active_slots - 1) /
979 if (active_serializers == 1)
980 active_slots = channels;
981 for (i = 0; i < total_slots; i++) {
982 if ((1 << i) & mcasp->tdm_mask[stream]) {
984 if (--active_slots <= 0)
989 active_serializers = (channels + total_slots - 1) / total_slots;
990 if (active_serializers == 1)
991 active_slots = channels;
993 active_slots = total_slots;
995 for (i = 0; i < active_slots; i++)
999 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
1001 if (!mcasp->dat_port)
1004 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1005 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
1006 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
1007 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1008 FSXMOD(total_slots), FSXMOD(0x1FF));
1009 } else if (stream == SNDRV_PCM_STREAM_CAPTURE) {
1010 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
1011 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
1012 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
1013 FSRMOD(total_slots), FSRMOD(0x1FF));
1015 * If McASP is set to be TX/RX synchronous and the playback is
1016 * not running already we need to configure the TX slots in
1017 * order to have correct FSX on the bus
1019 if (mcasp_is_synchronous(mcasp) && !mcasp->channels)
1020 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
1021 FSXMOD(total_slots), FSXMOD(0x1FF));
1028 static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp,
1032 u8 *cs_bytes = (u8*) &cs_value;
1034 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
1036 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
1038 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
1039 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
1041 /* Set the TX tdm : for all the slots */
1042 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
1044 /* Set the TX clock controls : div = 1 and internal */
1045 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
1047 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
1049 /* Only 44100 and 48000 are valid, both have the same setting */
1050 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
1052 /* Enable the DIT */
1053 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
1055 /* Set S/PDIF channel status bits */
1056 cs_bytes[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
1057 cs_bytes[1] = IEC958_AES1_CON_PCM_CODER;
1061 cs_bytes[3] |= IEC958_AES3_CON_FS_22050;
1064 cs_bytes[3] |= IEC958_AES3_CON_FS_24000;
1067 cs_bytes[3] |= IEC958_AES3_CON_FS_32000;
1070 cs_bytes[3] |= IEC958_AES3_CON_FS_44100;
1073 cs_bytes[3] |= IEC958_AES3_CON_FS_48000;
1076 cs_bytes[3] |= IEC958_AES3_CON_FS_88200;
1079 cs_bytes[3] |= IEC958_AES3_CON_FS_96000;
1082 cs_bytes[3] |= IEC958_AES3_CON_FS_176400;
1085 cs_bytes[3] |= IEC958_AES3_CON_FS_192000;
1088 printk(KERN_WARNING "unsupported sampling rate: %d\n", rate);
1092 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRA_REG, cs_value);
1093 mcasp_set_reg(mcasp, DAVINCI_MCASP_DITCSRB_REG, cs_value);
1098 static int davinci_mcasp_calc_clk_div(struct davinci_mcasp *mcasp,
1099 unsigned int sysclk_freq,
1100 unsigned int bclk_freq, bool set)
1102 u32 reg = mcasp_get_reg(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG);
1103 int div = sysclk_freq / bclk_freq;
1104 int rem = sysclk_freq % bclk_freq;
1108 if (div > (ACLKXDIV_MASK + 1)) {
1109 if (reg & AHCLKXE) {
1110 aux_div = div / (ACLKXDIV_MASK + 1);
1111 if (div % (ACLKXDIV_MASK + 1))
1114 sysclk_freq /= aux_div;
1115 div = sysclk_freq / bclk_freq;
1116 rem = sysclk_freq % bclk_freq;
1118 dev_warn(mcasp->dev, "Too fast reference clock (%u)\n",
1125 ((sysclk_freq / div) - bclk_freq) >
1126 (bclk_freq - (sysclk_freq / (div+1)))) {
1128 rem = rem - bclk_freq;
1131 error_ppm = (div*1000000 + (int)div64_long(1000000LL*rem,
1132 (int)bclk_freq)) / div - 1000000;
1136 dev_info(mcasp->dev, "Sample-rate is off by %d PPM\n",
1139 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_BCLK, div, 0);
1141 __davinci_mcasp_set_clkdiv(mcasp, MCASP_CLKDIV_AUXCLK,
1148 static inline u32 davinci_mcasp_tx_delay(struct davinci_mcasp *mcasp)
1150 if (!mcasp->txnumevt)
1153 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_WFIFOSTS_OFFSET);
1156 static inline u32 davinci_mcasp_rx_delay(struct davinci_mcasp *mcasp)
1158 if (!mcasp->rxnumevt)
1161 return mcasp_get_reg(mcasp, mcasp->fifo_base + MCASP_RFIFOSTS_OFFSET);
1164 static snd_pcm_sframes_t davinci_mcasp_delay(
1165 struct snd_pcm_substream *substream,
1166 struct snd_soc_dai *cpu_dai)
1168 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1171 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1172 fifo_use = davinci_mcasp_tx_delay(mcasp);
1174 fifo_use = davinci_mcasp_rx_delay(mcasp);
1177 * Divide the used locations with the channel count to get the
1178 * FIFO usage in samples (don't care about partial samples in the
1181 return fifo_use / substream->runtime->channels;
1184 static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
1185 struct snd_pcm_hw_params *params,
1186 struct snd_soc_dai *cpu_dai)
1188 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1190 int channels = params_channels(params);
1191 int period_size = params_period_size(params);
1194 switch (params_format(params)) {
1195 case SNDRV_PCM_FORMAT_U8:
1196 case SNDRV_PCM_FORMAT_S8:
1200 case SNDRV_PCM_FORMAT_U16_LE:
1201 case SNDRV_PCM_FORMAT_S16_LE:
1205 case SNDRV_PCM_FORMAT_U24_3LE:
1206 case SNDRV_PCM_FORMAT_S24_3LE:
1210 case SNDRV_PCM_FORMAT_U24_LE:
1211 case SNDRV_PCM_FORMAT_S24_LE:
1215 case SNDRV_PCM_FORMAT_U32_LE:
1216 case SNDRV_PCM_FORMAT_S32_LE:
1221 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
1225 ret = davinci_mcasp_set_dai_fmt(cpu_dai, mcasp->dai_fmt);
1230 * If mcasp is BCLK master, and a BCLK divider was not provided by
1231 * the machine driver, we need to calculate the ratio.
1233 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1234 int slots = mcasp->tdm_slots;
1235 int rate = params_rate(params);
1236 int sbits = params_width(params);
1238 if (mcasp->slot_width)
1239 sbits = mcasp->slot_width;
1241 davinci_mcasp_calc_clk_div(mcasp, mcasp->sysclk_freq,
1242 rate * sbits * slots, true);
1245 ret = mcasp_common_hw_param(mcasp, substream->stream,
1246 period_size * channels, channels);
1250 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1251 ret = mcasp_dit_hw_param(mcasp, params_rate(params));
1253 ret = mcasp_i2s_hw_param(mcasp, substream->stream,
1259 davinci_config_channel_size(mcasp, word_length);
1261 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
1262 mcasp->channels = channels;
1263 if (!mcasp->max_format_width)
1264 mcasp->max_format_width = word_length;
1270 static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
1271 int cmd, struct snd_soc_dai *cpu_dai)
1273 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1277 case SNDRV_PCM_TRIGGER_RESUME:
1278 case SNDRV_PCM_TRIGGER_START:
1279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1280 davinci_mcasp_start(mcasp, substream->stream);
1282 case SNDRV_PCM_TRIGGER_SUSPEND:
1283 case SNDRV_PCM_TRIGGER_STOP:
1284 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1285 davinci_mcasp_stop(mcasp, substream->stream);
1295 static int davinci_mcasp_hw_rule_slot_width(struct snd_pcm_hw_params *params,
1296 struct snd_pcm_hw_rule *rule)
1298 struct davinci_mcasp_ruledata *rd = rule->private;
1299 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1300 struct snd_mask nfmt;
1303 snd_mask_none(&nfmt);
1304 slot_width = rd->mcasp->slot_width;
1306 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1307 if (snd_mask_test(fmt, i)) {
1308 if (snd_pcm_format_width(i) <= slot_width) {
1309 snd_mask_set(&nfmt, i);
1314 return snd_mask_refine(fmt, &nfmt);
1317 static int davinci_mcasp_hw_rule_format_width(struct snd_pcm_hw_params *params,
1318 struct snd_pcm_hw_rule *rule)
1320 struct davinci_mcasp_ruledata *rd = rule->private;
1321 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1322 struct snd_mask nfmt;
1323 int i, format_width;
1325 snd_mask_none(&nfmt);
1326 format_width = rd->mcasp->max_format_width;
1328 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1329 if (snd_mask_test(fmt, i)) {
1330 if (snd_pcm_format_width(i) == format_width) {
1331 snd_mask_set(&nfmt, i);
1336 return snd_mask_refine(fmt, &nfmt);
1339 static const unsigned int davinci_mcasp_dai_rates[] = {
1340 8000, 11025, 16000, 22050, 32000, 44100, 48000, 64000,
1341 88200, 96000, 176400, 192000,
1344 #define DAVINCI_MAX_RATE_ERROR_PPM 1000
1346 static int davinci_mcasp_hw_rule_rate(struct snd_pcm_hw_params *params,
1347 struct snd_pcm_hw_rule *rule)
1349 struct davinci_mcasp_ruledata *rd = rule->private;
1350 struct snd_interval *ri =
1351 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
1352 int sbits = params_width(params);
1353 int slots = rd->mcasp->tdm_slots;
1354 struct snd_interval range;
1357 if (rd->mcasp->slot_width)
1358 sbits = rd->mcasp->slot_width;
1360 snd_interval_any(&range);
1363 for (i = 0; i < ARRAY_SIZE(davinci_mcasp_dai_rates); i++) {
1364 if (snd_interval_test(ri, davinci_mcasp_dai_rates[i])) {
1365 uint bclk_freq = sbits * slots *
1366 davinci_mcasp_dai_rates[i];
1367 unsigned int sysclk_freq;
1370 if (rd->mcasp->auxclk_fs_ratio)
1371 sysclk_freq = davinci_mcasp_dai_rates[i] *
1372 rd->mcasp->auxclk_fs_ratio;
1374 sysclk_freq = rd->mcasp->sysclk_freq;
1376 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1378 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1380 range.min = davinci_mcasp_dai_rates[i];
1383 range.max = davinci_mcasp_dai_rates[i];
1388 dev_dbg(rd->mcasp->dev,
1389 "Frequencies %d-%d -> %d-%d for %d sbits and %d tdm slots\n",
1390 ri->min, ri->max, range.min, range.max, sbits, slots);
1392 return snd_interval_refine(hw_param_interval(params, rule->var),
1396 static int davinci_mcasp_hw_rule_format(struct snd_pcm_hw_params *params,
1397 struct snd_pcm_hw_rule *rule)
1399 struct davinci_mcasp_ruledata *rd = rule->private;
1400 struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
1401 struct snd_mask nfmt;
1402 int rate = params_rate(params);
1403 int slots = rd->mcasp->tdm_slots;
1406 snd_mask_none(&nfmt);
1408 for (i = 0; i <= SNDRV_PCM_FORMAT_LAST; i++) {
1409 if (snd_mask_test(fmt, i)) {
1410 uint sbits = snd_pcm_format_width(i);
1411 unsigned int sysclk_freq;
1414 if (rd->mcasp->auxclk_fs_ratio)
1415 sysclk_freq = rate *
1416 rd->mcasp->auxclk_fs_ratio;
1418 sysclk_freq = rd->mcasp->sysclk_freq;
1420 if (rd->mcasp->slot_width)
1421 sbits = rd->mcasp->slot_width;
1423 ppm = davinci_mcasp_calc_clk_div(rd->mcasp, sysclk_freq,
1424 sbits * slots * rate,
1426 if (abs(ppm) < DAVINCI_MAX_RATE_ERROR_PPM) {
1427 snd_mask_set(&nfmt, i);
1432 dev_dbg(rd->mcasp->dev,
1433 "%d possible sample format for %d Hz and %d tdm slots\n",
1434 count, rate, slots);
1436 return snd_mask_refine(fmt, &nfmt);
1439 static int davinci_mcasp_hw_rule_min_periodsize(
1440 struct snd_pcm_hw_params *params, struct snd_pcm_hw_rule *rule)
1442 struct snd_interval *period_size = hw_param_interval(params,
1443 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
1444 struct snd_interval frames;
1446 snd_interval_any(&frames);
1450 return snd_interval_refine(period_size, &frames);
1453 static int davinci_mcasp_startup(struct snd_pcm_substream *substream,
1454 struct snd_soc_dai *cpu_dai)
1456 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1457 struct davinci_mcasp_ruledata *ruledata =
1458 &mcasp->ruledata[substream->stream];
1459 u32 max_channels = 0;
1461 int tdm_slots = mcasp->tdm_slots;
1463 /* Do not allow more then one stream per direction */
1464 if (mcasp->substreams[substream->stream])
1467 mcasp->substreams[substream->stream] = substream;
1469 if (mcasp->tdm_mask[substream->stream])
1470 tdm_slots = hweight32(mcasp->tdm_mask[substream->stream]);
1472 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1476 * Limit the maximum allowed channels for the first stream:
1477 * number of serializers for the direction * tdm slots per serializer
1479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1484 for (i = 0; i < mcasp->num_serializer; i++) {
1485 if (mcasp->serial_dir[i] == dir)
1488 ruledata->serializers = max_channels;
1489 ruledata->mcasp = mcasp;
1490 max_channels *= tdm_slots;
1492 * If the already active stream has less channels than the calculated
1493 * limit based on the seirializers * tdm_slots, and only one serializer
1494 * is in use we need to use that as a constraint for the second stream.
1495 * Otherwise (first stream or less allowed channels or more than one
1496 * serializer in use) we use the calculated constraint.
1498 if (mcasp->channels && mcasp->channels < max_channels &&
1499 ruledata->serializers == 1)
1500 max_channels = mcasp->channels;
1502 * But we can always allow channels upto the amount of
1503 * the available tdm_slots.
1505 if (max_channels < tdm_slots)
1506 max_channels = tdm_slots;
1508 snd_pcm_hw_constraint_minmax(substream->runtime,
1509 SNDRV_PCM_HW_PARAM_CHANNELS,
1512 snd_pcm_hw_constraint_list(substream->runtime,
1513 0, SNDRV_PCM_HW_PARAM_CHANNELS,
1514 &mcasp->chconstr[substream->stream]);
1516 if (mcasp->max_format_width) {
1518 * Only allow formats which require same amount of bits on the
1519 * bus as the currently running stream
1521 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1522 SNDRV_PCM_HW_PARAM_FORMAT,
1523 davinci_mcasp_hw_rule_format_width,
1525 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1529 else if (mcasp->slot_width) {
1530 /* Only allow formats require <= slot_width bits on the bus */
1531 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1532 SNDRV_PCM_HW_PARAM_FORMAT,
1533 davinci_mcasp_hw_rule_slot_width,
1535 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1541 * If we rely on implicit BCLK divider setting we should
1542 * set constraints based on what we can provide.
1544 if (mcasp->bclk_master && mcasp->bclk_div == 0 && mcasp->sysclk_freq) {
1545 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1546 SNDRV_PCM_HW_PARAM_RATE,
1547 davinci_mcasp_hw_rule_rate,
1549 SNDRV_PCM_HW_PARAM_FORMAT, -1);
1552 ret = snd_pcm_hw_rule_add(substream->runtime, 0,
1553 SNDRV_PCM_HW_PARAM_FORMAT,
1554 davinci_mcasp_hw_rule_format,
1556 SNDRV_PCM_HW_PARAM_RATE, -1);
1561 snd_pcm_hw_rule_add(substream->runtime, 0,
1562 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
1563 davinci_mcasp_hw_rule_min_periodsize, NULL,
1564 SNDRV_PCM_HW_PARAM_PERIOD_SIZE, -1);
1569 static void davinci_mcasp_shutdown(struct snd_pcm_substream *substream,
1570 struct snd_soc_dai *cpu_dai)
1572 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
1574 mcasp->substreams[substream->stream] = NULL;
1575 mcasp->active_serializers[substream->stream] = 0;
1577 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
1580 if (!cpu_dai->active) {
1581 mcasp->channels = 0;
1582 mcasp->max_format_width = 0;
1586 static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
1587 .startup = davinci_mcasp_startup,
1588 .shutdown = davinci_mcasp_shutdown,
1589 .trigger = davinci_mcasp_trigger,
1590 .delay = davinci_mcasp_delay,
1591 .hw_params = davinci_mcasp_hw_params,
1592 .set_fmt = davinci_mcasp_set_dai_fmt,
1593 .set_clkdiv = davinci_mcasp_set_clkdiv,
1594 .set_sysclk = davinci_mcasp_set_sysclk,
1595 .set_tdm_slot = davinci_mcasp_set_tdm_slot,
1598 static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
1600 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
1602 dai->playback_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
1603 dai->capture_dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
1608 #define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
1610 #define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
1611 SNDRV_PCM_FMTBIT_U8 | \
1612 SNDRV_PCM_FMTBIT_S16_LE | \
1613 SNDRV_PCM_FMTBIT_U16_LE | \
1614 SNDRV_PCM_FMTBIT_S24_LE | \
1615 SNDRV_PCM_FMTBIT_U24_LE | \
1616 SNDRV_PCM_FMTBIT_S24_3LE | \
1617 SNDRV_PCM_FMTBIT_U24_3LE | \
1618 SNDRV_PCM_FMTBIT_S32_LE | \
1619 SNDRV_PCM_FMTBIT_U32_LE)
1621 static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
1623 .name = "davinci-mcasp.0",
1624 .probe = davinci_mcasp_dai_probe,
1627 .channels_max = 32 * 16,
1628 .rates = DAVINCI_MCASP_RATES,
1629 .formats = DAVINCI_MCASP_PCM_FMTS,
1633 .channels_max = 32 * 16,
1634 .rates = DAVINCI_MCASP_RATES,
1635 .formats = DAVINCI_MCASP_PCM_FMTS,
1637 .ops = &davinci_mcasp_dai_ops,
1639 .symmetric_rates = 1,
1642 .name = "davinci-mcasp.1",
1643 .probe = davinci_mcasp_dai_probe,
1646 .channels_max = 384,
1647 .rates = DAVINCI_MCASP_RATES,
1648 .formats = DAVINCI_MCASP_PCM_FMTS,
1650 .ops = &davinci_mcasp_dai_ops,
1655 static const struct snd_soc_component_driver davinci_mcasp_component = {
1656 .name = "davinci-mcasp",
1659 /* Some HW specific values and defaults. The rest is filled in from DT. */
1660 static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
1661 .tx_dma_offset = 0x400,
1662 .rx_dma_offset = 0x400,
1663 .version = MCASP_VERSION_1,
1666 static struct davinci_mcasp_pdata da830_mcasp_pdata = {
1667 .tx_dma_offset = 0x2000,
1668 .rx_dma_offset = 0x2000,
1669 .version = MCASP_VERSION_2,
1672 static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
1675 .version = MCASP_VERSION_3,
1678 static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
1679 /* The CFG port offset will be calculated if it is needed */
1682 .version = MCASP_VERSION_4,
1685 static const struct of_device_id mcasp_dt_ids[] = {
1687 .compatible = "ti,dm646x-mcasp-audio",
1688 .data = &dm646x_mcasp_pdata,
1691 .compatible = "ti,da830-mcasp-audio",
1692 .data = &da830_mcasp_pdata,
1695 .compatible = "ti,am33xx-mcasp-audio",
1696 .data = &am33xx_mcasp_pdata,
1699 .compatible = "ti,dra7-mcasp-audio",
1700 .data = &dra7_mcasp_pdata,
1704 MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
1706 static int mcasp_reparent_fck(struct platform_device *pdev)
1708 struct device_node *node = pdev->dev.of_node;
1709 struct clk *gfclk, *parent_clk;
1710 const char *parent_name;
1716 parent_name = of_get_property(node, "fck_parent", NULL);
1720 dev_warn(&pdev->dev, "Update the bindings to use assigned-clocks!\n");
1722 gfclk = clk_get(&pdev->dev, "fck");
1723 if (IS_ERR(gfclk)) {
1724 dev_err(&pdev->dev, "failed to get fck\n");
1725 return PTR_ERR(gfclk);
1728 parent_clk = clk_get(NULL, parent_name);
1729 if (IS_ERR(parent_clk)) {
1730 dev_err(&pdev->dev, "failed to get parent clock\n");
1731 ret = PTR_ERR(parent_clk);
1735 ret = clk_set_parent(gfclk, parent_clk);
1737 dev_err(&pdev->dev, "failed to reparent fck\n");
1742 clk_put(parent_clk);
1748 static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
1749 struct platform_device *pdev)
1751 struct device_node *np = pdev->dev.of_node;
1752 struct davinci_mcasp_pdata *pdata = NULL;
1753 const struct of_device_id *match =
1754 of_match_device(mcasp_dt_ids, &pdev->dev);
1755 struct of_phandle_args dma_spec;
1757 const u32 *of_serial_dir32;
1761 if (pdev->dev.platform_data) {
1762 pdata = pdev->dev.platform_data;
1763 pdata->dismod = DISMOD_LOW;
1766 pdata = devm_kmemdup(&pdev->dev, match->data, sizeof(*pdata),
1773 /* control shouldn't reach here. something is wrong */
1778 ret = of_property_read_u32(np, "op-mode", &val);
1780 pdata->op_mode = val;
1782 ret = of_property_read_u32(np, "tdm-slots", &val);
1784 if (val < 2 || val > 32) {
1786 "tdm-slots must be in rage [2-32]\n");
1791 pdata->tdm_slots = val;
1794 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
1796 if (of_serial_dir32) {
1797 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1798 (sizeof(*of_serial_dir) * val),
1800 if (!of_serial_dir) {
1805 for (i = 0; i < val; i++)
1806 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1808 pdata->num_serializer = val;
1809 pdata->serial_dir = of_serial_dir;
1812 ret = of_property_match_string(np, "dma-names", "tx");
1816 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1821 pdata->tx_dma_channel = dma_spec.args[0];
1823 /* RX is not valid in DIT mode */
1824 if (pdata->op_mode != DAVINCI_MCASP_DIT_MODE) {
1825 ret = of_property_match_string(np, "dma-names", "rx");
1829 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1834 pdata->rx_dma_channel = dma_spec.args[0];
1837 ret = of_property_read_u32(np, "tx-num-evt", &val);
1839 pdata->txnumevt = val;
1841 ret = of_property_read_u32(np, "rx-num-evt", &val);
1843 pdata->rxnumevt = val;
1845 ret = of_property_read_u32(np, "sram-size-playback", &val);
1847 pdata->sram_size_playback = val;
1849 ret = of_property_read_u32(np, "sram-size-capture", &val);
1851 pdata->sram_size_capture = val;
1853 ret = of_property_read_u32(np, "dismod", &val);
1855 if (val == 0 || val == 2 || val == 3) {
1856 pdata->dismod = DISMOD_VAL(val);
1858 dev_warn(&pdev->dev, "Invalid dismod value: %u\n", val);
1859 pdata->dismod = DISMOD_LOW;
1862 pdata->dismod = DISMOD_LOW;
1869 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1881 static const char *sdma_prefix = "ti,omap";
1883 static int davinci_mcasp_get_dma_type(struct davinci_mcasp *mcasp)
1885 struct dma_chan *chan;
1889 if (!mcasp->dev->of_node)
1892 tmp = mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK].filter_data;
1893 chan = dma_request_chan(mcasp->dev, tmp);
1895 if (PTR_ERR(chan) != -EPROBE_DEFER)
1897 "Can't verify DMA configuration (%ld)\n",
1899 return PTR_ERR(chan);
1901 if (WARN_ON(!chan->device || !chan->device->dev))
1904 if (chan->device->dev->of_node)
1905 ret = of_property_read_string(chan->device->dev->of_node,
1906 "compatible", &tmp);
1908 dev_dbg(mcasp->dev, "DMA controller has no of-node\n");
1910 dma_release_channel(chan);
1914 dev_dbg(mcasp->dev, "DMA controller compatible = \"%s\"\n", tmp);
1915 if (!strncmp(tmp, sdma_prefix, strlen(sdma_prefix)))
1917 else if (strstr(tmp, "udmap"))
1923 static u32 davinci_mcasp_txdma_offset(struct davinci_mcasp_pdata *pdata)
1928 if (pdata->version != MCASP_VERSION_4)
1929 return pdata->tx_dma_offset;
1931 for (i = 0; i < pdata->num_serializer; i++) {
1932 if (pdata->serial_dir[i] == TX_MODE) {
1934 offset = DAVINCI_MCASP_TXBUF_REG(i);
1936 pr_err("%s: Only one serializer allowed!\n",
1946 static u32 davinci_mcasp_rxdma_offset(struct davinci_mcasp_pdata *pdata)
1951 if (pdata->version != MCASP_VERSION_4)
1952 return pdata->rx_dma_offset;
1954 for (i = 0; i < pdata->num_serializer; i++) {
1955 if (pdata->serial_dir[i] == RX_MODE) {
1957 offset = DAVINCI_MCASP_RXBUF_REG(i);
1959 pr_err("%s: Only one serializer allowed!\n",
1969 #ifdef CONFIG_GPIOLIB
1970 static int davinci_mcasp_gpio_request(struct gpio_chip *chip, unsigned offset)
1972 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1974 if (mcasp->num_serializer && offset < mcasp->num_serializer &&
1975 mcasp->serial_dir[offset] != INACTIVE_MODE) {
1976 dev_err(mcasp->dev, "AXR%u pin is used for audio\n", offset);
1980 /* Do not change the PIN yet */
1982 return pm_runtime_get_sync(mcasp->dev);
1985 static void davinci_mcasp_gpio_free(struct gpio_chip *chip, unsigned offset)
1987 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
1989 /* Set the direction to input */
1990 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
1992 /* Set the pin as McASP pin */
1993 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
1995 pm_runtime_put_sync(mcasp->dev);
1998 static int davinci_mcasp_gpio_direction_out(struct gpio_chip *chip,
1999 unsigned offset, int value)
2001 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2005 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2007 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2009 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2010 if (!(val & BIT(offset))) {
2011 /* Set the pin as GPIO pin */
2012 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2014 /* Set the direction to output */
2015 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2021 static void davinci_mcasp_gpio_set(struct gpio_chip *chip, unsigned offset,
2024 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2027 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2029 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDOUT_REG, BIT(offset));
2032 static int davinci_mcasp_gpio_direction_in(struct gpio_chip *chip,
2035 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2038 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PFUNC_REG);
2039 if (!(val & BIT(offset))) {
2040 /* Set the direction to input */
2041 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, BIT(offset));
2043 /* Set the pin as GPIO pin */
2044 mcasp_set_bits(mcasp, DAVINCI_MCASP_PFUNC_REG, BIT(offset));
2050 static int davinci_mcasp_gpio_get(struct gpio_chip *chip, unsigned offset)
2052 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2055 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDSET_REG);
2056 if (val & BIT(offset))
2062 static int davinci_mcasp_gpio_get_direction(struct gpio_chip *chip,
2065 struct davinci_mcasp *mcasp = gpiochip_get_data(chip);
2068 val = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
2069 if (val & BIT(offset))
2075 static const struct gpio_chip davinci_mcasp_template_chip = {
2076 .owner = THIS_MODULE,
2077 .request = davinci_mcasp_gpio_request,
2078 .free = davinci_mcasp_gpio_free,
2079 .direction_output = davinci_mcasp_gpio_direction_out,
2080 .set = davinci_mcasp_gpio_set,
2081 .direction_input = davinci_mcasp_gpio_direction_in,
2082 .get = davinci_mcasp_gpio_get,
2083 .get_direction = davinci_mcasp_gpio_get_direction,
2088 static int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2090 if (!of_property_read_bool(mcasp->dev->of_node, "gpio-controller"))
2093 mcasp->gpio_chip = davinci_mcasp_template_chip;
2094 mcasp->gpio_chip.label = dev_name(mcasp->dev);
2095 mcasp->gpio_chip.parent = mcasp->dev;
2096 #ifdef CONFIG_OF_GPIO
2097 mcasp->gpio_chip.of_node = mcasp->dev->of_node;
2100 return devm_gpiochip_add_data(mcasp->dev, &mcasp->gpio_chip, mcasp);
2103 #else /* CONFIG_GPIOLIB */
2104 static inline int davinci_mcasp_init_gpiochip(struct davinci_mcasp *mcasp)
2108 #endif /* CONFIG_GPIOLIB */
2110 static int davinci_mcasp_get_dt_params(struct davinci_mcasp *mcasp)
2112 struct device_node *np = mcasp->dev->of_node;
2119 ret = of_property_read_u32(np, "auxclk-fs-ratio", &val);
2121 mcasp->auxclk_fs_ratio = val;
2126 static int davinci_mcasp_probe(struct platform_device *pdev)
2128 struct snd_dmaengine_dai_dma_data *dma_data;
2129 struct resource *mem, *res, *dat;
2130 struct davinci_mcasp_pdata *pdata;
2131 struct davinci_mcasp *mcasp;
2137 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
2138 dev_err(&pdev->dev, "No platform data supplied\n");
2142 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
2147 pdata = davinci_mcasp_set_pdata_from_of(pdev);
2149 dev_err(&pdev->dev, "no platform data\n");
2153 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
2155 dev_warn(mcasp->dev,
2156 "\"mpu\" mem resource not found, using index 0\n");
2157 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2159 dev_err(&pdev->dev, "no mem resource?\n");
2164 mcasp->base = devm_ioremap_resource(&pdev->dev, mem);
2165 if (IS_ERR(mcasp->base))
2166 return PTR_ERR(mcasp->base);
2168 pm_runtime_enable(&pdev->dev);
2170 mcasp->op_mode = pdata->op_mode;
2171 /* sanity check for tdm slots parameter */
2172 if (mcasp->op_mode == DAVINCI_MCASP_IIS_MODE) {
2173 if (pdata->tdm_slots < 2) {
2174 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2176 mcasp->tdm_slots = 2;
2177 } else if (pdata->tdm_slots > 32) {
2178 dev_err(&pdev->dev, "invalid tdm slots: %d\n",
2180 mcasp->tdm_slots = 32;
2182 mcasp->tdm_slots = pdata->tdm_slots;
2186 mcasp->num_serializer = pdata->num_serializer;
2188 mcasp->context.xrsr_regs = devm_kcalloc(&pdev->dev,
2189 mcasp->num_serializer, sizeof(u32),
2191 if (!mcasp->context.xrsr_regs) {
2196 mcasp->serial_dir = pdata->serial_dir;
2197 mcasp->version = pdata->version;
2198 mcasp->txnumevt = pdata->txnumevt;
2199 mcasp->rxnumevt = pdata->rxnumevt;
2200 mcasp->dismod = pdata->dismod;
2202 mcasp->dev = &pdev->dev;
2204 irq = platform_get_irq_byname(pdev, "common");
2206 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_common",
2207 dev_name(&pdev->dev));
2212 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2213 davinci_mcasp_common_irq_handler,
2214 IRQF_ONESHOT | IRQF_SHARED,
2217 dev_err(&pdev->dev, "common IRQ request failed\n");
2221 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2222 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2225 irq = platform_get_irq_byname(pdev, "rx");
2227 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_rx",
2228 dev_name(&pdev->dev));
2233 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2234 davinci_mcasp_rx_irq_handler,
2235 IRQF_ONESHOT, irq_name, mcasp);
2237 dev_err(&pdev->dev, "RX IRQ request failed\n");
2241 mcasp->irq_request[SNDRV_PCM_STREAM_CAPTURE] = ROVRN;
2244 irq = platform_get_irq_byname(pdev, "tx");
2246 irq_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s_tx",
2247 dev_name(&pdev->dev));
2252 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
2253 davinci_mcasp_tx_irq_handler,
2254 IRQF_ONESHOT, irq_name, mcasp);
2256 dev_err(&pdev->dev, "TX IRQ request failed\n");
2260 mcasp->irq_request[SNDRV_PCM_STREAM_PLAYBACK] = XUNDRN;
2263 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
2265 mcasp->dat_port = true;
2267 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
2269 dma_data->addr = dat->start;
2271 dma_data->addr = mem->start + davinci_mcasp_txdma_offset(pdata);
2273 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_PLAYBACK];
2274 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
2278 *dma = pdata->tx_dma_channel;
2280 /* dmaengine filter data for DT and non-DT boot */
2281 if (pdev->dev.of_node)
2282 dma_data->filter_data = "tx";
2284 dma_data->filter_data = dma;
2286 /* RX is not valid in DIT mode */
2287 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
2288 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
2290 dma_data->addr = dat->start;
2293 mem->start + davinci_mcasp_rxdma_offset(pdata);
2295 dma = &mcasp->dma_request[SNDRV_PCM_STREAM_CAPTURE];
2296 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
2300 *dma = pdata->rx_dma_channel;
2302 /* dmaengine filter data for DT and non-DT boot */
2303 if (pdev->dev.of_node)
2304 dma_data->filter_data = "rx";
2306 dma_data->filter_data = dma;
2309 if (mcasp->version < MCASP_VERSION_3) {
2310 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
2311 /* dma_params->dma_addr is pointing to the data port address */
2312 mcasp->dat_port = true;
2314 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
2317 /* Allocate memory for long enough list for all possible
2318 * scenarios. Maximum number tdm slots is 32 and there cannot
2319 * be more serializers than given in the configuration. The
2320 * serializer directions could be taken into account, but it
2321 * would make code much more complex and save only couple of
2324 mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list =
2325 devm_kcalloc(mcasp->dev,
2326 32 + mcasp->num_serializer - 1,
2327 sizeof(unsigned int),
2330 mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list =
2331 devm_kcalloc(mcasp->dev,
2332 32 + mcasp->num_serializer - 1,
2333 sizeof(unsigned int),
2336 if (!mcasp->chconstr[SNDRV_PCM_STREAM_PLAYBACK].list ||
2337 !mcasp->chconstr[SNDRV_PCM_STREAM_CAPTURE].list) {
2342 ret = davinci_mcasp_set_ch_constraints(mcasp);
2346 dev_set_drvdata(&pdev->dev, mcasp);
2348 mcasp_reparent_fck(pdev);
2350 /* All PINS as McASP */
2351 pm_runtime_get_sync(mcasp->dev);
2352 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
2353 pm_runtime_put(mcasp->dev);
2355 ret = davinci_mcasp_init_gpiochip(mcasp);
2359 ret = davinci_mcasp_get_dt_params(mcasp);
2363 ret = devm_snd_soc_register_component(&pdev->dev,
2364 &davinci_mcasp_component,
2365 &davinci_mcasp_dai[pdata->op_mode], 1);
2370 ret = davinci_mcasp_get_dma_type(mcasp);
2373 ret = edma_pcm_platform_register(&pdev->dev);
2376 ret = sdma_pcm_platform_register(&pdev->dev, "tx", "rx");
2379 ret = udma_pcm_platform_register(&pdev->dev);
2382 dev_err(&pdev->dev, "No DMA controller found (%d)\n", ret);
2389 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
2396 pm_runtime_disable(&pdev->dev);
2400 static int davinci_mcasp_remove(struct platform_device *pdev)
2402 pm_runtime_disable(&pdev->dev);
2408 static int davinci_mcasp_runtime_suspend(struct device *dev)
2410 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2411 struct davinci_mcasp_context *context = &mcasp->context;
2415 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2416 context->config_regs[i] = mcasp_get_reg(mcasp, context_regs[i]);
2418 if (mcasp->txnumevt) {
2419 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2420 context->afifo_regs[0] = mcasp_get_reg(mcasp, reg);
2422 if (mcasp->rxnumevt) {
2423 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2424 context->afifo_regs[1] = mcasp_get_reg(mcasp, reg);
2427 for (i = 0; i < mcasp->num_serializer; i++)
2428 context->xrsr_regs[i] = mcasp_get_reg(mcasp,
2429 DAVINCI_MCASP_XRSRCTL_REG(i));
2434 static int davinci_mcasp_runtime_resume(struct device *dev)
2436 struct davinci_mcasp *mcasp = dev_get_drvdata(dev);
2437 struct davinci_mcasp_context *context = &mcasp->context;
2441 for (i = 0; i < ARRAY_SIZE(context_regs); i++)
2442 mcasp_set_reg(mcasp, context_regs[i], context->config_regs[i]);
2444 if (mcasp->txnumevt) {
2445 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
2446 mcasp_set_reg(mcasp, reg, context->afifo_regs[0]);
2448 if (mcasp->rxnumevt) {
2449 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
2450 mcasp_set_reg(mcasp, reg, context->afifo_regs[1]);
2453 for (i = 0; i < mcasp->num_serializer; i++)
2454 mcasp_set_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
2455 context->xrsr_regs[i]);
2462 static const struct dev_pm_ops davinci_mcasp_pm_ops = {
2463 SET_RUNTIME_PM_OPS(davinci_mcasp_runtime_suspend,
2464 davinci_mcasp_runtime_resume,
2468 static struct platform_driver davinci_mcasp_driver = {
2469 .probe = davinci_mcasp_probe,
2470 .remove = davinci_mcasp_remove,
2472 .name = "davinci-mcasp",
2473 .pm = &davinci_mcasp_pm_ops,
2474 .of_match_table = mcasp_dt_ids,
2478 module_platform_driver(davinci_mcasp_driver);
2480 MODULE_AUTHOR("Steve Chen");
2481 MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
2482 MODULE_LICENSE("GPL");