sound/soc/tegra/tegra20_spdif.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * tegra20_spdif.c - Tegra20 SPDIF driver
   4  *
   5  * Author: Stephen Warren <swarren@nvidia.com>
   6  * Copyright (C) 2011-2012 - NVIDIA, Inc.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/slab.h>
  18 #include <sound/core.h>
  19 #include <sound/pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/soc.h>
  22 #include <sound/dmaengine_pcm.h>
  23
  24 #include "tegra20_spdif.h"
  25
  26 static __maybe_unused int tegra20_spdif_runtime_suspend(struct device *dev)
  27 {
  28         struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  29
  30         clk_disable_unprepare(spdif->clk_spdif_out);
  31
  32         return 0;
  33 }
  34
  35 static __maybe_unused int tegra20_spdif_runtime_resume(struct device *dev)
  36 {
  37         struct tegra20_spdif *spdif = dev_get_drvdata(dev);
  38         int ret;
  39
  40         ret = clk_prepare_enable(spdif->clk_spdif_out);
  41         if (ret) {
  42                 dev_err(dev, "clk_enable failed: %d\n", ret);
  43                 return ret;
  44         }
  45
  46         return 0;
  47 }
  48
  49 static int tegra20_spdif_hw_params(struct snd_pcm_substream *substream,
  50                                    struct snd_pcm_hw_params *params,
  51                                    struct snd_soc_dai *dai)
  52 {
  53         struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
  54         unsigned int mask = 0, val = 0;
  55         int ret, spdifclock;
  56
  57         mask |= TEGRA20_SPDIF_CTRL_PACK |
  58                 TEGRA20_SPDIF_CTRL_BIT_MODE_MASK;
  59         switch (params_format(params)) {
  60         case SNDRV_PCM_FORMAT_S16_LE:
  61                 val |= TEGRA20_SPDIF_CTRL_PACK |
  62                        TEGRA20_SPDIF_CTRL_BIT_MODE_16BIT;
  63                 break;
  64         default:
  65                 return -EINVAL;
  66         }
  67
  68         regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL, mask, val);
  69
  70         /*
  71          * FIFO trigger level must be bigger than DMA burst or equal to it,
  72          * otherwise data is discarded on overflow.
  73          */
  74         regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_DATA_FIFO_CSR,
  75                            TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_MASK,
  76                            TEGRA20_SPDIF_DATA_FIFO_CSR_TX_ATN_LVL_TU4_WORD_FULL);
  77
  78         switch (params_rate(params)) {
  79         case 32000:
  80                 spdifclock = 4096000;
  81                 break;
  82         case 44100:
  83                 spdifclock = 5644800;
  84                 break;
  85         case 48000:
  86                 spdifclock = 6144000;
  87                 break;
  88         case 88200:
  89                 spdifclock = 11289600;
  90                 break;
  91         case 96000:
  92                 spdifclock = 12288000;
  93                 break;
  94         case 176400:
  95                 spdifclock = 22579200;
  96                 break;
  97         case 192000:
  98                 spdifclock = 24576000;
  99                 break;
 100         default:
 101                 return -EINVAL;
 102         }
 103
 104         ret = clk_set_rate(spdif->clk_spdif_out, spdifclock);
 105         if (ret) {
 106                 dev_err(dai->dev, "Can't set SPDIF clock rate: %d\n", ret);
 107                 return ret;
 108         }
 109
 110         return 0;
 111 }
 112
 113 static void tegra20_spdif_start_playback(struct tegra20_spdif *spdif)
 114 {
 115         regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
 116                            TEGRA20_SPDIF_CTRL_TX_EN,
 117                            TEGRA20_SPDIF_CTRL_TX_EN);
 118 }
 119
 120 static void tegra20_spdif_stop_playback(struct tegra20_spdif *spdif)
 121 {
 122         regmap_update_bits(spdif->regmap, TEGRA20_SPDIF_CTRL,
 123                            TEGRA20_SPDIF_CTRL_TX_EN, 0);
 124 }
 125
 126 static int tegra20_spdif_trigger(struct snd_pcm_substream *substream, int cmd,
 127                                  struct snd_soc_dai *dai)
 128 {
 129         struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
 130
 131         switch (cmd) {
 132         case SNDRV_PCM_TRIGGER_START:
 133         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 134         case SNDRV_PCM_TRIGGER_RESUME:
 135                 tegra20_spdif_start_playback(spdif);
 136                 break;
 137         case SNDRV_PCM_TRIGGER_STOP:
 138         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 139         case SNDRV_PCM_TRIGGER_SUSPEND:
 140                 tegra20_spdif_stop_playback(spdif);
 141                 break;
 142         default:
 143                 return -EINVAL;
 144         }
 145
 146         return 0;
 147 }
 148
 149 static int tegra20_spdif_probe(struct snd_soc_dai *dai)
 150 {
 151         struct tegra20_spdif *spdif = dev_get_drvdata(dai->dev);
 152
 153         dai->capture_dma_data = NULL;
 154         dai->playback_dma_data = &spdif->playback_dma_data;
 155
 156         return 0;
 157 }
 158
 159 static const struct snd_soc_dai_ops tegra20_spdif_dai_ops = {
 160         .hw_params = tegra20_spdif_hw_params,
 161         .trigger = tegra20_spdif_trigger,
 162 };
 163
 164 static struct snd_soc_dai_driver tegra20_spdif_dai = {
 165         .name = "tegra20-spdif",
 166         .probe = tegra20_spdif_probe,
 167         .playback = {
 168                 .stream_name = "Playback",
 169                 .channels_min = 2,
 170                 .channels_max = 2,
 171                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 172                          SNDRV_PCM_RATE_48000,
 173                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 174         },
 175         .ops = &tegra20_spdif_dai_ops,
 176 };
 177
 178 static const struct snd_soc_component_driver tegra20_spdif_component = {
 179         .name = "tegra20-spdif",
 180 };
 181
 182 static bool tegra20_spdif_wr_rd_reg(struct device *dev, unsigned int reg)
 183 {
 184         switch (reg) {
 185         case TEGRA20_SPDIF_CTRL:
 186         case TEGRA20_SPDIF_STATUS:
 187         case TEGRA20_SPDIF_STROBE_CTRL:
 188         case TEGRA20_SPDIF_DATA_FIFO_CSR:
 189         case TEGRA20_SPDIF_DATA_OUT:
 190         case TEGRA20_SPDIF_DATA_IN:
 191         case TEGRA20_SPDIF_CH_STA_RX_A:
 192         case TEGRA20_SPDIF_CH_STA_RX_B:
 193         case TEGRA20_SPDIF_CH_STA_RX_C:
 194         case TEGRA20_SPDIF_CH_STA_RX_D:
 195         case TEGRA20_SPDIF_CH_STA_RX_E:
 196         case TEGRA20_SPDIF_CH_STA_RX_F:
 197         case TEGRA20_SPDIF_CH_STA_TX_A:
 198         case TEGRA20_SPDIF_CH_STA_TX_B:
 199         case TEGRA20_SPDIF_CH_STA_TX_C:
 200         case TEGRA20_SPDIF_CH_STA_TX_D:
 201         case TEGRA20_SPDIF_CH_STA_TX_E:
 202         case TEGRA20_SPDIF_CH_STA_TX_F:
 203         case TEGRA20_SPDIF_USR_STA_RX_A:
 204         case TEGRA20_SPDIF_USR_DAT_TX_A:
 205                 return true;
 206         default:
 207                 return false;
 208         }
 209 }
 210
 211 static bool tegra20_spdif_volatile_reg(struct device *dev, unsigned int reg)
 212 {
 213         switch (reg) {
 214         case TEGRA20_SPDIF_STATUS:
 215         case TEGRA20_SPDIF_DATA_FIFO_CSR:
 216         case TEGRA20_SPDIF_DATA_OUT:
 217         case TEGRA20_SPDIF_DATA_IN:
 218         case TEGRA20_SPDIF_CH_STA_RX_A:
 219         case TEGRA20_SPDIF_CH_STA_RX_B:
 220         case TEGRA20_SPDIF_CH_STA_RX_C:
 221         case TEGRA20_SPDIF_CH_STA_RX_D:
 222         case TEGRA20_SPDIF_CH_STA_RX_E:
 223         case TEGRA20_SPDIF_CH_STA_RX_F:
 224         case TEGRA20_SPDIF_USR_STA_RX_A:
 225         case TEGRA20_SPDIF_USR_DAT_TX_A:
 226                 return true;
 227         default:
 228                 return false;
 229         }
 230 }
 231
 232 static bool tegra20_spdif_precious_reg(struct device *dev, unsigned int reg)
 233 {
 234         switch (reg) {
 235         case TEGRA20_SPDIF_DATA_OUT:
 236         case TEGRA20_SPDIF_DATA_IN:
 237         case TEGRA20_SPDIF_USR_STA_RX_A:
 238         case TEGRA20_SPDIF_USR_DAT_TX_A:
 239                 return true;
 240         default:
 241                 return false;
 242         }
 243 }
 244
 245 static const struct regmap_config tegra20_spdif_regmap_config = {
 246         .reg_bits = 32,
 247         .reg_stride = 4,
 248         .val_bits = 32,
 249         .max_register = TEGRA20_SPDIF_USR_DAT_TX_A,
 250         .writeable_reg = tegra20_spdif_wr_rd_reg,
 251         .readable_reg = tegra20_spdif_wr_rd_reg,
 252         .volatile_reg = tegra20_spdif_volatile_reg,
 253         .precious_reg = tegra20_spdif_precious_reg,
 254         .cache_type = REGCACHE_FLAT,
 255 };
 256
 257 static int tegra20_spdif_platform_probe(struct platform_device *pdev)
 258 {
 259         struct tegra20_spdif *spdif;
 260         struct resource *mem;
 261         void __iomem *regs;
 262         int ret;
 263
 264         spdif = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_spdif),
 265                              GFP_KERNEL);
 266         if (!spdif)
 267                 return -ENOMEM;
 268
 269         dev_set_drvdata(&pdev->dev, spdif);
 270
 271         spdif->clk_spdif_out = devm_clk_get(&pdev->dev, "out");
 272         if (IS_ERR(spdif->clk_spdif_out)) {
 273                 dev_err(&pdev->dev, "Could not retrieve spdif clock\n");
 274                 return PTR_ERR(spdif->clk_spdif_out);
 275         }
 276
 277         regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
 278         if (IS_ERR(regs))
 279                 return PTR_ERR(regs);
 280
 281         spdif->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
 282                                               &tegra20_spdif_regmap_config);
 283         if (IS_ERR(spdif->regmap)) {
 284                 dev_err(&pdev->dev, "regmap init failed\n");
 285                 return PTR_ERR(spdif->regmap);
 286         }
 287
 288         spdif->playback_dma_data.addr = mem->start + TEGRA20_SPDIF_DATA_OUT;
 289         spdif->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 290         spdif->playback_dma_data.maxburst = 4;
 291
 292         pm_runtime_enable(&pdev->dev);
 293
 294         ret = snd_soc_register_component(&pdev->dev, &tegra20_spdif_component,
 295                                          &tegra20_spdif_dai, 1);
 296         if (ret) {
 297                 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
 298                 goto err_pm_disable;
 299         }
 300
 301         ret = tegra_pcm_platform_register(&pdev->dev);
 302         if (ret) {
 303                 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
 304                 goto err_unregister_component;
 305         }
 306
 307         return 0;
 308
 309 err_unregister_component:
 310         snd_soc_unregister_component(&pdev->dev);
 311 err_pm_disable:
 312         pm_runtime_disable(&pdev->dev);
 313
 314         return ret;
 315 }
 316
 317 static int tegra20_spdif_platform_remove(struct platform_device *pdev)
 318 {
 319         tegra_pcm_platform_unregister(&pdev->dev);
 320         snd_soc_unregister_component(&pdev->dev);
 321
 322         pm_runtime_disable(&pdev->dev);
 323
 324         return 0;
 325 }
 326
 327 static const struct dev_pm_ops tegra20_spdif_pm_ops = {
 328         SET_RUNTIME_PM_OPS(tegra20_spdif_runtime_suspend,
 329                            tegra20_spdif_runtime_resume, NULL)
 330 };
 331
 332 static const struct of_device_id tegra20_spdif_of_match[] = {
 333         { .compatible = "nvidia,tegra20-spdif", },
 334         {},
 335 };
 336 MODULE_DEVICE_TABLE(of, tegra20_spdif_of_match);
 337
 338 static struct platform_driver tegra20_spdif_driver = {
 339         .driver = {
 340                 .name = "tegra20-spdif",
 341                 .pm = &tegra20_spdif_pm_ops,
 342                 .of_match_table = tegra20_spdif_of_match,
 343         },
 344         .probe = tegra20_spdif_platform_probe,
 345         .remove = tegra20_spdif_platform_remove,
 346 };
 347 module_platform_driver(tegra20_spdif_driver);
 348
 349 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
 350 MODULE_DESCRIPTION("Tegra20 SPDIF ASoC driver");
 351 MODULE_LICENSE("GPL");