sound/soc/sunxi/sun4i-i2s.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2015 Andrea Venturi
   4  * Andrea Venturi <be17068@iperbole.bo.it>
   5  *
   6  * Copyright (C) 2016 Maxime Ripard
   7  * Maxime Ripard <maxime.ripard@free-electrons.com>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/dmaengine.h>
  12 #include <linux/module.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17 #include <linux/reset.h>
  18
  19 #include <sound/dmaengine_pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/soc.h>
  22 #include <sound/soc-dai.h>
  23
  24 #define SUN4I_I2S_CTRL_REG              0x00
  25 #define SUN4I_I2S_CTRL_SDO_EN_MASK              GENMASK(11, 8)
  26 #define SUN4I_I2S_CTRL_SDO_EN(sdo)                      BIT(8 + (sdo))
  27 #define SUN4I_I2S_CTRL_MODE_MASK                BIT(5)
  28 #define SUN4I_I2S_CTRL_MODE_SLAVE                       (1 << 5)
  29 #define SUN4I_I2S_CTRL_MODE_MASTER                      (0 << 5)
  30 #define SUN4I_I2S_CTRL_TX_EN                    BIT(2)
  31 #define SUN4I_I2S_CTRL_RX_EN                    BIT(1)
  32 #define SUN4I_I2S_CTRL_GL_EN                    BIT(0)
  33
  34 #define SUN4I_I2S_FMT0_REG              0x04
  35 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK      BIT(7)
  36 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED          (1 << 7)
  37 #define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL            (0 << 7)
  38 #define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK       BIT(6)
  39 #define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED           (1 << 6)
  40 #define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL             (0 << 6)
  41 #define SUN4I_I2S_FMT0_SR_MASK                  GENMASK(5, 4)
  42 #define SUN4I_I2S_FMT0_SR(sr)                           ((sr) << 4)
  43 #define SUN4I_I2S_FMT0_WSS_MASK                 GENMASK(3, 2)
  44 #define SUN4I_I2S_FMT0_WSS(wss)                         ((wss) << 2)
  45 #define SUN4I_I2S_FMT0_FMT_MASK                 GENMASK(1, 0)
  46 #define SUN4I_I2S_FMT0_FMT_RIGHT_J                      (2 << 0)
  47 #define SUN4I_I2S_FMT0_FMT_LEFT_J                       (1 << 0)
  48 #define SUN4I_I2S_FMT0_FMT_I2S                          (0 << 0)
  49 #define SUN4I_I2S_FMT0_POLARITY_INVERTED                (1)
  50 #define SUN4I_I2S_FMT0_POLARITY_NORMAL                  (0)
  51
  52 #define SUN4I_I2S_FMT1_REG              0x08
  53 #define SUN4I_I2S_FIFO_TX_REG           0x0c
  54 #define SUN4I_I2S_FIFO_RX_REG           0x10
  55
  56 #define SUN4I_I2S_FIFO_CTRL_REG         0x14
  57 #define SUN4I_I2S_FIFO_CTRL_FLUSH_TX            BIT(25)
  58 #define SUN4I_I2S_FIFO_CTRL_FLUSH_RX            BIT(24)
  59 #define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK        BIT(2)
  60 #define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode)               ((mode) << 2)
  61 #define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK        GENMASK(1, 0)
  62 #define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode)               (mode)
  63
  64 #define SUN4I_I2S_FIFO_STA_REG          0x18
  65
  66 #define SUN4I_I2S_DMA_INT_CTRL_REG      0x1c
  67 #define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN        BIT(7)
  68 #define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN        BIT(3)
  69
  70 #define SUN4I_I2S_INT_STA_REG           0x20
  71
  72 #define SUN4I_I2S_CLK_DIV_REG           0x24
  73 #define SUN4I_I2S_CLK_DIV_MCLK_EN               BIT(7)
  74 #define SUN4I_I2S_CLK_DIV_BCLK_MASK             GENMASK(6, 4)
  75 #define SUN4I_I2S_CLK_DIV_BCLK(bclk)                    ((bclk) << 4)
  76 #define SUN4I_I2S_CLK_DIV_MCLK_MASK             GENMASK(3, 0)
  77 #define SUN4I_I2S_CLK_DIV_MCLK(mclk)                    ((mclk) << 0)
  78
  79 #define SUN4I_I2S_RX_CNT_REG            0x28
  80 #define SUN4I_I2S_TX_CNT_REG            0x2c
  81
  82 #define SUN4I_I2S_TX_CHAN_SEL_REG       0x30
  83 #define SUN4I_I2S_CHAN_SEL(num_chan)            (((num_chan) - 1) << 0)
  84
  85 #define SUN4I_I2S_TX_CHAN_MAP_REG       0x34
  86 #define SUN4I_I2S_TX_CHAN_MAP(chan, sample)     ((sample) << (chan << 2))
  87
  88 #define SUN4I_I2S_RX_CHAN_SEL_REG       0x38
  89 #define SUN4I_I2S_RX_CHAN_MAP_REG       0x3c
  90
  91 /* Defines required for sun8i-h3 support */
  92 #define SUN8I_I2S_CTRL_BCLK_OUT                 BIT(18)
  93 #define SUN8I_I2S_CTRL_LRCK_OUT                 BIT(17)
  94
  95 #define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK         GENMASK(17, 8)
  96 #define SUN8I_I2S_FMT0_LRCK_PERIOD(period)      ((period - 1) << 8)
  97
  98 #define SUN8I_I2S_INT_STA_REG           0x0c
  99 #define SUN8I_I2S_FIFO_TX_REG           0x20
 100
 101 #define SUN8I_I2S_CHAN_CFG_REG          0x30
 102 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK     GENMASK(6, 4)
 103 #define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan)    ((chan - 1) << 4)
 104 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK     GENMASK(2, 0)
 105 #define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan)    (chan - 1)
 106
 107 #define SUN8I_I2S_TX_CHAN_MAP_REG       0x44
 108 #define SUN8I_I2S_TX_CHAN_SEL_REG       0x34
 109 #define SUN8I_I2S_TX_CHAN_OFFSET_MASK           GENMASK(13, 12)
 110 #define SUN8I_I2S_TX_CHAN_OFFSET(offset)        (offset << 12)
 111 #define SUN8I_I2S_TX_CHAN_EN_MASK               GENMASK(11, 4)
 112 #define SUN8I_I2S_TX_CHAN_EN(num_chan)          (((1 << num_chan) - 1) << 4)
 113
 114 #define SUN8I_I2S_RX_CHAN_SEL_REG       0x54
 115 #define SUN8I_I2S_RX_CHAN_MAP_REG       0x58
 116
 117 struct sun4i_i2s;
 118
 119 /**
 120  * struct sun4i_i2s_quirks - Differences between SoC variants.
 121  *
 122  * @has_reset: SoC needs reset deasserted.
 123  * @has_slave_select_bit: SoC has a bit to enable slave mode.
 124  * @has_fmt_set_lrck_period: SoC requires lrclk period to be set.
 125  * @has_chcfg: tx and rx slot number need to be set.
 126  * @has_chsel_tx_chen: SoC requires that the tx channels are enabled.
 127  * @has_chsel_offset: SoC uses offset for selecting dai operational mode.
 128  * @reg_offset_txdata: offset of the tx fifo.
 129  * @sun4i_i2s_regmap: regmap config to use.
 130  * @mclk_offset: Value by which mclkdiv needs to be adjusted.
 131  * @bclk_offset: Value by which bclkdiv needs to be adjusted.
 132  * @field_clkdiv_mclk_en: regmap field to enable mclk output.
 133  * @field_fmt_wss: regmap field to set word select size.
 134  * @field_fmt_sr: regmap field to set sample resolution.
 135  * @field_fmt_bclk: regmap field to set clk polarity.
 136  * @field_fmt_lrclk: regmap field to set frame polarity.
 137  * @field_fmt_mode: regmap field to set the operational mode.
 138  * @field_txchanmap: location of the tx channel mapping register.
 139  * @field_rxchanmap: location of the rx channel mapping register.
 140  * @field_txchansel: location of the tx channel select bit fields.
 141  * @field_rxchansel: location of the rx channel select bit fields.
 142  */
 143 struct sun4i_i2s_quirks {
 144         bool                            has_reset;
 145         bool                            has_slave_select_bit;
 146         bool                            has_fmt_set_lrck_period;
 147         bool                            has_chcfg;
 148         bool                            has_chsel_tx_chen;
 149         bool                            has_chsel_offset;
 150         unsigned int                    reg_offset_txdata;      /* TX FIFO */
 151         const struct regmap_config      *sun4i_i2s_regmap;
 152         unsigned int                    mclk_offset;
 153         unsigned int                    bclk_offset;
 154
 155         /* Register fields for i2s */
 156         struct reg_field                field_clkdiv_mclk_en;
 157         struct reg_field                field_fmt_wss;
 158         struct reg_field                field_fmt_sr;
 159         struct reg_field                field_fmt_bclk;
 160         struct reg_field                field_fmt_lrclk;
 161         struct reg_field                field_fmt_mode;
 162         struct reg_field                field_txchanmap;
 163         struct reg_field                field_rxchanmap;
 164         struct reg_field                field_txchansel;
 165         struct reg_field                field_rxchansel;
 166
 167         s8      (*get_sr)(const struct sun4i_i2s *, int);
 168         s8      (*get_wss)(const struct sun4i_i2s *, int);
 169 };
 170
 171 struct sun4i_i2s {
 172         struct clk      *bus_clk;
 173         struct clk      *mod_clk;
 174         struct regmap   *regmap;
 175         struct reset_control *rst;
 176
 177         unsigned int    mclk_freq;
 178
 179         struct snd_dmaengine_dai_dma_data       capture_dma_data;
 180         struct snd_dmaengine_dai_dma_data       playback_dma_data;
 181
 182         /* Register fields for i2s */
 183         struct regmap_field     *field_clkdiv_mclk_en;
 184         struct regmap_field     *field_fmt_wss;
 185         struct regmap_field     *field_fmt_sr;
 186         struct regmap_field     *field_fmt_bclk;
 187         struct regmap_field     *field_fmt_lrclk;
 188         struct regmap_field     *field_fmt_mode;
 189         struct regmap_field     *field_txchanmap;
 190         struct regmap_field     *field_rxchanmap;
 191         struct regmap_field     *field_txchansel;
 192         struct regmap_field     *field_rxchansel;
 193
 194         const struct sun4i_i2s_quirks   *variant;
 195 };
 196
 197 struct sun4i_i2s_clk_div {
 198         u8      div;
 199         u8      val;
 200 };
 201
 202 static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
 203         { .div = 2, .val = 0 },
 204         { .div = 4, .val = 1 },
 205         { .div = 6, .val = 2 },
 206         { .div = 8, .val = 3 },
 207         { .div = 12, .val = 4 },
 208         { .div = 16, .val = 5 },
 209         /* TODO - extend divide ratio supported by newer SoCs */
 210 };
 211
 212 static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
 213         { .div = 1, .val = 0 },
 214         { .div = 2, .val = 1 },
 215         { .div = 4, .val = 2 },
 216         { .div = 6, .val = 3 },
 217         { .div = 8, .val = 4 },
 218         { .div = 12, .val = 5 },
 219         { .div = 16, .val = 6 },
 220         { .div = 24, .val = 7 },
 221         /* TODO - extend divide ratio supported by newer SoCs */
 222 };
 223
 224 static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
 225                                   unsigned long parent_rate,
 226                                   unsigned int sampling_rate,
 227                                   unsigned int word_size)
 228 {
 229         int div = parent_rate / sampling_rate / word_size / 2;
 230         int i;
 231
 232         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
 233                 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
 234
 235                 if (bdiv->div == div)
 236                         return bdiv->val;
 237         }
 238
 239         return -EINVAL;
 240 }
 241
 242 static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
 243                                   unsigned long parent_rate,
 244                                   unsigned long mclk_rate)
 245 {
 246         int div = parent_rate / mclk_rate;
 247         int i;
 248
 249         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
 250                 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
 251
 252                 if (mdiv->div == div)
 253                         return mdiv->val;
 254         }
 255
 256         return -EINVAL;
 257 }
 258
 259 static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
 260 static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
 261 {
 262         int i;
 263
 264         for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
 265                 if (sun4i_i2s_oversample_rates[i] == oversample)
 266                         return true;
 267
 268         return false;
 269 }
 270
 271 static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
 272                                   unsigned int rate,
 273                                   unsigned int word_size)
 274 {
 275         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 276         unsigned int oversample_rate, clk_rate;
 277         int bclk_div, mclk_div;
 278         int ret;
 279
 280         switch (rate) {
 281         case 176400:
 282         case 88200:
 283         case 44100:
 284         case 22050:
 285         case 11025:
 286                 clk_rate = 22579200;
 287                 break;
 288
 289         case 192000:
 290         case 128000:
 291         case 96000:
 292         case 64000:
 293         case 48000:
 294         case 32000:
 295         case 24000:
 296         case 16000:
 297         case 12000:
 298         case 8000:
 299                 clk_rate = 24576000;
 300                 break;
 301
 302         default:
 303                 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
 304                 return -EINVAL;
 305         }
 306
 307         ret = clk_set_rate(i2s->mod_clk, clk_rate);
 308         if (ret)
 309                 return ret;
 310
 311         oversample_rate = i2s->mclk_freq / rate;
 312         if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
 313                 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
 314                         oversample_rate);
 315                 return -EINVAL;
 316         }
 317
 318         bclk_div = sun4i_i2s_get_bclk_div(i2s, i2s->mclk_freq,
 319                                           rate, word_size);
 320         if (bclk_div < 0) {
 321                 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
 322                 return -EINVAL;
 323         }
 324
 325         mclk_div = sun4i_i2s_get_mclk_div(i2s, clk_rate, i2s->mclk_freq);
 326         if (mclk_div < 0) {
 327                 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
 328                 return -EINVAL;
 329         }
 330
 331         /* Adjust the clock division values if needed */
 332         bclk_div += i2s->variant->bclk_offset;
 333         mclk_div += i2s->variant->mclk_offset;
 334
 335         regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
 336                      SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
 337                      SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
 338
 339         regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
 340
 341         /* Set sync period */
 342         if (i2s->variant->has_fmt_set_lrck_period)
 343                 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
 344                                    SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
 345                                    SUN8I_I2S_FMT0_LRCK_PERIOD(32));
 346
 347         return 0;
 348 }
 349
 350 static s8 sun4i_i2s_get_sr(const struct sun4i_i2s *i2s, int width)
 351 {
 352         if (width < 16 || width > 24)
 353                 return -EINVAL;
 354
 355         if (width % 4)
 356                 return -EINVAL;
 357
 358         return (width - 16) / 4;
 359 }
 360
 361 static s8 sun4i_i2s_get_wss(const struct sun4i_i2s *i2s, int width)
 362 {
 363         if (width < 16 || width > 32)
 364                 return -EINVAL;
 365
 366         if (width % 4)
 367                 return -EINVAL;
 368
 369         return (width - 16) / 4;
 370 }
 371
 372 static s8 sun8i_i2s_get_sr_wss(const struct sun4i_i2s *i2s, int width)
 373 {
 374         if (width % 4)
 375                 return -EINVAL;
 376
 377         if (width < 8 || width > 32)
 378                 return -EINVAL;
 379
 380         return (width - 8) / 4 + 1;
 381 }
 382
 383 static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
 384                                struct snd_pcm_hw_params *params,
 385                                struct snd_soc_dai *dai)
 386 {
 387         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 388         int sr, wss, channels;
 389         u32 width;
 390
 391         channels = params_channels(params);
 392         if (channels != 2) {
 393                 dev_err(dai->dev, "Unsupported number of channels: %d\n",
 394                         channels);
 395                 return -EINVAL;
 396         }
 397
 398         if (i2s->variant->has_chcfg) {
 399                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 400                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
 401                                    SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
 402                 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
 403                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
 404                                    SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
 405         }
 406
 407         /* Map the channels for playback and capture */
 408         regmap_field_write(i2s->field_txchanmap, 0x76543210);
 409         regmap_field_write(i2s->field_rxchanmap, 0x00003210);
 410
 411         /* Configure the channels */
 412         regmap_field_write(i2s->field_txchansel,
 413                            SUN4I_I2S_CHAN_SEL(channels));
 414         regmap_field_write(i2s->field_rxchansel,
 415                            SUN4I_I2S_CHAN_SEL(channels));
 416
 417         if (i2s->variant->has_chsel_tx_chen)
 418                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 419                                    SUN8I_I2S_TX_CHAN_EN_MASK,
 420                                    SUN8I_I2S_TX_CHAN_EN(channels));
 421
 422         switch (params_physical_width(params)) {
 423         case 16:
 424                 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
 425                 break;
 426         default:
 427                 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
 428                         params_physical_width(params));
 429                 return -EINVAL;
 430         }
 431         i2s->playback_dma_data.addr_width = width;
 432
 433         sr = i2s->variant->get_sr(i2s, params_width(params));
 434         if (sr < 0)
 435                 return -EINVAL;
 436
 437         wss = i2s->variant->get_wss(i2s, params_width(params));
 438         if (wss < 0)
 439                 return -EINVAL;
 440
 441         regmap_field_write(i2s->field_fmt_wss, wss);
 442         regmap_field_write(i2s->field_fmt_sr, sr);
 443
 444         return sun4i_i2s_set_clk_rate(dai, params_rate(params),
 445                                       params_width(params));
 446 }
 447
 448 static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 449 {
 450         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 451         u32 val;
 452         u32 offset = 0;
 453         u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 454         u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
 455
 456         /* DAI Mode */
 457         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 458         case SND_SOC_DAIFMT_I2S:
 459                 val = SUN4I_I2S_FMT0_FMT_I2S;
 460                 offset = 1;
 461                 break;
 462         case SND_SOC_DAIFMT_LEFT_J:
 463                 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
 464                 break;
 465         case SND_SOC_DAIFMT_RIGHT_J:
 466                 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
 467                 break;
 468         default:
 469                 dev_err(dai->dev, "Unsupported format: %d\n",
 470                         fmt & SND_SOC_DAIFMT_FORMAT_MASK);
 471                 return -EINVAL;
 472         }
 473
 474         if (i2s->variant->has_chsel_offset) {
 475                 /*
 476                  * offset being set indicates that we're connected to an i2s
 477                  * device, however offset is only used on the sun8i block and
 478                  * i2s shares the same setting with the LJ format. Increment
 479                  * val so that the bit to value to write is correct.
 480                  */
 481                 if (offset > 0)
 482                         val++;
 483                 /* blck offset determines whether i2s or LJ */
 484                 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
 485                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 486                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 487
 488                 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
 489                                    SUN8I_I2S_TX_CHAN_OFFSET_MASK,
 490                                    SUN8I_I2S_TX_CHAN_OFFSET(offset));
 491         }
 492
 493         regmap_field_write(i2s->field_fmt_mode, val);
 494
 495         /* DAI clock polarity */
 496         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 497         case SND_SOC_DAIFMT_IB_IF:
 498                 /* Invert both clocks */
 499                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 500                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 501                 break;
 502         case SND_SOC_DAIFMT_IB_NF:
 503                 /* Invert bit clock */
 504                 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 505                 break;
 506         case SND_SOC_DAIFMT_NB_IF:
 507                 /* Invert frame clock */
 508                 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
 509                 break;
 510         case SND_SOC_DAIFMT_NB_NF:
 511                 break;
 512         default:
 513                 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
 514                         fmt & SND_SOC_DAIFMT_INV_MASK);
 515                 return -EINVAL;
 516         }
 517
 518         regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
 519         regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
 520
 521         if (i2s->variant->has_slave_select_bit) {
 522                 /* DAI clock master masks */
 523                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 524                 case SND_SOC_DAIFMT_CBS_CFS:
 525                         /* BCLK and LRCLK master */
 526                         val = SUN4I_I2S_CTRL_MODE_MASTER;
 527                         break;
 528                 case SND_SOC_DAIFMT_CBM_CFM:
 529                         /* BCLK and LRCLK slave */
 530                         val = SUN4I_I2S_CTRL_MODE_SLAVE;
 531                         break;
 532                 default:
 533                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 534                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 535                         return -EINVAL;
 536                 }
 537                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 538                                    SUN4I_I2S_CTRL_MODE_MASK,
 539                                    val);
 540         } else {
 541                 /*
 542                  * The newer i2s block does not have a slave select bit,
 543                  * instead the clk pins are configured as inputs.
 544                  */
 545                 /* DAI clock master masks */
 546                 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 547                 case SND_SOC_DAIFMT_CBS_CFS:
 548                         /* BCLK and LRCLK master */
 549                         val = SUN8I_I2S_CTRL_BCLK_OUT |
 550                                 SUN8I_I2S_CTRL_LRCK_OUT;
 551                         break;
 552                 case SND_SOC_DAIFMT_CBM_CFM:
 553                         /* BCLK and LRCLK slave */
 554                         val = 0;
 555                         break;
 556                 default:
 557                         dev_err(dai->dev, "Unsupported slave setting: %d\n",
 558                                 fmt & SND_SOC_DAIFMT_MASTER_MASK);
 559                         return -EINVAL;
 560                 }
 561                 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 562                                    SUN8I_I2S_CTRL_BCLK_OUT |
 563                                    SUN8I_I2S_CTRL_LRCK_OUT,
 564                                    val);
 565         }
 566
 567         /* Set significant bits in our FIFOs */
 568         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 569                            SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
 570                            SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
 571                            SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
 572                            SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
 573         return 0;
 574 }
 575
 576 static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
 577 {
 578         /* Flush RX FIFO */
 579         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 580                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
 581                            SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
 582
 583         /* Clear RX counter */
 584         regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
 585
 586         /* Enable RX Block */
 587         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 588                            SUN4I_I2S_CTRL_RX_EN,
 589                            SUN4I_I2S_CTRL_RX_EN);
 590
 591         /* Enable RX DRQ */
 592         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 593                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 594                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
 595 }
 596
 597 static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
 598 {
 599         /* Flush TX FIFO */
 600         regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
 601                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
 602                            SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
 603
 604         /* Clear TX counter */
 605         regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
 606
 607         /* Enable TX Block */
 608         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 609                            SUN4I_I2S_CTRL_TX_EN,
 610                            SUN4I_I2S_CTRL_TX_EN);
 611
 612         /* Enable TX DRQ */
 613         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 614                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 615                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
 616 }
 617
 618 static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
 619 {
 620         /* Disable RX Block */
 621         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 622                            SUN4I_I2S_CTRL_RX_EN,
 623                            0);
 624
 625         /* Disable RX DRQ */
 626         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 627                            SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
 628                            0);
 629 }
 630
 631 static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
 632 {
 633         /* Disable TX Block */
 634         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 635                            SUN4I_I2S_CTRL_TX_EN,
 636                            0);
 637
 638         /* Disable TX DRQ */
 639         regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
 640                            SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
 641                            0);
 642 }
 643
 644 static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
 645                              struct snd_soc_dai *dai)
 646 {
 647         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 648
 649         switch (cmd) {
 650         case SNDRV_PCM_TRIGGER_START:
 651         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 652         case SNDRV_PCM_TRIGGER_RESUME:
 653                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 654                         sun4i_i2s_start_playback(i2s);
 655                 else
 656                         sun4i_i2s_start_capture(i2s);
 657                 break;
 658
 659         case SNDRV_PCM_TRIGGER_STOP:
 660         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 661         case SNDRV_PCM_TRIGGER_SUSPEND:
 662                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 663                         sun4i_i2s_stop_playback(i2s);
 664                 else
 665                         sun4i_i2s_stop_capture(i2s);
 666                 break;
 667
 668         default:
 669                 return -EINVAL;
 670         }
 671
 672         return 0;
 673 }
 674
 675 static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 676                                 unsigned int freq, int dir)
 677 {
 678         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 679
 680         if (clk_id != 0)
 681                 return -EINVAL;
 682
 683         i2s->mclk_freq = freq;
 684
 685         return 0;
 686 }
 687
 688 static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
 689         .hw_params      = sun4i_i2s_hw_params,
 690         .set_fmt        = sun4i_i2s_set_fmt,
 691         .set_sysclk     = sun4i_i2s_set_sysclk,
 692         .trigger        = sun4i_i2s_trigger,
 693 };
 694
 695 static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
 696 {
 697         struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
 698
 699         snd_soc_dai_init_dma_data(dai,
 700                                   &i2s->playback_dma_data,
 701                                   &i2s->capture_dma_data);
 702
 703         snd_soc_dai_set_drvdata(dai, i2s);
 704
 705         return 0;
 706 }
 707
 708 static struct snd_soc_dai_driver sun4i_i2s_dai = {
 709         .probe = sun4i_i2s_dai_probe,
 710         .capture = {
 711                 .stream_name = "Capture",
 712                 .channels_min = 2,
 713                 .channels_max = 2,
 714                 .rates = SNDRV_PCM_RATE_8000_192000,
 715                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 716         },
 717         .playback = {
 718                 .stream_name = "Playback",
 719                 .channels_min = 2,
 720                 .channels_max = 2,
 721                 .rates = SNDRV_PCM_RATE_8000_192000,
 722                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 723         },
 724         .ops = &sun4i_i2s_dai_ops,
 725         .symmetric_rates = 1,
 726 };
 727
 728 static const struct snd_soc_component_driver sun4i_i2s_component = {
 729         .name   = "sun4i-dai",
 730 };
 731
 732 static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
 733 {
 734         switch (reg) {
 735         case SUN4I_I2S_FIFO_TX_REG:
 736                 return false;
 737
 738         default:
 739                 return true;
 740         }
 741 }
 742
 743 static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
 744 {
 745         switch (reg) {
 746         case SUN4I_I2S_FIFO_RX_REG:
 747         case SUN4I_I2S_FIFO_STA_REG:
 748                 return false;
 749
 750         default:
 751                 return true;
 752         }
 753 }
 754
 755 static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 756 {
 757         switch (reg) {
 758         case SUN4I_I2S_FIFO_RX_REG:
 759         case SUN4I_I2S_INT_STA_REG:
 760         case SUN4I_I2S_RX_CNT_REG:
 761         case SUN4I_I2S_TX_CNT_REG:
 762                 return true;
 763
 764         default:
 765                 return false;
 766         }
 767 }
 768
 769 static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
 770 {
 771         switch (reg) {
 772         case SUN8I_I2S_FIFO_TX_REG:
 773                 return false;
 774
 775         default:
 776                 return true;
 777         }
 778 }
 779
 780 static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
 781 {
 782         if (reg == SUN8I_I2S_INT_STA_REG)
 783                 return true;
 784         if (reg == SUN8I_I2S_FIFO_TX_REG)
 785                 return false;
 786
 787         return sun4i_i2s_volatile_reg(dev, reg);
 788 }
 789
 790 static const struct reg_default sun4i_i2s_reg_defaults[] = {
 791         { SUN4I_I2S_CTRL_REG, 0x00000000 },
 792         { SUN4I_I2S_FMT0_REG, 0x0000000c },
 793         { SUN4I_I2S_FMT1_REG, 0x00004020 },
 794         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 795         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 796         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 797         { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
 798         { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
 799         { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
 800         { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
 801 };
 802
 803 static const struct reg_default sun8i_i2s_reg_defaults[] = {
 804         { SUN4I_I2S_CTRL_REG, 0x00060000 },
 805         { SUN4I_I2S_FMT0_REG, 0x00000033 },
 806         { SUN4I_I2S_FMT1_REG, 0x00000030 },
 807         { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
 808         { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
 809         { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
 810         { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
 811         { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
 812         { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
 813         { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
 814         { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
 815 };
 816
 817 static const struct regmap_config sun4i_i2s_regmap_config = {
 818         .reg_bits       = 32,
 819         .reg_stride     = 4,
 820         .val_bits       = 32,
 821         .max_register   = SUN4I_I2S_RX_CHAN_MAP_REG,
 822
 823         .cache_type     = REGCACHE_FLAT,
 824         .reg_defaults   = sun4i_i2s_reg_defaults,
 825         .num_reg_defaults       = ARRAY_SIZE(sun4i_i2s_reg_defaults),
 826         .writeable_reg  = sun4i_i2s_wr_reg,
 827         .readable_reg   = sun4i_i2s_rd_reg,
 828         .volatile_reg   = sun4i_i2s_volatile_reg,
 829 };
 830
 831 static const struct regmap_config sun8i_i2s_regmap_config = {
 832         .reg_bits       = 32,
 833         .reg_stride     = 4,
 834         .val_bits       = 32,
 835         .max_register   = SUN8I_I2S_RX_CHAN_MAP_REG,
 836         .cache_type     = REGCACHE_FLAT,
 837         .reg_defaults   = sun8i_i2s_reg_defaults,
 838         .num_reg_defaults       = ARRAY_SIZE(sun8i_i2s_reg_defaults),
 839         .writeable_reg  = sun4i_i2s_wr_reg,
 840         .readable_reg   = sun8i_i2s_rd_reg,
 841         .volatile_reg   = sun8i_i2s_volatile_reg,
 842 };
 843
 844 static int sun4i_i2s_runtime_resume(struct device *dev)
 845 {
 846         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 847         int ret;
 848
 849         ret = clk_prepare_enable(i2s->bus_clk);
 850         if (ret) {
 851                 dev_err(dev, "Failed to enable bus clock\n");
 852                 return ret;
 853         }
 854
 855         regcache_cache_only(i2s->regmap, false);
 856         regcache_mark_dirty(i2s->regmap);
 857
 858         ret = regcache_sync(i2s->regmap);
 859         if (ret) {
 860                 dev_err(dev, "Failed to sync regmap cache\n");
 861                 goto err_disable_clk;
 862         }
 863
 864         /* Enable the whole hardware block */
 865         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 866                            SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
 867
 868         /* Enable the first output line */
 869         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 870                            SUN4I_I2S_CTRL_SDO_EN_MASK,
 871                            SUN4I_I2S_CTRL_SDO_EN(0));
 872
 873         ret = clk_prepare_enable(i2s->mod_clk);
 874         if (ret) {
 875                 dev_err(dev, "Failed to enable module clock\n");
 876                 goto err_disable_clk;
 877         }
 878
 879         return 0;
 880
 881 err_disable_clk:
 882         clk_disable_unprepare(i2s->bus_clk);
 883         return ret;
 884 }
 885
 886 static int sun4i_i2s_runtime_suspend(struct device *dev)
 887 {
 888         struct sun4i_i2s *i2s = dev_get_drvdata(dev);
 889
 890         clk_disable_unprepare(i2s->mod_clk);
 891
 892         /* Disable our output lines */
 893         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 894                            SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
 895
 896         /* Disable the whole hardware block */
 897         regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
 898                            SUN4I_I2S_CTRL_GL_EN, 0);
 899
 900         regcache_cache_only(i2s->regmap, true);
 901
 902         clk_disable_unprepare(i2s->bus_clk);
 903
 904         return 0;
 905 }
 906
 907 static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
 908         .has_reset              = false,
 909         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 910         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 911         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 912         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 913         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 914         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 915         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 916         .has_slave_select_bit   = true,
 917         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 918         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 919         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 920         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 921         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 922         .get_sr                 = sun4i_i2s_get_sr,
 923         .get_wss                = sun4i_i2s_get_wss,
 924 };
 925
 926 static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
 927         .has_reset              = true,
 928         .reg_offset_txdata      = SUN4I_I2S_FIFO_TX_REG,
 929         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 930         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 931         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 932         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 933         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 934         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 935         .has_slave_select_bit   = true,
 936         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 937         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 938         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 939         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 940         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 941         .get_sr                 = sun4i_i2s_get_sr,
 942         .get_wss                = sun4i_i2s_get_wss,
 943 };
 944
 945 static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
 946         .has_reset              = true,
 947         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 948         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 949         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 950         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 951         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 952         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 953         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 954         .has_slave_select_bit   = true,
 955         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 956         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
 957         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
 958         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
 959         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
 960         .get_sr                 = sun8i_i2s_get_sr_wss,
 961         .get_wss                = sun8i_i2s_get_sr_wss,
 962 };
 963
 964 static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
 965         .has_reset              = true,
 966         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 967         .sun4i_i2s_regmap       = &sun8i_i2s_regmap_config,
 968         .mclk_offset            = 1,
 969         .bclk_offset            = 2,
 970         .has_fmt_set_lrck_period = true,
 971         .has_chcfg              = true,
 972         .has_chsel_tx_chen      = true,
 973         .has_chsel_offset       = true,
 974         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
 975         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
 976         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
 977         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 978         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
 979         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
 980         .field_txchanmap        = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
 981         .field_rxchanmap        = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
 982         .field_txchansel        = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
 983         .field_rxchansel        = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
 984         .get_sr                 = sun8i_i2s_get_sr_wss,
 985         .get_wss                = sun8i_i2s_get_sr_wss,
 986 };
 987
 988 static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
 989         .has_reset              = true,
 990         .reg_offset_txdata      = SUN8I_I2S_FIFO_TX_REG,
 991         .sun4i_i2s_regmap       = &sun4i_i2s_regmap_config,
 992         .has_slave_select_bit   = true,
 993         .field_clkdiv_mclk_en   = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
 994         .field_fmt_wss          = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
 995         .field_fmt_sr           = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
 996         .field_fmt_bclk         = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
 997         .field_fmt_lrclk        = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
 998         .field_fmt_mode         = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
 999         .field_txchanmap        = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
1000         .field_rxchanmap        = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
1001         .field_txchansel        = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
1002         .field_rxchansel        = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
1003         .get_sr                 = sun4i_i2s_get_sr,
1004         .get_wss                = sun4i_i2s_get_wss,
1005 };
1006
1007 static int sun4i_i2s_init_regmap_fields(struct device *dev,
1008                                         struct sun4i_i2s *i2s)
1009 {
1010         i2s->field_clkdiv_mclk_en =
1011                 devm_regmap_field_alloc(dev, i2s->regmap,
1012                                         i2s->variant->field_clkdiv_mclk_en);
1013         if (IS_ERR(i2s->field_clkdiv_mclk_en))
1014                 return PTR_ERR(i2s->field_clkdiv_mclk_en);
1015
1016         i2s->field_fmt_wss =
1017                         devm_regmap_field_alloc(dev, i2s->regmap,
1018                                                 i2s->variant->field_fmt_wss);
1019         if (IS_ERR(i2s->field_fmt_wss))
1020                 return PTR_ERR(i2s->field_fmt_wss);
1021
1022         i2s->field_fmt_sr =
1023                         devm_regmap_field_alloc(dev, i2s->regmap,
1024                                                 i2s->variant->field_fmt_sr);
1025         if (IS_ERR(i2s->field_fmt_sr))
1026                 return PTR_ERR(i2s->field_fmt_sr);
1027
1028         i2s->field_fmt_bclk =
1029                         devm_regmap_field_alloc(dev, i2s->regmap,
1030                                                 i2s->variant->field_fmt_bclk);
1031         if (IS_ERR(i2s->field_fmt_bclk))
1032                 return PTR_ERR(i2s->field_fmt_bclk);
1033
1034         i2s->field_fmt_lrclk =
1035                         devm_regmap_field_alloc(dev, i2s->regmap,
1036                                                 i2s->variant->field_fmt_lrclk);
1037         if (IS_ERR(i2s->field_fmt_lrclk))
1038                 return PTR_ERR(i2s->field_fmt_lrclk);
1039
1040         i2s->field_fmt_mode =
1041                         devm_regmap_field_alloc(dev, i2s->regmap,
1042                                                 i2s->variant->field_fmt_mode);
1043         if (IS_ERR(i2s->field_fmt_mode))
1044                 return PTR_ERR(i2s->field_fmt_mode);
1045
1046         i2s->field_txchanmap =
1047                         devm_regmap_field_alloc(dev, i2s->regmap,
1048                                                 i2s->variant->field_txchanmap);
1049         if (IS_ERR(i2s->field_txchanmap))
1050                 return PTR_ERR(i2s->field_txchanmap);
1051
1052         i2s->field_rxchanmap =
1053                         devm_regmap_field_alloc(dev, i2s->regmap,
1054                                                 i2s->variant->field_rxchanmap);
1055         if (IS_ERR(i2s->field_rxchanmap))
1056                 return PTR_ERR(i2s->field_rxchanmap);
1057
1058         i2s->field_txchansel =
1059                         devm_regmap_field_alloc(dev, i2s->regmap,
1060                                                 i2s->variant->field_txchansel);
1061         if (IS_ERR(i2s->field_txchansel))
1062                 return PTR_ERR(i2s->field_txchansel);
1063
1064         i2s->field_rxchansel =
1065                         devm_regmap_field_alloc(dev, i2s->regmap,
1066                                                 i2s->variant->field_rxchansel);
1067         return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1068 }
1069
1070 static int sun4i_i2s_probe(struct platform_device *pdev)
1071 {
1072         struct sun4i_i2s *i2s;
1073         struct resource *res;
1074         void __iomem *regs;
1075         int irq, ret;
1076
1077         i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1078         if (!i2s)
1079                 return -ENOMEM;
1080         platform_set_drvdata(pdev, i2s);
1081
1082         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083         regs = devm_ioremap_resource(&pdev->dev, res);
1084         if (IS_ERR(regs))
1085                 return PTR_ERR(regs);
1086
1087         irq = platform_get_irq(pdev, 0);
1088         if (irq < 0)
1089                 return irq;
1090
1091         i2s->variant = of_device_get_match_data(&pdev->dev);
1092         if (!i2s->variant) {
1093                 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1094                 return -ENODEV;
1095         }
1096
1097         i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1098         if (IS_ERR(i2s->bus_clk)) {
1099                 dev_err(&pdev->dev, "Can't get our bus clock\n");
1100                 return PTR_ERR(i2s->bus_clk);
1101         }
1102
1103         i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1104                                             i2s->variant->sun4i_i2s_regmap);
1105         if (IS_ERR(i2s->regmap)) {
1106                 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1107                 return PTR_ERR(i2s->regmap);
1108         }
1109
1110         i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1111         if (IS_ERR(i2s->mod_clk)) {
1112                 dev_err(&pdev->dev, "Can't get our mod clock\n");
1113                 return PTR_ERR(i2s->mod_clk);
1114         }
1115
1116         if (i2s->variant->has_reset) {
1117                 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1118                 if (IS_ERR(i2s->rst)) {
1119                         dev_err(&pdev->dev, "Failed to get reset control\n");
1120                         return PTR_ERR(i2s->rst);
1121                 }
1122         }
1123
1124         if (!IS_ERR(i2s->rst)) {
1125                 ret = reset_control_deassert(i2s->rst);
1126                 if (ret) {
1127                         dev_err(&pdev->dev,
1128                                 "Failed to deassert the reset control\n");
1129                         return -EINVAL;
1130                 }
1131         }
1132
1133         i2s->playback_dma_data.addr = res->start +
1134                                         i2s->variant->reg_offset_txdata;
1135         i2s->playback_dma_data.maxburst = 8;
1136
1137         i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1138         i2s->capture_dma_data.maxburst = 8;
1139
1140         pm_runtime_enable(&pdev->dev);
1141         if (!pm_runtime_enabled(&pdev->dev)) {
1142                 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1143                 if (ret)
1144                         goto err_pm_disable;
1145         }
1146
1147         ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1148         if (ret) {
1149                 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1150                 goto err_suspend;
1151         }
1152
1153         ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1154         if (ret) {
1155                 dev_err(&pdev->dev, "Could not register PCM\n");
1156                 goto err_suspend;
1157         }
1158
1159         ret = devm_snd_soc_register_component(&pdev->dev,
1160                                               &sun4i_i2s_component,
1161                                               &sun4i_i2s_dai, 1);
1162         if (ret) {
1163                 dev_err(&pdev->dev, "Could not register DAI\n");
1164                 goto err_suspend;
1165         }
1166
1167         return 0;
1168
1169 err_suspend:
1170         if (!pm_runtime_status_suspended(&pdev->dev))
1171                 sun4i_i2s_runtime_suspend(&pdev->dev);
1172 err_pm_disable:
1173         pm_runtime_disable(&pdev->dev);
1174         if (!IS_ERR(i2s->rst))
1175                 reset_control_assert(i2s->rst);
1176
1177         return ret;
1178 }
1179
1180 static int sun4i_i2s_remove(struct platform_device *pdev)
1181 {
1182         struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1183
1184         pm_runtime_disable(&pdev->dev);
1185         if (!pm_runtime_status_suspended(&pdev->dev))
1186                 sun4i_i2s_runtime_suspend(&pdev->dev);
1187
1188         if (!IS_ERR(i2s->rst))
1189                 reset_control_assert(i2s->rst);
1190
1191         return 0;
1192 }
1193
1194 static const struct of_device_id sun4i_i2s_match[] = {
1195         {
1196                 .compatible = "allwinner,sun4i-a10-i2s",
1197                 .data = &sun4i_a10_i2s_quirks,
1198         },
1199         {
1200                 .compatible = "allwinner,sun6i-a31-i2s",
1201                 .data = &sun6i_a31_i2s_quirks,
1202         },
1203         {
1204                 .compatible = "allwinner,sun8i-a83t-i2s",
1205                 .data = &sun8i_a83t_i2s_quirks,
1206         },
1207         {
1208                 .compatible = "allwinner,sun8i-h3-i2s",
1209                 .data = &sun8i_h3_i2s_quirks,
1210         },
1211         {
1212                 .compatible = "allwinner,sun50i-a64-codec-i2s",
1213                 .data = &sun50i_a64_codec_i2s_quirks,
1214         },
1215         {}
1216 };
1217 MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1218
1219 static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1220         .runtime_resume         = sun4i_i2s_runtime_resume,
1221         .runtime_suspend        = sun4i_i2s_runtime_suspend,
1222 };
1223
1224 static struct platform_driver sun4i_i2s_driver = {
1225         .probe  = sun4i_i2s_probe,
1226         .remove = sun4i_i2s_remove,
1227         .driver = {
1228                 .name           = "sun4i-i2s",
1229                 .of_match_table = sun4i_i2s_match,
1230                 .pm             = &sun4i_i2s_pm_ops,
1231         },
1232 };
1233 module_platform_driver(sun4i_i2s_driver);
1234
1235 MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1236 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1237 MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1238 MODULE_LICENSE("GPL");