2 * STM32 ALSA SoC Digital Audio Interface (SPDIF-rx) driver.
4 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
5 * Author(s): Olivier Moysan <olivier.moysan@st.com> for STMicroelectronics.
7 * License terms: GPL V2.0.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
19 #include <linux/bitfield.h>
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/delay.h>
23 #include <linux/module.h>
24 #include <linux/of_platform.h>
25 #include <linux/pinctrl/consumer.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
29 #include <sound/dmaengine_pcm.h>
30 #include <sound/pcm_params.h>
32 /* SPDIF-rx Register Map */
33 #define STM32_SPDIFRX_CR 0x00
34 #define STM32_SPDIFRX_IMR 0x04
35 #define STM32_SPDIFRX_SR 0x08
36 #define STM32_SPDIFRX_IFCR 0x0C
37 #define STM32_SPDIFRX_DR 0x10
38 #define STM32_SPDIFRX_CSR 0x14
39 #define STM32_SPDIFRX_DIR 0x18
40 #define STM32_SPDIFRX_VERR 0x3F4
41 #define STM32_SPDIFRX_IDR 0x3F8
42 #define STM32_SPDIFRX_SIDR 0x3FC
44 /* Bit definition for SPDIF_CR register */
45 #define SPDIFRX_CR_SPDIFEN_SHIFT 0
46 #define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
47 #define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
49 #define SPDIFRX_CR_RXDMAEN BIT(2)
50 #define SPDIFRX_CR_RXSTEO BIT(3)
52 #define SPDIFRX_CR_DRFMT_SHIFT 4
53 #define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
54 #define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
56 #define SPDIFRX_CR_PMSK BIT(6)
57 #define SPDIFRX_CR_VMSK BIT(7)
58 #define SPDIFRX_CR_CUMSK BIT(8)
59 #define SPDIFRX_CR_PTMSK BIT(9)
60 #define SPDIFRX_CR_CBDMAEN BIT(10)
61 #define SPDIFRX_CR_CHSEL_SHIFT 11
62 #define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
64 #define SPDIFRX_CR_NBTR_SHIFT 12
65 #define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
66 #define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
68 #define SPDIFRX_CR_WFA BIT(14)
70 #define SPDIFRX_CR_INSEL_SHIFT 16
71 #define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
72 #define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
74 #define SPDIFRX_CR_CKSEN_SHIFT 20
75 #define SPDIFRX_CR_CKSEN BIT(20)
76 #define SPDIFRX_CR_CKSBKPEN BIT(21)
78 /* Bit definition for SPDIFRX_IMR register */
79 #define SPDIFRX_IMR_RXNEI BIT(0)
80 #define SPDIFRX_IMR_CSRNEIE BIT(1)
81 #define SPDIFRX_IMR_PERRIE BIT(2)
82 #define SPDIFRX_IMR_OVRIE BIT(3)
83 #define SPDIFRX_IMR_SBLKIE BIT(4)
84 #define SPDIFRX_IMR_SYNCDIE BIT(5)
85 #define SPDIFRX_IMR_IFEIE BIT(6)
87 #define SPDIFRX_XIMR_MASK GENMASK(6, 0)
89 /* Bit definition for SPDIFRX_SR register */
90 #define SPDIFRX_SR_RXNE BIT(0)
91 #define SPDIFRX_SR_CSRNE BIT(1)
92 #define SPDIFRX_SR_PERR BIT(2)
93 #define SPDIFRX_SR_OVR BIT(3)
94 #define SPDIFRX_SR_SBD BIT(4)
95 #define SPDIFRX_SR_SYNCD BIT(5)
96 #define SPDIFRX_SR_FERR BIT(6)
97 #define SPDIFRX_SR_SERR BIT(7)
98 #define SPDIFRX_SR_TERR BIT(8)
100 #define SPDIFRX_SR_WIDTH5_SHIFT 16
101 #define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
102 #define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
104 /* Bit definition for SPDIFRX_IFCR register */
105 #define SPDIFRX_IFCR_PERRCF BIT(2)
106 #define SPDIFRX_IFCR_OVRCF BIT(3)
107 #define SPDIFRX_IFCR_SBDCF BIT(4)
108 #define SPDIFRX_IFCR_SYNCDCF BIT(5)
110 #define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
112 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b00) */
113 #define SPDIFRX_DR0_DR_SHIFT 0
114 #define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
115 #define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
117 #define SPDIFRX_DR0_PE BIT(24)
119 #define SPDIFRX_DR0_V BIT(25)
120 #define SPDIFRX_DR0_U BIT(26)
121 #define SPDIFRX_DR0_C BIT(27)
123 #define SPDIFRX_DR0_PT_SHIFT 28
124 #define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
125 #define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
127 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b01) */
128 #define SPDIFRX_DR1_PE BIT(0)
129 #define SPDIFRX_DR1_V BIT(1)
130 #define SPDIFRX_DR1_U BIT(2)
131 #define SPDIFRX_DR1_C BIT(3)
133 #define SPDIFRX_DR1_PT_SHIFT 4
134 #define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
135 #define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
137 #define SPDIFRX_DR1_DR_SHIFT 8
138 #define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
139 #define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
141 /* Bit definition for SPDIFRX_DR register (DRFMT = 0b10) */
142 #define SPDIFRX_DR1_DRNL1_SHIFT 0
143 #define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
144 #define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
146 #define SPDIFRX_DR1_DRNL2_SHIFT 16
147 #define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
148 #define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
150 /* Bit definition for SPDIFRX_CSR register */
151 #define SPDIFRX_CSR_USR_SHIFT 0
152 #define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
153 #define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
154 >> SPDIFRX_CSR_USR_SHIFT)
156 #define SPDIFRX_CSR_CS_SHIFT 16
157 #define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
158 #define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
159 >> SPDIFRX_CSR_CS_SHIFT)
161 #define SPDIFRX_CSR_SOB BIT(24)
163 /* Bit definition for SPDIFRX_DIR register */
164 #define SPDIFRX_DIR_THI_SHIFT 0
165 #define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
166 #define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
168 #define SPDIFRX_DIR_TLO_SHIFT 16
169 #define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
170 #define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
172 #define SPDIFRX_SPDIFEN_DISABLE 0x0
173 #define SPDIFRX_SPDIFEN_SYNC 0x1
174 #define SPDIFRX_SPDIFEN_ENABLE 0x3
176 /* Bit definition for SPDIFRX_VERR register */
177 #define SPDIFRX_VERR_MIN_MASK GENMASK(3, 0)
178 #define SPDIFRX_VERR_MAJ_MASK GENMASK(7, 4)
180 /* Bit definition for SPDIFRX_IDR register */
181 #define SPDIFRX_IDR_ID_MASK GENMASK(31, 0)
183 /* Bit definition for SPDIFRX_SIDR register */
184 #define SPDIFRX_SIDR_SID_MASK GENMASK(31, 0)
186 #define SPDIFRX_IPIDR_NUMBER 0x00130041
188 #define SPDIFRX_IN1 0x1
189 #define SPDIFRX_IN2 0x2
190 #define SPDIFRX_IN3 0x3
191 #define SPDIFRX_IN4 0x4
192 #define SPDIFRX_IN5 0x5
193 #define SPDIFRX_IN6 0x6
194 #define SPDIFRX_IN7 0x7
195 #define SPDIFRX_IN8 0x8
197 #define SPDIFRX_NBTR_NONE 0x0
198 #define SPDIFRX_NBTR_3 0x1
199 #define SPDIFRX_NBTR_15 0x2
200 #define SPDIFRX_NBTR_63 0x3
202 #define SPDIFRX_DRFMT_RIGHT 0x0
203 #define SPDIFRX_DRFMT_LEFT 0x1
204 #define SPDIFRX_DRFMT_PACKED 0x2
206 /* 192 CS bits in S/PDIF frame. i.e 24 CS bytes */
207 #define SPDIFRX_CS_BYTES_NB 24
208 #define SPDIFRX_UB_BYTES_NB 48
211 * CSR register is retrieved as a 32 bits word
212 * It contains 1 channel status byte and 2 user data bytes
213 * 2 S/PDIF frames are acquired to get all CS/UB bits
215 #define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
218 * struct stm32_spdifrx_data - private data of SPDIFRX
219 * @pdev: device data pointer
220 * @base: mmio register base virtual address
221 * @regmap: SPDIFRX register map pointer
222 * @regmap_conf: SPDIFRX register map configuration pointer
223 * @cs_completion: channel status retrieving completion
224 * @kclk: kernel clock feeding the SPDIFRX clock generator
225 * @dma_params: dma configuration data for rx channel
226 * @substream: PCM substream data pointer
227 * @dmab: dma buffer info pointer
228 * @ctrl_chan: dma channel for S/PDIF control bits
229 * @desc:dma async transaction descriptor
230 * @slave_config: dma slave channel runtime config pointer
231 * @phys_addr: SPDIFRX registers physical base address
232 * @lock: synchronization enabling lock
233 * @cs: channel status buffer
234 * @ub: user data buffer
235 * @irq: SPDIFRX interrupt line
236 * @refcount: keep count of opened DMA channels
238 struct stm32_spdifrx_data {
239 struct platform_device *pdev;
241 struct regmap *regmap;
242 const struct regmap_config *regmap_conf;
243 struct completion cs_completion;
245 struct snd_dmaengine_dai_dma_data dma_params;
246 struct snd_pcm_substream *substream;
247 struct snd_dma_buffer *dmab;
248 struct dma_chan *ctrl_chan;
249 struct dma_async_tx_descriptor *desc;
250 struct dma_slave_config slave_config;
251 dma_addr_t phys_addr;
252 spinlock_t lock; /* Sync enabling lock */
253 unsigned char cs[SPDIFRX_CS_BYTES_NB];
254 unsigned char ub[SPDIFRX_UB_BYTES_NB];
259 static void stm32_spdifrx_dma_complete(void *data)
261 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
262 struct platform_device *pdev = spdifrx->pdev;
263 u32 *p_start = (u32 *)spdifrx->dmab->area;
264 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
266 u16 *ub_ptr = (short *)spdifrx->ub;
269 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
271 (unsigned int)~SPDIFRX_CR_CBDMAEN);
273 if (!spdifrx->dmab->area)
276 while (ptr <= p_end) {
277 if (*ptr & SPDIFRX_CSR_SOB)
283 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
287 while (i < SPDIFRX_CS_BYTES_NB) {
288 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
289 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
291 dev_err(&pdev->dev, "Failed to get channel status\n");
297 complete(&spdifrx->cs_completion);
300 static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
305 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
307 SPDIFRX_CSR_BUF_LENGTH,
313 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
314 spdifrx->desc->callback_param = spdifrx;
315 cookie = dmaengine_submit(spdifrx->desc);
316 err = dma_submit_error(cookie);
320 dma_async_issue_pending(spdifrx->ctrl_chan);
325 static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
327 dmaengine_terminate_async(spdifrx->ctrl_chan);
330 static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
332 int cr, cr_mask, imr, ret;
335 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
336 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
340 spin_lock(&spdifrx->lock);
344 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
346 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
348 * Start sync if SPDIFRX is still in idle state.
349 * SPDIFRX reception enabled when sync done
351 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
354 * SPDIFRX configuration:
355 * Wait for activity before starting sync process. This avoid
356 * to issue sync errors when spdif signal is missing on input.
357 * Preamble, CS, user, validity and parity error bits not copied
360 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
361 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
364 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
365 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
366 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
369 dev_err(&spdifrx->pdev->dev,
370 "Failed to start synchronization\n");
373 spin_unlock(&spdifrx->lock);
378 static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
380 int cr, cr_mask, reg;
382 spin_lock(&spdifrx->lock);
384 if (--spdifrx->refcount) {
385 spin_unlock(&spdifrx->lock);
389 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
390 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
392 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
394 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
395 SPDIFRX_XIMR_MASK, 0);
397 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
398 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
400 /* dummy read to clear CSRNE and RXNE in status register */
401 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
402 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
404 spin_unlock(&spdifrx->lock);
407 static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
408 struct stm32_spdifrx_data *spdifrx)
412 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
413 if (IS_ERR(spdifrx->ctrl_chan)) {
414 dev_err(dev, "dma_request_slave_channel failed\n");
415 return PTR_ERR(spdifrx->ctrl_chan);
418 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
423 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
424 spdifrx->dmab->dev.dev = dev;
425 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
426 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
428 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
432 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
433 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
435 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
436 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
437 spdifrx->slave_config.src_maxburst = 1;
439 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
440 &spdifrx->slave_config);
442 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
443 spdifrx->ctrl_chan = NULL;
449 static const char * const spdifrx_enum_input[] = {
450 "in0", "in1", "in2", "in3"
453 /* By default CS bits are retrieved from channel A */
454 static const char * const spdifrx_enum_cs_channel[] = {
458 static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
459 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
462 static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
463 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
464 spdifrx_enum_cs_channel);
466 static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
467 struct snd_ctl_elem_info *uinfo)
469 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
475 static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
476 struct snd_ctl_elem_info *uinfo)
478 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
484 static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
488 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
489 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
491 pinctrl_pm_select_default_state(&spdifrx->pdev->dev);
493 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
497 ret = clk_prepare_enable(spdifrx->kclk);
499 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
503 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
504 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
508 ret = stm32_spdifrx_start_sync(spdifrx);
512 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
513 msecs_to_jiffies(100))
515 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
519 stm32_spdifrx_stop(spdifrx);
520 stm32_spdifrx_dma_ctrl_stop(spdifrx);
523 clk_disable_unprepare(spdifrx->kclk);
524 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev);
529 static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
530 struct snd_ctl_elem_value *ucontrol)
532 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
533 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
535 stm32_spdifrx_get_ctrl_data(spdifrx);
537 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
538 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
539 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
540 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
541 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
546 static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
547 struct snd_ctl_elem_value *ucontrol)
549 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
550 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
552 stm32_spdifrx_get_ctrl_data(spdifrx);
554 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
555 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
556 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
557 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
558 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
563 static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
564 /* Channel status control */
566 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
567 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
568 .access = SNDRV_CTL_ELEM_ACCESS_READ |
569 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
570 .info = stm32_spdifrx_info,
571 .get = stm32_spdifrx_capture_get,
573 /* User bits control */
575 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
576 .name = "IEC958 User Bit Capture Default",
577 .access = SNDRV_CTL_ELEM_ACCESS_READ |
578 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
579 .info = stm32_spdifrx_ub_info,
580 .get = stm32_spdif_user_bits_get,
584 static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
585 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
586 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
589 static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
593 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
594 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
598 return snd_soc_add_component_controls(cpu_dai->component,
600 ARRAY_SIZE(stm32_spdifrx_ctrls));
603 static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
605 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
607 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
609 spdifrx->dma_params.maxburst = 1;
611 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
613 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
616 static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
619 case STM32_SPDIFRX_CR:
620 case STM32_SPDIFRX_IMR:
621 case STM32_SPDIFRX_SR:
622 case STM32_SPDIFRX_IFCR:
623 case STM32_SPDIFRX_DR:
624 case STM32_SPDIFRX_CSR:
625 case STM32_SPDIFRX_DIR:
626 case STM32_SPDIFRX_VERR:
627 case STM32_SPDIFRX_IDR:
628 case STM32_SPDIFRX_SIDR:
635 static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
638 case STM32_SPDIFRX_DR:
639 case STM32_SPDIFRX_CSR:
640 case STM32_SPDIFRX_SR:
641 case STM32_SPDIFRX_DIR:
648 static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
651 case STM32_SPDIFRX_CR:
652 case STM32_SPDIFRX_IMR:
653 case STM32_SPDIFRX_IFCR:
660 static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
664 .max_register = STM32_SPDIFRX_SIDR,
665 .readable_reg = stm32_spdifrx_readable_reg,
666 .volatile_reg = stm32_spdifrx_volatile_reg,
667 .writeable_reg = stm32_spdifrx_writeable_reg,
668 .num_reg_defaults_raw = STM32_SPDIFRX_SIDR / sizeof(u32) + 1,
670 .cache_type = REGCACHE_FLAT,
673 static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
675 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
676 struct snd_pcm_substream *substream = spdifrx->substream;
677 struct platform_device *pdev = spdifrx->pdev;
678 unsigned int cr, mask, sr, imr;
680 int err = 0, err_xrun = 0;
682 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
683 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
685 mask = imr & SPDIFRX_XIMR_MASK;
686 /* SERR, TERR, FERR IRQs are generated if IFEIE is set */
687 if (mask & SPDIFRX_IMR_IFEIE)
688 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
692 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
698 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
699 SPDIFRX_XIFCR_MASK, flags);
701 if (flags & SPDIFRX_SR_PERR) {
702 dev_dbg(&pdev->dev, "Parity error\n");
706 if (flags & SPDIFRX_SR_OVR) {
707 dev_dbg(&pdev->dev, "Overrun error\n");
711 if (flags & SPDIFRX_SR_SBD)
712 dev_dbg(&pdev->dev, "Synchronization block detected\n");
714 if (flags & SPDIFRX_SR_SYNCD) {
715 dev_dbg(&pdev->dev, "Synchronization done\n");
718 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
719 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
720 SPDIFRX_CR_SPDIFEN_MASK, cr);
723 if (flags & SPDIFRX_SR_FERR) {
724 dev_dbg(&pdev->dev, "Frame error\n");
728 if (flags & SPDIFRX_SR_SERR) {
729 dev_dbg(&pdev->dev, "Synchronization error\n");
733 if (flags & SPDIFRX_SR_TERR) {
734 dev_dbg(&pdev->dev, "Timeout error\n");
739 /* SPDIFRX in STATE_STOP. Disable SPDIFRX to clear errors */
740 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
741 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
742 SPDIFRX_CR_SPDIFEN_MASK, cr);
745 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
750 if (err_xrun && substream)
751 snd_pcm_stop_xrun(substream);
756 static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
757 struct snd_soc_dai *cpu_dai)
759 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
762 spdifrx->substream = substream;
764 ret = clk_prepare_enable(spdifrx->kclk);
766 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
771 static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
772 struct snd_pcm_hw_params *params,
773 struct snd_soc_dai *cpu_dai)
775 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
776 int data_size = params_width(params);
781 fmt = SPDIFRX_DRFMT_PACKED;
784 fmt = SPDIFRX_DRFMT_LEFT;
787 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
792 * Set buswidth to 4 bytes for all data formats.
793 * Packed format: transfer 2 x 2 bytes samples
794 * Left format: transfer 1 x 3 bytes samples + 1 dummy byte
796 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
797 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
799 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
800 SPDIFRX_CR_DRFMT_MASK,
801 SPDIFRX_CR_DRFMTSET(fmt));
804 static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
805 struct snd_soc_dai *cpu_dai)
807 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
811 case SNDRV_PCM_TRIGGER_START:
812 case SNDRV_PCM_TRIGGER_RESUME:
813 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
814 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
815 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
817 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
818 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
820 ret = stm32_spdifrx_start_sync(spdifrx);
822 case SNDRV_PCM_TRIGGER_SUSPEND:
823 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
824 case SNDRV_PCM_TRIGGER_STOP:
825 stm32_spdifrx_stop(spdifrx);
834 static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
835 struct snd_soc_dai *cpu_dai)
837 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
839 spdifrx->substream = NULL;
840 clk_disable_unprepare(spdifrx->kclk);
843 static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
844 .startup = stm32_spdifrx_startup,
845 .hw_params = stm32_spdifrx_hw_params,
846 .trigger = stm32_spdifrx_trigger,
847 .shutdown = stm32_spdifrx_shutdown,
850 static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
852 .probe = stm32_spdifrx_dai_probe,
854 .stream_name = "CPU-Capture",
857 .rates = SNDRV_PCM_RATE_8000_192000,
858 .formats = SNDRV_PCM_FMTBIT_S32_LE |
859 SNDRV_PCM_FMTBIT_S16_LE,
861 .ops = &stm32_spdifrx_pcm_dai_ops,
865 static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
866 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
867 .buffer_bytes_max = 8 * PAGE_SIZE,
868 .period_bytes_min = 1024,
869 .period_bytes_max = 4 * PAGE_SIZE,
874 static const struct snd_soc_component_driver stm32_spdifrx_component = {
875 .name = "stm32-spdifrx",
878 static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
879 .pcm_hardware = &stm32_spdifrx_pcm_hw,
880 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
883 static const struct of_device_id stm32_spdifrx_ids[] = {
885 .compatible = "st,stm32h7-spdifrx",
886 .data = &stm32_h7_spdifrx_regmap_conf
891 static int stm32_spdifrx_parse_of(struct platform_device *pdev,
892 struct stm32_spdifrx_data *spdifrx)
894 struct device_node *np = pdev->dev.of_node;
895 const struct of_device_id *of_id;
896 struct resource *res;
901 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
903 spdifrx->regmap_conf =
904 (const struct regmap_config *)of_id->data;
908 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
909 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
910 if (IS_ERR(spdifrx->base))
911 return PTR_ERR(spdifrx->base);
913 spdifrx->phys_addr = res->start;
915 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
916 if (IS_ERR(spdifrx->kclk)) {
917 dev_err(&pdev->dev, "Could not get kclk\n");
918 return PTR_ERR(spdifrx->kclk);
921 spdifrx->irq = platform_get_irq(pdev, 0);
922 if (spdifrx->irq < 0) {
923 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
930 static int stm32_spdifrx_probe(struct platform_device *pdev)
932 struct stm32_spdifrx_data *spdifrx;
933 struct reset_control *rst;
934 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
938 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
942 spdifrx->pdev = pdev;
943 init_completion(&spdifrx->cs_completion);
944 spin_lock_init(&spdifrx->lock);
946 platform_set_drvdata(pdev, spdifrx);
948 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
952 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
954 spdifrx->regmap_conf);
955 if (IS_ERR(spdifrx->regmap)) {
956 dev_err(&pdev->dev, "Regmap init failed\n");
957 return PTR_ERR(spdifrx->regmap);
960 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
961 dev_name(&pdev->dev), spdifrx);
963 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
967 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
969 reset_control_assert(rst);
971 reset_control_deassert(rst);
974 ret = devm_snd_soc_register_component(&pdev->dev,
975 &stm32_spdifrx_component,
977 ARRAY_SIZE(stm32_spdifrx_dai));
981 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
985 pcm_config = &stm32_spdifrx_pcm_config;
986 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
988 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
992 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_IDR, &idr);
996 if (idr == SPDIFRX_IPIDR_NUMBER) {
997 ret = regmap_read(spdifrx->regmap, STM32_SPDIFRX_VERR, &ver);
999 dev_dbg(&pdev->dev, "SPDIFRX version: %lu.%lu registered\n",
1000 FIELD_GET(SPDIFRX_VERR_MAJ_MASK, ver),
1001 FIELD_GET(SPDIFRX_VERR_MIN_MASK, ver));
1007 if (!IS_ERR(spdifrx->ctrl_chan))
1008 dma_release_channel(spdifrx->ctrl_chan);
1010 snd_dma_free_pages(spdifrx->dmab);
1015 static int stm32_spdifrx_remove(struct platform_device *pdev)
1017 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
1019 if (spdifrx->ctrl_chan)
1020 dma_release_channel(spdifrx->ctrl_chan);
1023 snd_dma_free_pages(spdifrx->dmab);
1028 MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
1030 #ifdef CONFIG_PM_SLEEP
1031 static int stm32_spdifrx_suspend(struct device *dev)
1033 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1035 regcache_cache_only(spdifrx->regmap, true);
1036 regcache_mark_dirty(spdifrx->regmap);
1041 static int stm32_spdifrx_resume(struct device *dev)
1043 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1045 regcache_cache_only(spdifrx->regmap, false);
1047 return regcache_sync(spdifrx->regmap);
1049 #endif /* CONFIG_PM_SLEEP */
1051 static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1052 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1055 static struct platform_driver stm32_spdifrx_driver = {
1057 .name = "st,stm32-spdifrx",
1058 .of_match_table = stm32_spdifrx_ids,
1059 .pm = &stm32_spdifrx_pm_ops,
1061 .probe = stm32_spdifrx_probe,
1062 .remove = stm32_spdifrx_remove,
1065 module_platform_driver(stm32_spdifrx_driver);
1067 MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1068 MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1069 MODULE_ALIAS("platform:stm32-spdifrx");
1070 MODULE_LICENSE("GPL v2");