1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2022 Intel Corporation. All rights reserved.
9 #include <sound/pcm_params.h>
10 #include <sound/sof/ipc4/header.h>
11 #include "sof-audio.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
18 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
19 struct ipc4_pipeline_set_state_data *trigger_list)
21 struct sof_ipc4_msg msg = {{ 0 }};
22 u32 primary, ipc_size;
24 /* trigger a single pipeline */
25 if (trigger_list->count == 1)
26 return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_ids[0], state);
29 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
30 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
31 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
32 msg.primary = primary;
34 /* trigger multiple pipelines with a single IPC */
35 msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
37 /* ipc_size includes the count and the pipeline IDs for the number of pipelines */
38 ipc_size = sizeof(u32) * (trigger_list->count + 1);
39 msg.data_size = ipc_size;
40 msg.data_ptr = trigger_list;
42 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
45 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 id, u32 state)
47 struct sof_ipc4_msg msg = {{ 0 }};
50 dev_dbg(sdev->dev, "ipc4 set pipeline %d state %d", id, state);
53 primary |= SOF_IPC4_GLB_PIPE_STATE_ID(id);
54 primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
55 primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
56 primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
58 msg.primary = primary;
60 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
62 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
65 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
66 struct snd_sof_pipeline *spipe,
67 struct ipc4_pipeline_set_state_data *trigger_list)
69 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
70 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
72 if (pipeline->skip_during_fe_trigger)
76 case SOF_IPC4_PIPE_RUNNING:
78 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
81 if (spipe->started_count == spipe->paused_count)
82 trigger_list->pipeline_ids[trigger_list->count++] =
83 pipe_widget->instance_id;
85 case SOF_IPC4_PIPE_RESET:
86 /* RESET if the pipeline is neither running nor paused */
87 if (!spipe->started_count && !spipe->paused_count)
88 trigger_list->pipeline_ids[trigger_list->count++] =
89 pipe_widget->instance_id;
91 case SOF_IPC4_PIPE_PAUSED:
92 /* Pause the pipeline only when its started_count is 1 more than paused_count */
93 if (spipe->paused_count == (spipe->started_count - 1))
94 trigger_list->pipeline_ids[trigger_list->count++] =
95 pipe_widget->instance_id;
103 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
104 struct snd_sof_pipeline *spipe,
105 struct ipc4_pipeline_set_state_data *trigger_list)
107 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
108 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
111 if (pipeline->skip_during_fe_trigger)
114 /* set state for pipeline if it was just triggered */
115 for (i = 0; i < trigger_list->count; i++) {
116 if (trigger_list->pipeline_ids[i] == pipe_widget->instance_id) {
117 pipeline->state = state;
123 case SOF_IPC4_PIPE_PAUSED:
125 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
127 * increment paused_count if the PAUSED is the final state during
130 spipe->paused_count++;
132 case SNDRV_PCM_TRIGGER_STOP:
133 case SNDRV_PCM_TRIGGER_SUSPEND:
135 * decrement started_count if PAUSED is the final state during the
138 spipe->started_count--;
144 case SOF_IPC4_PIPE_RUNNING:
146 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
147 /* decrement paused_count for RELEASE */
148 spipe->paused_count--;
150 case SNDRV_PCM_TRIGGER_START:
151 case SNDRV_PCM_TRIGGER_RESUME:
152 /* increment started_count for START/RESUME */
153 spipe->started_count++;
165 * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
166 * triggers and ioctls
177 * +----------------+ +------v-------+ +-------------+
178 * | | START | | HW_FREE | |
179 * | RUNNING <-------------+ PAUSED +--------------> + RESET |
181 * +------+---------+ RELEASE +---------+----+ +-------------+
187 * +---------------------------------+
190 * Note that during system suspend, the suspend trigger is followed by a hw_free in
191 * sof_pcm_trigger(). So, the final state during suspend would be RESET.
192 * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
193 * prepare ioctl before the START trigger.
197 * Chained DMA is a special case where there is no processing on
198 * DSP. The samples are just moved over by host side DMA to a single
199 * buffer on DSP and directly from there to link DMA. However, the
200 * model on SOF driver has two notional pipelines, one at host DAI,
201 * and another at link DAI. They both shall have the use_chain_dma
205 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
206 struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
209 bool allocate, enable, set_fifo_size;
210 struct sof_ipc4_msg msg = {{ 0 }};
214 case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
218 * SOF assumes creation of a new stream from the presence of fifo_size
219 * in the message, so we must leave it out in pause release case.
221 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
222 set_fifo_size = false;
224 set_fifo_size = true;
226 case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
229 set_fifo_size = false;
231 case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
234 set_fifo_size = false;
237 dev_err(sdev->dev, "Unexpected state %d", state);
241 msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
242 msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
243 msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
246 * To set-up the DMA chain, the host DMA ID and SCS setting
247 * are retrieved from the host pipeline configuration. Likewise
248 * the link DMA ID and fifo_size are retrieved from the link
249 * pipeline configuration.
251 for (i = 0; i < pipeline_list->count; i++) {
252 struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
253 struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
254 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
256 if (!pipeline->use_chain_dma) {
258 "All pipelines in chained DMA stream should have use_chain_dma attribute set.");
262 msg.primary |= pipeline->msg.primary;
264 /* Add fifo_size (actually DMA buffer size) field to the message */
266 msg.extension |= pipeline->msg.extension;
270 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
273 msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
275 return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
278 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
279 struct snd_pcm_substream *substream, int state, int cmd)
281 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
282 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
283 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
284 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
285 struct ipc4_pipeline_set_state_data *trigger_list;
286 struct snd_sof_widget *pipe_widget;
287 struct sof_ipc4_pipeline *pipeline;
288 struct snd_sof_pipeline *spipe;
289 struct snd_sof_pcm *spcm;
293 dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
295 spcm = snd_sof_find_spcm_dai(component, rtd);
299 pipeline_list = &spcm->stream[substream->stream].pipeline_list;
301 /* nothing to trigger if the list is empty */
302 if (!pipeline_list->pipelines || !pipeline_list->count)
305 spipe = pipeline_list->pipelines[0];
306 pipe_widget = spipe->pipe_widget;
307 pipeline = pipe_widget->private;
310 * If use_chain_dma attribute is set we proceed to chained DMA
311 * trigger function that handles the rest for the substream.
313 if (pipeline->use_chain_dma)
314 return sof_ipc4_chain_dma_trigger(sdev, pipeline_list, state, cmd);
316 /* allocate memory for the pipeline data */
317 trigger_list = kzalloc(struct_size(trigger_list, pipeline_ids, pipeline_list->count),
322 mutex_lock(&ipc4_data->pipeline_state_mutex);
325 * IPC4 requires pipelines to be triggered in order starting at the sink and
326 * walking all the way to the source. So traverse the pipeline_list in the order
327 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
328 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
329 * in the pipeline, the order of triggering between the left/right paths will be
330 * indeterministic. But the sink->source trigger order sink->source would still be
331 * guaranteed for each fork independently.
333 if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
334 for (i = pipeline_list->count - 1; i >= 0; i--) {
335 spipe = pipeline_list->pipelines[i];
336 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
339 for (i = 0; i < pipeline_list->count; i++) {
340 spipe = pipeline_list->pipelines[i];
341 sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list);
344 /* return if all pipelines are in the requested state already */
345 if (!trigger_list->count) {
350 /* no need to pause before reset or before pause release */
351 if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
352 goto skip_pause_transition;
355 * set paused state for pipelines if the final state is PAUSED or when the pipeline
356 * is set to RUNNING for the first time after the PCM is started.
358 ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
360 dev_err(sdev->dev, "failed to pause all pipelines\n");
364 /* update PAUSED state for all pipelines just triggered */
365 for (i = 0; i < pipeline_list->count ; i++) {
366 spipe = pipeline_list->pipelines[i];
367 sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
371 /* return if this is the final state */
372 if (state == SOF_IPC4_PIPE_PAUSED)
374 skip_pause_transition:
375 /* else set the RUNNING/RESET state in the DSP */
376 ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
378 dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
382 /* update RUNNING/RESET state for all pipelines that were just triggered */
383 for (i = 0; i < pipeline_list->count; i++) {
384 spipe = pipeline_list->pipelines[i];
385 sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
389 mutex_unlock(&ipc4_data->pipeline_state_mutex);
394 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
395 struct snd_pcm_substream *substream, int cmd)
399 /* determine the pipeline state */
401 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
402 state = SOF_IPC4_PIPE_PAUSED;
404 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
405 case SNDRV_PCM_TRIGGER_RESUME:
406 case SNDRV_PCM_TRIGGER_START:
407 state = SOF_IPC4_PIPE_RUNNING;
409 case SNDRV_PCM_TRIGGER_SUSPEND:
410 case SNDRV_PCM_TRIGGER_STOP:
411 state = SOF_IPC4_PIPE_PAUSED;
414 dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
418 /* set the pipeline state */
419 return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
422 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
423 struct snd_pcm_substream *substream)
425 /* command is not relevant with RESET, so just pass 0 */
426 return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
429 static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
430 struct snd_pcm_hw_params *params)
432 struct snd_sof_dai_link *slink;
433 struct snd_sof_dai *dai;
434 bool dai_link_found = false;
437 list_for_each_entry(slink, &sdev->dai_link_list, list) {
438 if (!strcmp(slink->link->name, link_name)) {
439 dai_link_found = true;
447 for (i = 0; i < slink->num_hw_configs; i++) {
448 struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
450 if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
451 /* set current config for all DAI's with matching name */
452 list_for_each_entry(dai, &sdev->dai_list, list)
453 if (!strcmp(slink->link->name, dai->name))
454 dai->current_config = le32_to_cpu(hw_config->id);
461 * Fixup DAI link parameters for sampling rate based on
462 * DAI copier configuration.
464 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
465 struct snd_pcm_hw_params *params,
466 struct sof_ipc4_copier *ipc4_copier)
468 struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
469 struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
470 int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
471 unsigned int fe_rate = params_rate(params);
472 bool fe_be_rate_match = false;
473 bool single_be_rate = true;
474 unsigned int be_rate;
478 * Copier does not change sampling rate, so we
479 * need to only consider the input pin information.
481 for (i = 0; i < num_input_formats; i++) {
482 unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
486 else if (val != be_rate)
487 single_be_rate = false;
489 if (val == fe_rate) {
490 fe_be_rate_match = true;
496 * If rate is different than FE rate, topology must
497 * contain an SRC. But we do require topology to
498 * define a single rate in the DAI copier config in
499 * this case (FE rate may be variable).
501 if (!fe_be_rate_match) {
502 if (!single_be_rate) {
503 dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
508 rate->max = rate->min;
514 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
515 struct snd_pcm_hw_params *params)
517 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
518 struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
519 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
520 struct snd_soc_dai *cpu_dai = asoc_rtd_to_cpu(rtd, 0);
521 struct sof_ipc4_copier *ipc4_copier;
522 bool use_chain_dma = false;
526 dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
527 rtd->dai_link->name);
531 ipc4_copier = dai->private;
533 dev_err(component->dev, "%s: No private data found for DAI %s\n",
534 __func__, rtd->dai_link->name);
538 for_each_pcm_streams(dir) {
539 struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
542 struct snd_sof_widget *swidget = w->dobj.private;
543 struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
544 struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
546 if (pipeline->use_chain_dma)
547 use_chain_dma = true;
551 /* Chain DMA does not use copiers, so no fixup needed */
552 if (!use_chain_dma) {
553 int ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
559 switch (ipc4_copier->dai_type) {
560 case SOF_DAI_INTEL_SSP:
561 ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
570 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
572 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
575 for_each_pcm_streams(stream) {
576 pipeline_list = &spcm->stream[stream].pipeline_list;
577 kfree(pipeline_list->pipelines);
578 pipeline_list->pipelines = NULL;
579 kfree(spcm->stream[stream].private);
580 spcm->stream[stream].private = NULL;
584 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
586 struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
587 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
588 struct sof_ipc4_timestamp_info *stream_info;
589 bool support_info = true;
594 abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
595 sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
596 sizeof(abi_version));
598 if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
599 support_info = false;
601 for_each_pcm_streams(stream) {
602 pipeline_list = &spcm->stream[stream].pipeline_list;
604 /* allocate memory for max number of pipeline IDs */
605 pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
606 sizeof(struct snd_sof_widget *), GFP_KERNEL);
607 if (!pipeline_list->pipelines) {
608 sof_ipc4_pcm_free(sdev, spcm);
615 stream_info = kzalloc(sizeof(*stream_info), GFP_KERNEL);
617 sof_ipc4_pcm_free(sdev, spcm);
621 spcm->stream[stream].private = stream_info;
627 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *spcm)
629 struct sof_ipc4_copier *host_copier = NULL;
630 struct sof_ipc4_copier *dai_copier = NULL;
631 struct sof_ipc4_llp_reading_slot llp_slot;
632 struct sof_ipc4_timestamp_info *info;
633 struct snd_soc_dapm_widget *widget;
634 struct snd_sof_dai *dai;
637 /* find host & dai to locate info in memory window */
638 for_each_dapm_widgets(spcm->list, i, widget) {
639 struct snd_sof_widget *swidget = widget->dobj.private;
644 if (WIDGET_IS_AIF(swidget->widget->id)) {
645 host_copier = swidget->private;
646 } else if (WIDGET_IS_DAI(swidget->widget->id)) {
647 dai = swidget->private;
648 dai_copier = dai->private;
652 /* both host and dai copier must be valid for time_info */
653 if (!host_copier || !dai_copier) {
654 dev_err(sdev->dev, "host or dai copier are not found\n");
658 info = spcm->private;
659 info->host_copier = host_copier;
660 info->dai_copier = dai_copier;
661 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_gpdma_reading_slots) +
662 sdev->fw_info_box.offset;
664 /* find llp slot used by current dai */
665 for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
666 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
667 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
670 info->llp_offset += sizeof(llp_slot);
673 if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
676 /* if no llp gpdma slot is used, check aggregated sdw slot */
677 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_sndw_reading_slots) +
678 sdev->fw_info_box.offset;
679 for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
680 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
681 if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
684 info->llp_offset += sizeof(llp_slot);
687 if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
690 /* check EVAD slot */
691 info->llp_offset = offsetof(struct sof_ipc4_fw_registers, llp_evad_reading_slot) +
692 sdev->fw_info_box.offset;
693 sof_mailbox_read(sdev, info->llp_offset, &llp_slot, sizeof(llp_slot));
694 if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id) {
695 dev_info(sdev->dev, "no llp found, fall back to default HDA path");
696 info->llp_offset = 0;
700 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
701 struct snd_pcm_substream *substream,
702 struct snd_pcm_hw_params *params,
703 struct snd_sof_platform_stream_params *platform_params)
705 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
706 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
707 struct sof_ipc4_timestamp_info *time_info;
708 struct snd_sof_pcm *spcm;
710 spcm = snd_sof_find_spcm_dai(component, rtd);
711 time_info = spcm->stream[substream->stream].private;
712 /* delay calculation is not supported by current fw_reg ABI */
716 time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
717 time_info->llp_offset = 0;
719 sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
724 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
725 struct snd_pcm_substream *substream,
726 struct snd_sof_pcm_stream *stream,
727 struct sof_ipc4_timestamp_info *time_info)
729 struct sof_ipc4_copier *host_copier = time_info->host_copier;
730 struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
731 struct sof_ipc4_pipeline_registers ppl_reg;
732 u64 stream_start_position;
737 if (!host_copier || !dai_copier)
740 if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
743 node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
744 offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
745 sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
746 if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
749 stream_start_position = ppl_reg.stream_start_offset;
750 ch = dai_copier->data.out_format.fmt_cfg;
751 ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
752 dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
753 /* convert offset to sample count */
754 do_div(stream_start_position, dai_sample_size);
755 time_info->stream_start_offset = stream_start_position;
760 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
761 struct snd_pcm_substream *substream)
763 struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
764 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
765 struct sof_ipc4_timestamp_info *time_info;
766 struct sof_ipc4_llp_reading_slot llp;
767 snd_pcm_uframes_t head_ptr, tail_ptr;
768 struct snd_sof_pcm_stream *stream;
769 struct snd_sof_pcm *spcm;
773 spcm = snd_sof_find_spcm_dai(component, rtd);
777 stream = &spcm->stream[substream->stream];
778 time_info = stream->private;
783 * stream_start_offset is updated to memory window by FW based on
784 * pipeline statistics and it may be invalid if host query happens before
785 * the statistics is complete. And it will not change after the first initiailization.
787 if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
788 ret = sof_ipc4_get_stream_start_offset(sdev, substream, stream, time_info);
794 * HDaudio links don't support the LLP counter reported by firmware
795 * the link position is read directly from hardware registers.
797 if (!time_info->llp_offset) {
798 tmp_ptr = snd_sof_pcm_get_stream_position(sdev, component, substream);
802 sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
803 tmp_ptr = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
806 /* In two cases dai dma position is not accurate
807 * (1) dai pipeline is started before host pipeline
808 * (2) multiple streams mixed into one. Each stream has the same dai dma position
810 * Firmware calculates correct stream_start_offset for all cases including above two.
811 * Driver subtracts stream_start_offset from dai dma position to get accurate one
813 tmp_ptr -= time_info->stream_start_offset;
815 /* Calculate the delay taking into account that both pointer can wrap */
816 div64_u64_rem(tmp_ptr, substream->runtime->boundary, &tmp_ptr);
817 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
818 head_ptr = substream->runtime->status->hw_ptr;
822 tail_ptr = substream->runtime->status->hw_ptr;
825 if (head_ptr < tail_ptr)
826 return substream->runtime->boundary - tail_ptr + head_ptr;
828 return head_ptr - tail_ptr;
831 const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
832 .hw_params = sof_ipc4_pcm_hw_params,
833 .trigger = sof_ipc4_pcm_trigger,
834 .hw_free = sof_ipc4_pcm_hw_free,
835 .dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
836 .pcm_setup = sof_ipc4_pcm_setup,
837 .pcm_free = sof_ipc4_pcm_free,
838 .delay = sof_ipc4_pcm_delay,
839 .ipc_first_on_start = true,
840 .platform_stop_during_hw_free = true,