sound/soc/sof/intel/tgl.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // Copyright(c) 2020 Intel Corporation. All rights reserved.
   4 //
   5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
   6 //
   7
   8 /*
   9  * Hardware interface for audio DSP on Tigerlake.
  10  */
  11
  12 #include <sound/sof/ext_manifest4.h>
  13 #include "../ipc4-priv.h"
  14 #include "../ops.h"
  15 #include "hda.h"
  16 #include "hda-ipc.h"
  17 #include "../sof-audio.h"
  18
  19 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
  20         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  21         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  22         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  23 };
  24
  25 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
  26 {
  27         struct sof_ipc_pm_core_config pm_core_config = {
  28                 .hdr = {
  29                         .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
  30                         .size = sizeof(pm_core_config),
  31                 },
  32                 .enable_mask = sdev->enabled_cores_mask | BIT(core),
  33         };
  34
  35         /* power up primary core if not already powered up and return */
  36         if (core == SOF_DSP_PRIMARY_CORE)
  37                 return hda_dsp_enable_core(sdev, BIT(core));
  38
  39         /* notify DSP for secondary cores */
  40         return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config),
  41                                  &pm_core_config, sizeof(pm_core_config));
  42 }
  43
  44 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
  45 {
  46         struct sof_ipc_pm_core_config pm_core_config = {
  47                 .hdr = {
  48                         .cmd = SOF_IPC_GLB_PM_MSG | SOF_IPC_PM_CORE_ENABLE,
  49                         .size = sizeof(pm_core_config),
  50                 },
  51                 .enable_mask = sdev->enabled_cores_mask & ~BIT(core),
  52         };
  53
  54         /* power down primary core and return */
  55         if (core == SOF_DSP_PRIMARY_CORE)
  56                 return hda_dsp_core_reset_power_down(sdev, BIT(core));
  57
  58         /* notify DSP for secondary cores */
  59         return sof_ipc_tx_message(sdev->ipc, &pm_core_config, sizeof(pm_core_config),
  60                                  &pm_core_config, sizeof(pm_core_config));
  61 }
  62
  63 /* Tigerlake ops */
  64 struct snd_sof_dsp_ops sof_tgl_ops;
  65 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
  66
  67 int sof_tgl_ops_init(struct snd_sof_dev *sdev)
  68 {
  69         /* common defaults */
  70         memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
  71
  72         /* probe/remove/shutdown */
  73         sof_tgl_ops.shutdown    = hda_dsp_shutdown;
  74
  75         if (sdev->pdata->ipc_type == SOF_IPC) {
  76                 /* doorbell */
  77                 sof_tgl_ops.irq_thread  = cnl_ipc_irq_thread;
  78
  79                 /* ipc */
  80                 sof_tgl_ops.send_msg    = cnl_ipc_send_msg;
  81         }
  82
  83         if (sdev->pdata->ipc_type == SOF_INTEL_IPC4) {
  84                 struct sof_ipc4_fw_data *ipc4_data;
  85
  86                 sdev->private = devm_kzalloc(sdev->dev, sizeof(*ipc4_data), GFP_KERNEL);
  87                 if (!sdev->private)
  88                         return -ENOMEM;
  89
  90                 ipc4_data = sdev->private;
  91                 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
  92
  93                 /* doorbell */
  94                 sof_tgl_ops.irq_thread  = cnl_ipc4_irq_thread;
  95
  96                 /* ipc */
  97                 sof_tgl_ops.send_msg    = cnl_ipc4_send_msg;
  98         }
  99
 100         /* set DAI driver ops */
 101         hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
 102
 103         /* debug */
 104         sof_tgl_ops.debug_map   = tgl_dsp_debugfs;
 105         sof_tgl_ops.debug_map_count     = ARRAY_SIZE(tgl_dsp_debugfs);
 106         sof_tgl_ops.ipc_dump    = cnl_ipc_dump;
 107
 108         /* pre/post fw run */
 109         sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
 110
 111         /* firmware run */
 112         sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
 113
 114         /* dsp core get/put */
 115         sof_tgl_ops.core_get = tgl_dsp_core_get;
 116         sof_tgl_ops.core_put = tgl_dsp_core_put;
 117
 118         return 0;
 119 };
 120 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
 121
 122 const struct sof_intel_dsp_desc tgl_chip_info = {
 123         /* Tigerlake , Alderlake */
 124         .cores_num = 4,
 125         .init_core_mask = 1,
 126         .host_managed_cores_mask = BIT(0),
 127         .ipc_req = CNL_DSP_REG_HIPCIDR,
 128         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 129         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 130         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 131         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 132         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 133         .rom_init_timeout       = 300,
 134         .ssp_count = ICL_SSP_COUNT,
 135         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 136         .sdw_shim_base = SDW_SHIM_BASE,
 137         .sdw_alh_base = SDW_ALH_BASE,
 138         .check_sdw_irq  = hda_common_check_sdw_irq,
 139         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 140         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 141 };
 142 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 143
 144 const struct sof_intel_dsp_desc tglh_chip_info = {
 145         /* Tigerlake-H */
 146         .cores_num = 2,
 147         .init_core_mask = 1,
 148         .host_managed_cores_mask = BIT(0),
 149         .ipc_req = CNL_DSP_REG_HIPCIDR,
 150         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 151         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 152         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 153         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 154         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 155         .rom_init_timeout       = 300,
 156         .ssp_count = ICL_SSP_COUNT,
 157         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 158         .sdw_shim_base = SDW_SHIM_BASE,
 159         .sdw_alh_base = SDW_ALH_BASE,
 160         .check_sdw_irq  = hda_common_check_sdw_irq,
 161         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 162         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 163 };
 164 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 165
 166 const struct sof_intel_dsp_desc ehl_chip_info = {
 167         /* Elkhartlake */
 168         .cores_num = 4,
 169         .init_core_mask = 1,
 170         .host_managed_cores_mask = BIT(0),
 171         .ipc_req = CNL_DSP_REG_HIPCIDR,
 172         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 173         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 174         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 175         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 176         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 177         .rom_init_timeout       = 300,
 178         .ssp_count = ICL_SSP_COUNT,
 179         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 180         .sdw_shim_base = SDW_SHIM_BASE,
 181         .sdw_alh_base = SDW_ALH_BASE,
 182         .check_sdw_irq  = hda_common_check_sdw_irq,
 183         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 184         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 185 };
 186 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 187
 188 const struct sof_intel_dsp_desc adls_chip_info = {
 189         /* Alderlake-S */
 190         .cores_num = 2,
 191         .init_core_mask = BIT(0),
 192         .host_managed_cores_mask = BIT(0),
 193         .ipc_req = CNL_DSP_REG_HIPCIDR,
 194         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 195         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 196         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 197         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 198         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 199         .rom_init_timeout       = 300,
 200         .ssp_count = ICL_SSP_COUNT,
 201         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 202         .sdw_shim_base = SDW_SHIM_BASE,
 203         .sdw_alh_base = SDW_ALH_BASE,
 204         .check_sdw_irq  = hda_common_check_sdw_irq,
 205         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 206         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 207 };
 208 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);