sound/soc/sof/intel/tgl.c

   1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2 //
   3 // Copyright(c) 2020 Intel Corporation
   4 //
   5 // Authors: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
   6 //
   7
   8 /*
   9  * Hardware interface for audio DSP on Tigerlake.
  10  */
  11
  12 #include <sound/sof/ext_manifest4.h>
  13 #include "../ipc4-priv.h"
  14 #include "../ops.h"
  15 #include "hda.h"
  16 #include "hda-ipc.h"
  17 #include "../sof-audio.h"
  18
  19 static const struct snd_sof_debugfs_map tgl_dsp_debugfs[] = {
  20         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  21         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  22         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  23 };
  24
  25 static const struct snd_sof_debugfs_map tgl_ipc4_dsp_debugfs[] = {
  26         {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
  27         {"pp", HDA_DSP_PP_BAR,  0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
  28         {"dsp", HDA_DSP_BAR,  0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
  29         {"fw_regs", HDA_DSP_BAR,  SRAM_WINDOW_OFFSET(0), 0x1000, SOF_DEBUGFS_ACCESS_D0_ONLY},
  30 };
  31
  32 static int tgl_dsp_core_get(struct snd_sof_dev *sdev, int core)
  33 {
  34         const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
  35
  36         /* power up primary core if not already powered up and return */
  37         if (core == SOF_DSP_PRIMARY_CORE)
  38                 return hda_dsp_enable_core(sdev, BIT(core));
  39
  40         if (pm_ops->set_core_state)
  41                 return pm_ops->set_core_state(sdev, core, true);
  42
  43         return 0;
  44 }
  45
  46 static int tgl_dsp_core_put(struct snd_sof_dev *sdev, int core)
  47 {
  48         const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
  49         int ret;
  50
  51         if (pm_ops->set_core_state) {
  52                 ret = pm_ops->set_core_state(sdev, core, false);
  53                 if (ret < 0)
  54                         return ret;
  55         }
  56
  57         /* power down primary core and return */
  58         if (core == SOF_DSP_PRIMARY_CORE)
  59                 return hda_dsp_core_reset_power_down(sdev, BIT(core));
  60
  61         return 0;
  62 }
  63
  64 /* Tigerlake ops */
  65 struct snd_sof_dsp_ops sof_tgl_ops;
  66 EXPORT_SYMBOL_NS(sof_tgl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
  67
  68 int sof_tgl_ops_init(struct snd_sof_dev *sdev)
  69 {
  70         /* common defaults */
  71         memcpy(&sof_tgl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
  72
  73         /* probe/remove/shutdown */
  74         sof_tgl_ops.shutdown    = hda_dsp_shutdown_dma_flush;
  75
  76         if (sdev->pdata->ipc_type == SOF_IPC_TYPE_3) {
  77                 /* doorbell */
  78                 sof_tgl_ops.irq_thread  = cnl_ipc_irq_thread;
  79
  80                 /* ipc */
  81                 sof_tgl_ops.send_msg    = cnl_ipc_send_msg;
  82
  83                 /* debug */
  84                 sof_tgl_ops.ipc_dump    = cnl_ipc_dump;
  85                 sof_tgl_ops.debug_map   = tgl_dsp_debugfs;
  86                 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_dsp_debugfs);
  87
  88                 sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc3;
  89         }
  90
  91         if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
  92                 struct sof_ipc4_fw_data *ipc4_data;
  93
  94                 sdev->private = kzalloc(sizeof(*ipc4_data), GFP_KERNEL);
  95                 if (!sdev->private)
  96                         return -ENOMEM;
  97
  98                 ipc4_data = sdev->private;
  99                 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
 100
 101                 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
 102
 103                 ipc4_data->fw_context_save = true;
 104
 105                 /* External library loading support */
 106                 ipc4_data->load_library = hda_dsp_ipc4_load_library;
 107
 108                 /* doorbell */
 109                 sof_tgl_ops.irq_thread  = cnl_ipc4_irq_thread;
 110
 111                 /* ipc */
 112                 sof_tgl_ops.send_msg    = cnl_ipc4_send_msg;
 113
 114                 /* debug */
 115                 sof_tgl_ops.ipc_dump    = cnl_ipc4_dump;
 116                 sof_tgl_ops.dbg_dump    = hda_ipc4_dsp_dump;
 117                 sof_tgl_ops.debug_map   = tgl_ipc4_dsp_debugfs;
 118                 sof_tgl_ops.debug_map_count = ARRAY_SIZE(tgl_ipc4_dsp_debugfs);
 119
 120                 sof_tgl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
 121         }
 122
 123         /* set DAI driver ops */
 124         hda_set_dai_drv_ops(sdev, &sof_tgl_ops);
 125
 126         /* pre/post fw run */
 127         sof_tgl_ops.post_fw_run = hda_dsp_post_fw_run;
 128
 129         /* firmware run */
 130         sof_tgl_ops.run = hda_dsp_cl_boot_firmware_iccmax;
 131
 132         /* dsp core get/put */
 133         sof_tgl_ops.core_get = tgl_dsp_core_get;
 134         sof_tgl_ops.core_put = tgl_dsp_core_put;
 135
 136         return 0;
 137 };
 138 EXPORT_SYMBOL_NS(sof_tgl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
 139
 140 const struct sof_intel_dsp_desc tgl_chip_info = {
 141         /* Tigerlake , Alderlake */
 142         .cores_num = 4,
 143         .init_core_mask = 1,
 144         .host_managed_cores_mask = BIT(0),
 145         .ipc_req = CNL_DSP_REG_HIPCIDR,
 146         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 147         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 148         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 149         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 150         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 151         .rom_init_timeout       = 300,
 152         .ssp_count = TGL_SSP_COUNT,
 153         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 154         .sdw_shim_base = SDW_SHIM_BASE,
 155         .sdw_alh_base = SDW_ALH_BASE,
 156         .d0i3_offset = SOF_HDA_VS_D0I3C,
 157         .read_sdw_lcount =  hda_sdw_check_lcount_common,
 158         .enable_sdw_irq = hda_common_enable_sdw_irq,
 159         .check_sdw_irq  = hda_common_check_sdw_irq,
 160         .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
 161         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 162         .cl_init = cl_dsp_init,
 163         .power_down_dsp = hda_power_down_dsp,
 164         .disable_interrupts = hda_dsp_disable_interrupts,
 165         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 166 };
 167 EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 168
 169 const struct sof_intel_dsp_desc tglh_chip_info = {
 170         /* Tigerlake-H */
 171         .cores_num = 2,
 172         .init_core_mask = 1,
 173         .host_managed_cores_mask = BIT(0),
 174         .ipc_req = CNL_DSP_REG_HIPCIDR,
 175         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 176         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 177         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 178         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 179         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 180         .rom_init_timeout       = 300,
 181         .ssp_count = TGL_SSP_COUNT,
 182         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 183         .sdw_shim_base = SDW_SHIM_BASE,
 184         .sdw_alh_base = SDW_ALH_BASE,
 185         .d0i3_offset = SOF_HDA_VS_D0I3C,
 186         .read_sdw_lcount =  hda_sdw_check_lcount_common,
 187         .enable_sdw_irq = hda_common_enable_sdw_irq,
 188         .check_sdw_irq  = hda_common_check_sdw_irq,
 189         .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
 190         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 191         .cl_init = cl_dsp_init,
 192         .power_down_dsp = hda_power_down_dsp,
 193         .disable_interrupts = hda_dsp_disable_interrupts,
 194         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 195 };
 196 EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 197
 198 const struct sof_intel_dsp_desc ehl_chip_info = {
 199         /* Elkhartlake */
 200         .cores_num = 4,
 201         .init_core_mask = 1,
 202         .host_managed_cores_mask = BIT(0),
 203         .ipc_req = CNL_DSP_REG_HIPCIDR,
 204         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 205         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 206         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 207         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 208         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 209         .rom_init_timeout       = 300,
 210         .ssp_count = TGL_SSP_COUNT,
 211         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 212         .sdw_shim_base = SDW_SHIM_BASE,
 213         .sdw_alh_base = SDW_ALH_BASE,
 214         .d0i3_offset = SOF_HDA_VS_D0I3C,
 215         .read_sdw_lcount =  hda_sdw_check_lcount_common,
 216         .enable_sdw_irq = hda_common_enable_sdw_irq,
 217         .check_sdw_irq  = hda_common_check_sdw_irq,
 218         .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
 219         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 220         .cl_init = cl_dsp_init,
 221         .power_down_dsp = hda_power_down_dsp,
 222         .disable_interrupts = hda_dsp_disable_interrupts,
 223         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 224 };
 225 EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
 226
 227 const struct sof_intel_dsp_desc adls_chip_info = {
 228         /* Alderlake-S */
 229         .cores_num = 2,
 230         .init_core_mask = BIT(0),
 231         .host_managed_cores_mask = BIT(0),
 232         .ipc_req = CNL_DSP_REG_HIPCIDR,
 233         .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
 234         .ipc_ack = CNL_DSP_REG_HIPCIDA,
 235         .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
 236         .ipc_ctl = CNL_DSP_REG_HIPCCTL,
 237         .rom_status_reg = HDA_DSP_SRAM_REG_ROM_STATUS,
 238         .rom_init_timeout       = 300,
 239         .ssp_count = TGL_SSP_COUNT,
 240         .ssp_base_offset = CNL_SSP_BASE_OFFSET,
 241         .sdw_shim_base = SDW_SHIM_BASE,
 242         .sdw_alh_base = SDW_ALH_BASE,
 243         .d0i3_offset = SOF_HDA_VS_D0I3C,
 244         .read_sdw_lcount =  hda_sdw_check_lcount_common,
 245         .enable_sdw_irq = hda_common_enable_sdw_irq,
 246         .check_sdw_irq  = hda_common_check_sdw_irq,
 247         .check_sdw_wakeen_irq = hda_sdw_check_wakeen_irq_common,
 248         .check_ipc_irq  = hda_dsp_check_ipc_irq,
 249         .cl_init = cl_dsp_init,
 250         .power_down_dsp = hda_power_down_dsp,
 251         .disable_interrupts = hda_dsp_disable_interrupts,
 252         .hw_ip_version = SOF_INTEL_CAVS_2_5,
 253 };
 254 EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);