1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <sound/hdaudio_ext.h>
19 #include <sound/hda_register.h>
20 #include <sound/sof.h>
21 #include <trace/events/sof_intel.h>
23 #include "../sof-audio.h"
24 #include "../ipc4-priv.h"
27 #define HDA_LTRP_GB_VALUE_US 95
29 static inline const char *hda_hstream_direction_str(struct hdac_stream *hstream)
31 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK)
37 static char *hda_hstream_dbg_get_stream_info_str(struct hdac_stream *hstream)
39 struct snd_soc_pcm_runtime *rtd;
41 if (hstream->substream)
42 rtd = snd_soc_substream_to_rtd(hstream->substream);
43 else if (hstream->cstream)
44 rtd = hstream->cstream->private_data;
46 /* Non audio DMA user, like dma-trace */
47 return kasprintf(GFP_KERNEL, "-- (%s, stream_tag: %u)",
48 hda_hstream_direction_str(hstream),
51 return kasprintf(GFP_KERNEL, "dai_link \"%s\" (%s, stream_tag: %u)",
52 rtd->dai_link->name, hda_hstream_direction_str(hstream),
57 * set up one of BDL entries for a stream
59 static int hda_setup_bdle(struct snd_sof_dev *sdev,
60 struct snd_dma_buffer *dmab,
61 struct hdac_stream *hstream,
62 struct sof_intel_dsp_bdl **bdlp,
63 int offset, int size, int ioc)
65 struct hdac_bus *bus = sof_to_bus(sdev);
66 struct sof_intel_dsp_bdl *bdl = *bdlp;
72 if (hstream->frags >= HDA_DSP_MAX_BDL_ENTRIES) {
73 dev_err(sdev->dev, "error: stream frags exceeded\n");
77 addr = snd_sgbuf_get_addr(dmab, offset);
78 /* program BDL addr */
79 bdl->addr_l = cpu_to_le32(lower_32_bits(addr));
80 bdl->addr_h = cpu_to_le32(upper_32_bits(addr));
81 /* program BDL size */
82 chunk = snd_sgbuf_get_chunk_size(dmab, offset, size);
83 /* one BDLE should not cross 4K boundary */
84 if (bus->align_bdle_4k) {
85 u32 remain = 0x1000 - (offset & 0xfff);
90 bdl->size = cpu_to_le32(chunk);
91 /* only program IOC when the whole segment is processed */
93 bdl->ioc = (size || !ioc) ? 0 : cpu_to_le32(0x01);
104 * set up Buffer Descriptor List (BDL) for host memory transfer
105 * BDL describes the location of the individual buffers and is little endian.
107 int hda_dsp_stream_setup_bdl(struct snd_sof_dev *sdev,
108 struct snd_dma_buffer *dmab,
109 struct hdac_stream *hstream)
111 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
112 struct sof_intel_dsp_bdl *bdl;
113 int i, offset, period_bytes, periods;
116 period_bytes = hstream->period_bytes;
117 dev_dbg(sdev->dev, "period_bytes:0x%x\n", period_bytes);
119 period_bytes = hstream->bufsize;
121 periods = hstream->bufsize / period_bytes;
123 dev_dbg(sdev->dev, "periods:%d\n", periods);
125 remain = hstream->bufsize % period_bytes;
129 /* program the initial BDL entries */
130 bdl = (struct sof_intel_dsp_bdl *)hstream->bdl.area;
135 * set IOC if don't use position IPC
136 * and period_wakeup needed.
138 ioc = hda->no_ipc_position ?
139 !hstream->no_period_wakeup : 0;
141 for (i = 0; i < periods; i++) {
142 if (i == (periods - 1) && remain)
143 /* set the last small entry */
144 offset = hda_setup_bdle(sdev, dmab,
145 hstream, &bdl, offset,
148 offset = hda_setup_bdle(sdev, dmab,
149 hstream, &bdl, offset,
156 int hda_dsp_stream_spib_config(struct snd_sof_dev *sdev,
157 struct hdac_ext_stream *hext_stream,
158 int enable, u32 size)
160 struct hdac_stream *hstream = &hext_stream->hstream;
163 if (!sdev->bar[HDA_DSP_SPIB_BAR]) {
164 dev_err(sdev->dev, "error: address of spib capability is NULL\n");
168 mask = (1 << hstream->index);
170 /* enable/disable SPIB for the stream */
171 snd_sof_dsp_update_bits(sdev, HDA_DSP_SPIB_BAR,
172 SOF_HDA_ADSP_REG_CL_SPBFIFO_SPBFCCTL, mask,
173 enable << hstream->index);
175 /* set the SPIB value */
176 sof_io_write(sdev, hstream->spib_addr, size);
181 /* get next unused stream */
182 struct hdac_ext_stream *
183 hda_dsp_stream_get(struct snd_sof_dev *sdev, int direction, u32 flags)
185 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
186 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
187 struct hdac_bus *bus = sof_to_bus(sdev);
188 struct sof_intel_hda_stream *hda_stream;
189 struct hdac_ext_stream *hext_stream = NULL;
190 struct hdac_stream *s;
192 spin_lock_irq(&bus->reg_lock);
194 /* get an unused stream */
195 list_for_each_entry(s, &bus->stream_list, list) {
196 if (s->direction == direction && !s->opened) {
197 hext_stream = stream_to_hdac_ext_stream(s);
198 hda_stream = container_of(hext_stream,
199 struct sof_intel_hda_stream,
201 /* check if the host DMA channel is reserved */
202 if (hda_stream->host_reserved)
210 spin_unlock_irq(&bus->reg_lock);
214 dev_err(sdev->dev, "error: no free %s streams\n",
215 direction == SNDRV_PCM_STREAM_PLAYBACK ?
216 "playback" : "capture");
220 hda_stream->flags = flags;
223 * Prevent DMI Link L1 entry for streams that don't support it.
224 * Workaround to address a known issue with host DMA that results
225 * in xruns during pause/release in capture scenarios. This is not needed for the ACE IP.
227 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 &&
228 !(flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
229 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
231 HDA_VS_INTEL_EM2_L1SEN, 0);
232 hda->l1_disabled = true;
239 int hda_dsp_stream_put(struct snd_sof_dev *sdev, int direction, int stream_tag)
241 const struct sof_intel_dsp_desc *chip_info = get_chip_info(sdev->pdata);
242 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
243 struct hdac_bus *bus = sof_to_bus(sdev);
244 struct sof_intel_hda_stream *hda_stream;
245 struct hdac_ext_stream *hext_stream;
246 struct hdac_stream *s;
247 bool dmi_l1_enable = true;
250 spin_lock_irq(&bus->reg_lock);
253 * close stream matching the stream tag and check if there are any open streams
254 * that are DMI L1 incompatible.
256 list_for_each_entry(s, &bus->stream_list, list) {
257 hext_stream = stream_to_hdac_ext_stream(s);
258 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream, hext_stream);
263 if (s->direction == direction && s->stream_tag == stream_tag) {
266 } else if (!(hda_stream->flags & SOF_HDA_STREAM_DMI_L1_COMPATIBLE)) {
267 dmi_l1_enable = false;
271 spin_unlock_irq(&bus->reg_lock);
273 /* Enable DMI L1 if permitted */
274 if (chip_info->hw_ip_version < SOF_INTEL_ACE_1_0 && dmi_l1_enable) {
275 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_EM2,
276 HDA_VS_INTEL_EM2_L1SEN, HDA_VS_INTEL_EM2_L1SEN);
277 hda->l1_disabled = false;
281 dev_err(sdev->dev, "%s: stream_tag %d not opened!\n",
282 __func__, stream_tag);
289 static int hda_dsp_stream_reset(struct snd_sof_dev *sdev, struct hdac_stream *hstream)
291 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
292 int timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
295 /* enter stream reset */
296 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST,
297 SOF_STREAM_SD_OFFSET_CRST);
299 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
300 if (val & SOF_STREAM_SD_OFFSET_CRST)
304 dev_err(sdev->dev, "timeout waiting for stream reset\n");
308 timeout = HDA_DSP_STREAM_RESET_TIMEOUT;
310 /* exit stream reset and wait to read a zero before reading any other register */
311 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset, SOF_STREAM_SD_OFFSET_CRST, 0x0);
313 /* wait for hardware to report that stream is out of reset */
316 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, sd_offset);
317 if ((val & SOF_STREAM_SD_OFFSET_CRST) == 0)
321 dev_err(sdev->dev, "timeout waiting for stream to exit reset\n");
328 int hda_dsp_stream_trigger(struct snd_sof_dev *sdev,
329 struct hdac_ext_stream *hext_stream, int cmd)
331 struct hdac_stream *hstream = &hext_stream->hstream;
332 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
333 u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
337 /* cmd must be for audio stream */
339 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
340 if (!sdev->dspless_mode_selected)
343 case SNDRV_PCM_TRIGGER_START:
344 if (hstream->running)
347 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
349 1 << hstream->index);
351 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
353 SOF_HDA_SD_CTL_DMA_START |
354 SOF_HDA_CL_DMA_SD_INT_MASK,
355 SOF_HDA_SD_CTL_DMA_START |
356 SOF_HDA_CL_DMA_SD_INT_MASK);
358 ret = snd_sof_dsp_read_poll_timeout(sdev,
361 ((run & dma_start) == dma_start),
362 HDA_DSP_REG_POLL_INTERVAL_US,
363 HDA_DSP_STREAM_RUN_TIMEOUT);
366 hstream->running = true;
369 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
370 if (!sdev->dspless_mode_selected)
373 case SNDRV_PCM_TRIGGER_SUSPEND:
374 case SNDRV_PCM_TRIGGER_STOP:
375 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
377 SOF_HDA_SD_CTL_DMA_START |
378 SOF_HDA_CL_DMA_SD_INT_MASK, 0x0);
380 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
383 HDA_DSP_REG_POLL_INTERVAL_US,
384 HDA_DSP_STREAM_RUN_TIMEOUT);
387 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
388 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
389 SOF_HDA_CL_DMA_SD_INT_MASK);
391 hstream->running = false;
392 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
394 1 << hstream->index, 0x0);
398 dev_err(sdev->dev, "error: unknown command: %d\n", cmd);
403 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
406 "%s: cmd %d on %s: timeout on STREAM_SD_OFFSET read\n",
407 __func__, cmd, stream_name ? stream_name : "unknown stream");
414 /* minimal recommended programming for ICCMAX stream */
415 int hda_dsp_iccmax_stream_hw_params(struct snd_sof_dev *sdev, struct hdac_ext_stream *hext_stream,
416 struct snd_dma_buffer *dmab,
417 struct snd_pcm_hw_params *params)
419 struct hdac_stream *hstream = &hext_stream->hstream;
420 int sd_offset = SOF_STREAM_SD_OFFSET(hstream);
422 u32 mask = 0x1 << hstream->index;
425 dev_err(sdev->dev, "error: no stream available\n");
430 dev_err(sdev->dev, "error: no dma buffer allocated!\n");
435 *hstream->posbuf = 0;
437 /* reset BDL address */
438 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
439 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
441 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
442 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
447 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
449 dev_err(sdev->dev, "error: set up of BDL failed\n");
453 /* program BDL address */
454 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
455 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
456 (u32)hstream->bdl.addr);
457 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
458 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
459 upper_32_bits(hstream->bdl.addr));
461 /* program cyclic buffer length */
462 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
463 sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
466 /* program last valid index */
467 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
468 sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
469 0xffff, (hstream->frags - 1));
471 /* decouple host and link DMA, enable DSP features */
472 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
475 /* Follow HW recommendation to set the guardband value to 95us during FW boot */
476 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, HDA_VS_INTEL_LTRP,
477 HDA_VS_INTEL_LTRP_GB_MASK, HDA_LTRP_GB_VALUE_US);
480 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
481 SOF_HDA_SD_CTL_DMA_START, SOF_HDA_SD_CTL_DMA_START);
487 * prepare for common hdac registers settings, for both code loader
490 int hda_dsp_stream_hw_params(struct snd_sof_dev *sdev,
491 struct hdac_ext_stream *hext_stream,
492 struct snd_dma_buffer *dmab,
493 struct snd_pcm_hw_params *params)
495 const struct sof_intel_dsp_desc *chip = get_chip_info(sdev->pdata);
496 struct hdac_bus *bus = sof_to_bus(sdev);
497 struct hdac_stream *hstream;
499 u32 dma_start = SOF_HDA_SD_CTL_DMA_START;
504 dev_err(sdev->dev, "error: no stream available\n");
509 dev_err(sdev->dev, "error: no dma buffer allocated!\n");
513 hstream = &hext_stream->hstream;
514 sd_offset = SOF_STREAM_SD_OFFSET(hstream);
515 mask = BIT(hstream->index);
517 /* decouple host and link DMA if the DSP is used */
518 if (!sdev->dspless_mode_selected)
519 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
522 /* clear stream status */
523 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
524 SOF_HDA_CL_DMA_SD_INT_MASK |
525 SOF_HDA_SD_CTL_DMA_START, 0);
527 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
530 HDA_DSP_REG_POLL_INTERVAL_US,
531 HDA_DSP_STREAM_RUN_TIMEOUT);
534 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
537 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
538 __func__, stream_name ? stream_name : "unknown stream");
543 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
544 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
545 SOF_HDA_CL_DMA_SD_INT_MASK,
546 SOF_HDA_CL_DMA_SD_INT_MASK);
549 ret = hda_dsp_stream_reset(sdev, hstream);
554 *hstream->posbuf = 0;
556 /* reset BDL address */
557 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
558 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
560 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
561 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
564 /* clear stream status */
565 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
566 SOF_HDA_CL_DMA_SD_INT_MASK |
567 SOF_HDA_SD_CTL_DMA_START, 0);
569 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_HDA_BAR,
572 HDA_DSP_REG_POLL_INTERVAL_US,
573 HDA_DSP_STREAM_RUN_TIMEOUT);
576 char *stream_name = hda_hstream_dbg_get_stream_info_str(hstream);
579 "%s: on %s: timeout on STREAM_SD_OFFSET read1\n",
580 __func__, stream_name ? stream_name : "unknown stream");
585 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
586 sd_offset + SOF_HDA_ADSP_REG_SD_STS,
587 SOF_HDA_CL_DMA_SD_INT_MASK,
588 SOF_HDA_CL_DMA_SD_INT_MASK);
592 ret = hda_dsp_stream_setup_bdl(sdev, dmab, hstream);
594 dev_err(sdev->dev, "error: set up of BDL failed\n");
598 /* program stream tag to set up stream descriptor for DMA */
599 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
600 SOF_HDA_CL_SD_CTL_STREAM_TAG_MASK,
601 hstream->stream_tag <<
602 SOF_HDA_CL_SD_CTL_STREAM_TAG_SHIFT);
604 /* program cyclic buffer length */
605 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
606 sd_offset + SOF_HDA_ADSP_REG_SD_CBL,
610 * Recommended hardware programming sequence for HDAudio DMA format
611 * on earlier platforms - this is not needed on newer platforms
613 * 1. Put DMA into coupled mode by clearing PPCTL.PROCEN bit
614 * for corresponding stream index before the time of writing
615 * format to SDxFMT register.
617 * 3. Set PPCTL.PROCEN bit for corresponding stream index to
618 * enable decoupled mode
621 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
622 /* couple host and link DMA, disable DSP features */
623 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
626 /* program stream format */
627 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
629 SOF_HDA_ADSP_REG_SD_FORMAT,
630 0xffff, hstream->format_val);
632 if (!sdev->dspless_mode_selected && (chip->quirks & SOF_INTEL_PROCEN_FMT_QUIRK))
633 /* decouple host and link DMA, enable DSP features */
634 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
637 /* program last valid index */
638 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
639 sd_offset + SOF_HDA_ADSP_REG_SD_LVI,
640 0xffff, (hstream->frags - 1));
642 /* program BDL address */
643 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
644 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPL,
645 (u32)hstream->bdl.addr);
646 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR,
647 sd_offset + SOF_HDA_ADSP_REG_SD_BDLPU,
648 upper_32_bits(hstream->bdl.addr));
650 /* enable position buffer, if needed */
651 if (bus->use_posbuf && bus->posbuf.addr &&
652 !(snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE)
653 & SOF_HDA_ADSP_DPLBASE_ENABLE)) {
654 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPUBASE,
655 upper_32_bits(bus->posbuf.addr));
656 snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_ADSP_DPLBASE,
657 (u32)bus->posbuf.addr |
658 SOF_HDA_ADSP_DPLBASE_ENABLE);
661 /* set interrupt enable bits */
662 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, sd_offset,
663 SOF_HDA_CL_DMA_SD_INT_MASK,
664 SOF_HDA_CL_DMA_SD_INT_MASK);
667 if (hstream->direction == SNDRV_PCM_STREAM_PLAYBACK) {
669 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
671 SOF_HDA_ADSP_REG_SD_FIFOSIZE);
672 hstream->fifo_size &= SOF_HDA_SD_FIFOSIZE_FIFOS_MASK;
673 hstream->fifo_size += 1;
675 hstream->fifo_size = 0;
681 int hda_dsp_stream_hw_free(struct snd_sof_dev *sdev,
682 struct snd_pcm_substream *substream)
684 struct hdac_stream *hstream = substream->runtime->private_data;
685 struct hdac_ext_stream *hext_stream = container_of(hstream,
686 struct hdac_ext_stream,
690 ret = hda_dsp_stream_reset(sdev, hstream);
694 if (!sdev->dspless_mode_selected) {
695 struct hdac_bus *bus = sof_to_bus(sdev);
696 u32 mask = BIT(hstream->index);
698 spin_lock_irq(&bus->reg_lock);
699 /* couple host and link DMA if link DMA channel is idle */
700 if (!hext_stream->link_locked)
701 snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR,
702 SOF_HDA_REG_PP_PPCTL, mask, 0);
703 spin_unlock_irq(&bus->reg_lock);
706 hda_dsp_stream_spib_config(sdev, hext_stream, HDA_DSP_SPIB_DISABLE, 0);
708 hstream->substream = NULL;
713 bool hda_dsp_check_stream_irq(struct snd_sof_dev *sdev)
715 struct hdac_bus *bus = sof_to_bus(sdev);
719 /* The function can be called at irq thread, so use spin_lock_irq */
720 spin_lock_irq(&bus->reg_lock);
722 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
724 trace_sof_intel_hda_dsp_check_stream_irq(sdev, status);
726 /* if Register inaccessible, ignore it.*/
727 if (status != 0xffffffff)
730 spin_unlock_irq(&bus->reg_lock);
736 hda_dsp_compr_bytes_transferred(struct hdac_stream *hstream, int direction)
738 u64 buffer_size = hstream->bufsize;
739 u64 prev_pos, pos, num_bytes;
741 div64_u64_rem(hstream->curr_pos, buffer_size, &prev_pos);
742 pos = hda_dsp_stream_get_position(hstream, direction, false);
745 num_bytes = (buffer_size - prev_pos) + pos;
747 num_bytes = pos - prev_pos;
749 hstream->curr_pos += num_bytes;
752 static bool hda_dsp_stream_check(struct hdac_bus *bus, u32 status)
754 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
755 struct hdac_stream *s;
759 list_for_each_entry(s, &bus->stream_list, list) {
760 if (status & BIT(s->index) && s->opened) {
761 sd_status = readb(s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
763 trace_sof_intel_hda_dsp_stream_status(bus->dev, s, sd_status);
765 writeb(sd_status, s->sd_addr + SOF_HDA_ADSP_REG_SD_STS);
770 if ((sd_status & SOF_HDA_CL_DMA_SD_INT_COMPLETE) == 0)
772 if (!s->substream && !s->cstream) {
774 * when no substream is found, the DMA may used for code loading
775 * or data transfers which can rely on wait_for_completion()
777 struct sof_intel_hda_stream *hda_stream;
778 struct hdac_ext_stream *hext_stream;
780 hext_stream = stream_to_hdac_ext_stream(s);
781 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream,
784 complete(&hda_stream->ioc);
788 /* Inform ALSA only if the IPC position is not used */
789 if (s->substream && sof_hda->no_ipc_position) {
790 snd_sof_pcm_period_elapsed(s->substream);
791 } else if (s->cstream) {
792 hda_dsp_compr_bytes_transferred(s, s->cstream->direction);
793 snd_compr_fragment_elapsed(s->cstream);
801 irqreturn_t hda_dsp_stream_threaded_handler(int irq, void *context)
803 struct snd_sof_dev *sdev = context;
804 struct hdac_bus *bus = sof_to_bus(sdev);
810 * Loop 10 times to handle missed interrupts caused by
811 * unsolicited responses from the codec
813 for (i = 0, active = true; i < 10 && active; i++) {
814 spin_lock_irq(&bus->reg_lock);
816 status = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS);
819 active = hda_dsp_stream_check(bus, status);
821 /* check and clear RIRB interrupt */
822 if (status & AZX_INT_CTRL_EN) {
823 active |= hda_codec_check_rirb_status(sdev);
825 spin_unlock_irq(&bus->reg_lock);
831 int hda_dsp_stream_init(struct snd_sof_dev *sdev)
833 struct hdac_bus *bus = sof_to_bus(sdev);
834 struct hdac_ext_stream *hext_stream;
835 struct hdac_stream *hstream;
836 struct pci_dev *pci = to_pci_dev(sdev->dev);
837 struct sof_intel_hda_dev *sof_hda = bus_to_sof_hda(bus);
839 int i, num_playback, num_capture, num_total, ret;
842 gcap = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR, SOF_HDA_GCAP);
843 dev_dbg(sdev->dev, "hda global caps = 0x%x\n", gcap);
845 /* get stream count from GCAP */
846 num_capture = (gcap >> 8) & 0x0f;
847 num_playback = (gcap >> 12) & 0x0f;
848 num_total = num_playback + num_capture;
850 dev_dbg(sdev->dev, "detected %d playback and %d capture streams\n",
851 num_playback, num_capture);
853 if (num_playback >= SOF_HDA_PLAYBACK_STREAMS) {
854 dev_err(sdev->dev, "error: too many playback streams %d\n",
859 if (num_capture >= SOF_HDA_CAPTURE_STREAMS) {
860 dev_err(sdev->dev, "error: too many capture streams %d\n",
866 * mem alloc for the position buffer
867 * TODO: check position buffer update
869 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
870 SOF_HDA_DPIB_ENTRY_SIZE * num_total,
873 dev_err(sdev->dev, "error: posbuffer dma alloc failed\n");
878 * mem alloc for the CORB/RIRB ringbuffers - this will be used only for
881 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
882 PAGE_SIZE, &bus->rb);
884 dev_err(sdev->dev, "error: RB alloc failed\n");
888 /* create capture and playback streams */
889 for (i = 0; i < num_total; i++) {
890 struct sof_intel_hda_stream *hda_stream;
892 hda_stream = devm_kzalloc(sdev->dev, sizeof(*hda_stream),
897 hda_stream->sdev = sdev;
898 init_completion(&hda_stream->ioc);
900 hext_stream = &hda_stream->hext_stream;
902 if (sdev->bar[HDA_DSP_PP_BAR]) {
903 hext_stream->pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
904 SOF_HDA_PPHC_BASE + SOF_HDA_PPHC_INTERVAL * i;
906 hext_stream->pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
907 SOF_HDA_PPLC_BASE + SOF_HDA_PPLC_MULTI * num_total +
908 SOF_HDA_PPLC_INTERVAL * i;
911 hstream = &hext_stream->hstream;
913 /* do we support SPIB */
914 if (sdev->bar[HDA_DSP_SPIB_BAR]) {
915 hstream->spib_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
916 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
919 hstream->fifo_addr = sdev->bar[HDA_DSP_SPIB_BAR] +
920 SOF_HDA_SPIB_BASE + SOF_HDA_SPIB_INTERVAL * i +
921 SOF_HDA_SPIB_MAXFIFO;
925 hstream->sd_int_sta_mask = 1 << i;
927 sd_offset = SOF_STREAM_SD_OFFSET(hstream);
928 hstream->sd_addr = sdev->bar[HDA_DSP_HDA_BAR] + sd_offset;
929 hstream->opened = false;
930 hstream->running = false;
932 if (i < num_capture) {
933 hstream->stream_tag = i + 1;
934 hstream->direction = SNDRV_PCM_STREAM_CAPTURE;
936 hstream->stream_tag = i - num_capture + 1;
937 hstream->direction = SNDRV_PCM_STREAM_PLAYBACK;
940 /* mem alloc for stream BDL */
941 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev,
942 HDA_DSP_BDL_SIZE, &hstream->bdl);
944 dev_err(sdev->dev, "error: stream bdl dma alloc failed\n");
948 hstream->posbuf = (__le32 *)(bus->posbuf.area +
949 (hstream->index) * 8);
951 list_add_tail(&hstream->list, &bus->stream_list);
954 /* store total stream count (playback + capture) from GCAP */
955 sof_hda->stream_max = num_total;
957 /* store stream count from GCAP required for CHAIN_DMA */
958 if (sdev->pdata->ipc_type == SOF_IPC_TYPE_4) {
959 struct sof_ipc4_fw_data *ipc4_data = sdev->private;
961 ipc4_data->num_playback_streams = num_playback;
962 ipc4_data->num_capture_streams = num_capture;
968 void hda_dsp_stream_free(struct snd_sof_dev *sdev)
970 struct hdac_bus *bus = sof_to_bus(sdev);
971 struct hdac_stream *s, *_s;
972 struct hdac_ext_stream *hext_stream;
973 struct sof_intel_hda_stream *hda_stream;
975 /* free position buffer */
976 if (bus->posbuf.area)
977 snd_dma_free_pages(&bus->posbuf);
979 /* free CORB/RIRB buffer - only used for HDaudio codecs */
981 snd_dma_free_pages(&bus->rb);
983 list_for_each_entry_safe(s, _s, &bus->stream_list, list) {
986 /* free bdl buffer */
988 snd_dma_free_pages(&s->bdl);
990 hext_stream = stream_to_hdac_ext_stream(s);
991 hda_stream = container_of(hext_stream, struct sof_intel_hda_stream,
993 devm_kfree(sdev->dev, hda_stream);
997 snd_pcm_uframes_t hda_dsp_stream_get_position(struct hdac_stream *hstream,
998 int direction, bool can_sleep)
1000 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
1001 struct sof_intel_hda_stream *hda_stream = hstream_to_sof_hda_stream(hext_stream);
1002 struct snd_sof_dev *sdev = hda_stream->sdev;
1003 snd_pcm_uframes_t pos;
1005 switch (sof_hda_position_quirk) {
1006 case SOF_HDA_POSITION_QUIRK_USE_SKYLAKE_LEGACY:
1008 * This legacy code, inherited from the Skylake driver,
1009 * mixes DPIB registers and DPIB DDR updates and
1010 * does not seem to follow any known hardware recommendations.
1011 * It's not clear e.g. why there is a different flow
1012 * for capture and playback, the only information that matters is
1013 * what traffic class is used, and on all SOF-enabled platforms
1014 * only VC0 is supported so the work-around was likely not necessary
1015 * and quite possibly wrong.
1018 /* DPIB/posbuf position mode:
1019 * For Playback, Use DPIB register from HDA space which
1020 * reflects the actual data transferred.
1021 * For Capture, Use the position buffer for pointer, as DPIB
1022 * is not accurate enough, its update may be completed
1023 * earlier than the data written to DDR.
1025 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1026 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1027 AZX_REG_VS_SDXDPIB_XBASE +
1028 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1032 * For capture stream, we need more workaround to fix the
1033 * position incorrect issue:
1035 * 1. Wait at least 20us before reading position buffer after
1036 * the interrupt generated(IOC), to make sure position update
1037 * happens on frame boundary i.e. 20.833uSec for 48KHz.
1038 * 2. Perform a dummy Read to DPIB register to flush DMA
1040 * 3. Read the DMA Position from posbuf. Now the readback
1041 * value should be >= period boundary.
1044 usleep_range(20, 21);
1046 snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1047 AZX_REG_VS_SDXDPIB_XBASE +
1048 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1050 pos = snd_hdac_stream_get_pos_posbuf(hstream);
1053 case SOF_HDA_POSITION_QUIRK_USE_DPIB_REGISTERS:
1055 * In case VC1 traffic is disabled this is the recommended option
1057 pos = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
1058 AZX_REG_VS_SDXDPIB_XBASE +
1059 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1062 case SOF_HDA_POSITION_QUIRK_USE_DPIB_DDR_UPDATE:
1064 * This is the recommended option when VC1 is enabled.
1065 * While this isn't needed for SOF platforms it's added for
1066 * consistency and debug.
1068 pos = snd_hdac_stream_get_pos_posbuf(hstream);
1071 dev_err_once(sdev->dev, "hda_position_quirk value %d not supported\n",
1072 sof_hda_position_quirk);
1077 if (pos >= hstream->bufsize)
1083 #define merge_u64(u32_u, u32_l) (((u64)(u32_u) << 32) | (u32_l))
1086 * hda_dsp_get_stream_llp - Retrieve the LLP (Linear Link Position) of the stream
1088 * @component: ASoC component
1089 * @substream: PCM substream
1091 * Returns the raw Linear Link Position value
1093 u64 hda_dsp_get_stream_llp(struct snd_sof_dev *sdev,
1094 struct snd_soc_component *component,
1095 struct snd_pcm_substream *substream)
1097 struct hdac_stream *hstream = substream->runtime->private_data;
1098 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
1102 * The pplc_addr have been calculated during probe in
1103 * hda_dsp_stream_init():
1104 * pplc_addr = sdev->bar[HDA_DSP_PP_BAR] +
1105 * SOF_HDA_PPLC_BASE +
1106 * SOF_HDA_PPLC_MULTI * total_stream +
1107 * SOF_HDA_PPLC_INTERVAL * stream_index
1109 * Use this pre-calculated address to avoid repeated re-calculation.
1111 llp_l = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPL);
1112 llp_u = readl(hext_stream->pplc_addr + AZX_REG_PPLCLLPU);
1114 /* Compensate the LLP counter with the saved offset */
1115 if (hext_stream->pplcllpl || hext_stream->pplcllpu)
1116 return merge_u64(llp_u, llp_l) -
1117 merge_u64(hext_stream->pplcllpu, hext_stream->pplcllpl);
1119 return merge_u64(llp_u, llp_l);
1123 * hda_dsp_get_stream_ldp - Retrieve the LDP (Linear DMA Position) of the stream
1125 * @component: ASoC component
1126 * @substream: PCM substream
1128 * Returns the raw Linear Link Position value
1130 u64 hda_dsp_get_stream_ldp(struct snd_sof_dev *sdev,
1131 struct snd_soc_component *component,
1132 struct snd_pcm_substream *substream)
1134 struct hdac_stream *hstream = substream->runtime->private_data;
1135 struct hdac_ext_stream *hext_stream = stream_to_hdac_ext_stream(hstream);
1139 * The pphc_addr have been calculated during probe in
1140 * hda_dsp_stream_init():
1141 * pphc_addr = sdev->bar[HDA_DSP_PP_BAR] +
1142 * SOF_HDA_PPHC_BASE +
1143 * SOF_HDA_PPHC_INTERVAL * stream_index
1145 * Use this pre-calculated address to avoid repeated re-calculation.
1147 ldp_l = readl(hext_stream->pphc_addr + AZX_REG_PPHCLDPL);
1148 ldp_u = readl(hext_stream->pphc_addr + AZX_REG_PPHCLDPU);
1150 return ((u64)ldp_u << 32) | ldp_l;