1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for generic Intel audio DSP HDA IP
18 #include <linux/module.h>
19 #include <sound/hdaudio_ext.h>
20 #include <sound/hda_register.h>
21 #include <trace/events/sof_intel.h>
22 #include "../sof-audio.h"
27 static bool hda_enable_trace_D0I3_S0;
28 #if IS_ENABLED(CONFIG_SND_SOC_SOF_DEBUG)
29 module_param_named(enable_trace_D0I3_S0, hda_enable_trace_D0I3_S0, bool, 0444);
30 MODULE_PARM_DESC(enable_trace_D0I3_S0,
31 "SOF HDA enable trace when the DSP is in D0I3 in S0");
38 static int hda_dsp_core_reset_enter(struct snd_sof_dev *sdev, unsigned int core_mask)
44 /* set reset bits for cores */
45 reset = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
46 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
50 /* poll with timeout to check if operation successful */
51 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
52 HDA_DSP_REG_ADSPCS, adspcs,
53 ((adspcs & reset) == reset),
54 HDA_DSP_REG_POLL_INTERVAL_US,
55 HDA_DSP_RESET_TIMEOUT_US);
58 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
63 /* has core entered reset ? */
64 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
66 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) !=
67 HDA_DSP_ADSPCS_CRST_MASK(core_mask)) {
69 "error: reset enter failed: core_mask %x adspcs 0x%x\n",
77 static int hda_dsp_core_reset_leave(struct snd_sof_dev *sdev, unsigned int core_mask)
83 /* clear reset bits for cores */
84 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
86 HDA_DSP_ADSPCS_CRST_MASK(core_mask),
89 /* poll with timeout to check if operation successful */
90 crst = HDA_DSP_ADSPCS_CRST_MASK(core_mask);
91 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
92 HDA_DSP_REG_ADSPCS, adspcs,
94 HDA_DSP_REG_POLL_INTERVAL_US,
95 HDA_DSP_RESET_TIMEOUT_US);
99 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
104 /* has core left reset ? */
105 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
107 if ((adspcs & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) != 0) {
109 "error: reset leave failed: core_mask %x adspcs 0x%x\n",
117 int hda_dsp_core_stall_reset(struct snd_sof_dev *sdev, unsigned int core_mask)
120 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
122 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
123 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
125 /* set reset state */
126 return hda_dsp_core_reset_enter(sdev, core_mask);
129 bool hda_dsp_core_is_enabled(struct snd_sof_dev *sdev, unsigned int core_mask)
134 val = snd_sof_dsp_read(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS);
136 #define MASK_IS_EQUAL(v, m, field) ({ \
141 is_enable = MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_CPA_MASK) &&
142 MASK_IS_EQUAL(val, core_mask, HDA_DSP_ADSPCS_SPA_MASK) &&
143 !(val & HDA_DSP_ADSPCS_CRST_MASK(core_mask)) &&
144 !(val & HDA_DSP_ADSPCS_CSTALL_MASK(core_mask));
148 dev_dbg(sdev->dev, "DSP core(s) enabled? %d : core_mask %x\n",
149 is_enable, core_mask);
154 int hda_dsp_core_run(struct snd_sof_dev *sdev, unsigned int core_mask)
158 /* leave reset state */
159 ret = hda_dsp_core_reset_leave(sdev, core_mask);
164 dev_dbg(sdev->dev, "unstall/run core: core_mask = %x\n", core_mask);
165 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
167 HDA_DSP_ADSPCS_CSTALL_MASK(core_mask),
170 /* is core now running ? */
171 if (!hda_dsp_core_is_enabled(sdev, core_mask)) {
172 hda_dsp_core_stall_reset(sdev, core_mask);
173 dev_err(sdev->dev, "error: DSP start core failed: core_mask %x\n",
185 int hda_dsp_core_power_up(struct snd_sof_dev *sdev, unsigned int core_mask)
187 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
188 const struct sof_intel_dsp_desc *chip = hda->desc;
193 /* restrict core_mask to host managed cores mask */
194 core_mask &= chip->host_managed_cores_mask;
195 /* return if core_mask is not valid */
200 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPCS,
201 HDA_DSP_ADSPCS_SPA_MASK(core_mask),
202 HDA_DSP_ADSPCS_SPA_MASK(core_mask));
204 /* poll with timeout to check if operation successful */
205 cpa = HDA_DSP_ADSPCS_CPA_MASK(core_mask);
206 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
207 HDA_DSP_REG_ADSPCS, adspcs,
208 (adspcs & cpa) == cpa,
209 HDA_DSP_REG_POLL_INTERVAL_US,
210 HDA_DSP_RESET_TIMEOUT_US);
213 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
218 /* did core power up ? */
219 adspcs = snd_sof_dsp_read(sdev, HDA_DSP_BAR,
221 if ((adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)) !=
222 HDA_DSP_ADSPCS_CPA_MASK(core_mask)) {
224 "error: power up core failed core_mask %xadspcs 0x%x\n",
232 static int hda_dsp_core_power_down(struct snd_sof_dev *sdev, unsigned int core_mask)
238 snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
240 HDA_DSP_ADSPCS_SPA_MASK(core_mask), 0);
242 ret = snd_sof_dsp_read_poll_timeout(sdev, HDA_DSP_BAR,
243 HDA_DSP_REG_ADSPCS, adspcs,
244 !(adspcs & HDA_DSP_ADSPCS_CPA_MASK(core_mask)),
245 HDA_DSP_REG_POLL_INTERVAL_US,
246 HDA_DSP_PD_TIMEOUT * USEC_PER_MSEC);
249 "error: %s: timeout on HDA_DSP_REG_ADSPCS read\n",
255 int hda_dsp_enable_core(struct snd_sof_dev *sdev, unsigned int core_mask)
257 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
258 const struct sof_intel_dsp_desc *chip = hda->desc;
261 /* restrict core_mask to host managed cores mask */
262 core_mask &= chip->host_managed_cores_mask;
264 /* return if core_mask is not valid or cores are already enabled */
265 if (!core_mask || hda_dsp_core_is_enabled(sdev, core_mask))
269 ret = hda_dsp_core_power_up(sdev, core_mask);
271 dev_err(sdev->dev, "error: dsp core power up failed: core_mask %x\n",
276 return hda_dsp_core_run(sdev, core_mask);
279 int hda_dsp_core_reset_power_down(struct snd_sof_dev *sdev,
280 unsigned int core_mask)
282 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
283 const struct sof_intel_dsp_desc *chip = hda->desc;
286 /* restrict core_mask to host managed cores mask */
287 core_mask &= chip->host_managed_cores_mask;
289 /* return if core_mask is not valid */
293 /* place core in reset prior to power down */
294 ret = hda_dsp_core_stall_reset(sdev, core_mask);
296 dev_err(sdev->dev, "error: dsp core reset failed: core_mask %x\n",
301 /* power down core */
302 ret = hda_dsp_core_power_down(sdev, core_mask);
304 dev_err(sdev->dev, "error: dsp core power down fail mask %x: %d\n",
309 /* make sure we are in OFF state */
310 if (hda_dsp_core_is_enabled(sdev, core_mask)) {
311 dev_err(sdev->dev, "error: dsp core disable fail mask %x: %d\n",
319 void hda_dsp_ipc_int_enable(struct snd_sof_dev *sdev)
321 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
322 const struct sof_intel_dsp_desc *chip = hda->desc;
324 /* enable IPC DONE and BUSY interrupts */
325 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
326 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY,
327 HDA_DSP_REG_HIPCCTL_DONE | HDA_DSP_REG_HIPCCTL_BUSY);
329 /* enable IPC interrupt */
330 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
331 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
334 void hda_dsp_ipc_int_disable(struct snd_sof_dev *sdev)
336 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
337 const struct sof_intel_dsp_desc *chip = hda->desc;
339 /* disable IPC interrupt */
340 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
341 HDA_DSP_ADSPIC_IPC, 0);
343 /* disable IPC BUSY and DONE interrupt */
344 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, chip->ipc_ctl,
345 HDA_DSP_REG_HIPCCTL_BUSY | HDA_DSP_REG_HIPCCTL_DONE, 0);
348 static int hda_dsp_wait_d0i3c_done(struct snd_sof_dev *sdev)
350 int retry = HDA_DSP_REG_POLL_RETRY_COUNT;
351 struct snd_sof_pdata *pdata = sdev->pdata;
352 const struct sof_intel_dsp_desc *chip;
354 chip = get_chip_info(pdata);
355 while (snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset) &
356 SOF_HDA_VS_D0I3C_CIP) {
359 usleep_range(10, 15);
365 static int hda_dsp_send_pm_gate_ipc(struct snd_sof_dev *sdev, u32 flags)
367 const struct sof_ipc_pm_ops *pm_ops = sof_ipc_get_ops(sdev, pm);
369 if (pm_ops && pm_ops->set_pm_gate)
370 return pm_ops->set_pm_gate(sdev, flags);
375 static int hda_dsp_update_d0i3c_register(struct snd_sof_dev *sdev, u8 value)
377 struct snd_sof_pdata *pdata = sdev->pdata;
378 const struct sof_intel_dsp_desc *chip;
382 chip = get_chip_info(pdata);
384 /* Write to D0I3C after Command-In-Progress bit is cleared */
385 ret = hda_dsp_wait_d0i3c_done(sdev);
387 dev_err(sdev->dev, "CIP timeout before D0I3C update!\n");
391 /* Update D0I3C register */
392 snd_sof_dsp_update8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset,
393 SOF_HDA_VS_D0I3C_I3, value);
396 * The value written to the D0I3C::I3 bit may not be taken into account immediately.
397 * A delay is recommended before checking if D0I3C::CIP is cleared
399 usleep_range(30, 40);
401 /* Wait for cmd in progress to be cleared before exiting the function */
402 ret = hda_dsp_wait_d0i3c_done(sdev);
404 dev_err(sdev->dev, "CIP timeout after D0I3C update!\n");
408 reg = snd_sof_dsp_read8(sdev, HDA_DSP_HDA_BAR, chip->d0i3_offset);
409 /* Confirm d0i3 state changed with paranoia check */
410 if ((reg ^ value) & SOF_HDA_VS_D0I3C_I3) {
411 dev_err(sdev->dev, "failed to update D0I3C!\n");
415 trace_sof_intel_D0I3C_updated(sdev, reg);
421 * d0i3 streaming is enabled if all the active streams can
422 * work in d0i3 state and playback is enabled
424 static bool hda_dsp_d0i3_streaming_applicable(struct snd_sof_dev *sdev)
426 struct snd_pcm_substream *substream;
427 struct snd_sof_pcm *spcm;
428 bool playback_active = false;
431 list_for_each_entry(spcm, &sdev->pcm_list, list) {
432 for_each_pcm_streams(dir) {
433 substream = spcm->stream[dir].substream;
434 if (!substream || !substream->runtime)
437 if (!spcm->stream[dir].d0i3_compatible)
440 if (dir == SNDRV_PCM_STREAM_PLAYBACK)
441 playback_active = true;
445 return playback_active;
448 static int hda_dsp_set_D0_state(struct snd_sof_dev *sdev,
449 const struct sof_dsp_power_state *target_state)
456 * Sanity check for illegal state transitions
457 * The only allowed transitions are:
462 switch (sdev->dsp_power_state.state) {
464 /* Follow the sequence below for D0 substate transitions */
467 /* Follow regular flow for D3 -> D0 transition */
470 dev_err(sdev->dev, "error: transition from %d to %d not allowed\n",
471 sdev->dsp_power_state.state, target_state->state);
475 /* Set flags and register value for D0 target substate */
476 if (target_state->substate == SOF_HDA_DSP_PM_D0I3) {
477 value = SOF_HDA_VS_D0I3C_I3;
480 * Trace DMA need to be disabled when the DSP enters
481 * D0I3 for S0Ix suspend, but it can be kept enabled
482 * when the DSP enters D0I3 while the system is in S0
485 if (!sdev->fw_trace_is_supported ||
486 !hda_enable_trace_D0I3_S0 ||
487 sdev->system_suspend_target != SOF_SUSPEND_NONE)
488 flags = HDA_PM_NO_DMA_TRACE;
490 if (hda_dsp_d0i3_streaming_applicable(sdev))
491 flags |= HDA_PM_PG_STREAMING;
493 /* prevent power gating in D0I0 */
497 /* update D0I3C register */
498 ret = hda_dsp_update_d0i3c_register(sdev, value);
503 * Notify the DSP of the state change.
504 * If this IPC fails, revert the D0I3C register update in order
505 * to prevent partial state change.
507 ret = hda_dsp_send_pm_gate_ipc(sdev, flags);
510 "error: PM_GATE ipc error %d\n", ret);
517 /* fallback to the previous register value */
518 value = value ? 0 : SOF_HDA_VS_D0I3C_I3;
521 * This can fail but return the IPC error to signal that
522 * the state change failed.
524 hda_dsp_update_d0i3c_register(sdev, value);
529 /* helper to log DSP state */
530 static void hda_dsp_state_log(struct snd_sof_dev *sdev)
532 switch (sdev->dsp_power_state.state) {
534 switch (sdev->dsp_power_state.substate) {
535 case SOF_HDA_DSP_PM_D0I0:
536 dev_dbg(sdev->dev, "Current DSP power state: D0I0\n");
538 case SOF_HDA_DSP_PM_D0I3:
539 dev_dbg(sdev->dev, "Current DSP power state: D0I3\n");
542 dev_dbg(sdev->dev, "Unknown DSP D0 substate: %d\n",
543 sdev->dsp_power_state.substate);
548 dev_dbg(sdev->dev, "Current DSP power state: D1\n");
551 dev_dbg(sdev->dev, "Current DSP power state: D2\n");
554 dev_dbg(sdev->dev, "Current DSP power state: D3\n");
557 dev_dbg(sdev->dev, "Unknown DSP power state: %d\n",
558 sdev->dsp_power_state.state);
564 * All DSP power state transitions are initiated by the driver.
565 * If the requested state change fails, the error is simply returned.
566 * Further state transitions are attempted only when the set_power_save() op
567 * is called again either because of a new IPC sent to the DSP or
568 * during system suspend/resume.
570 int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
571 const struct sof_dsp_power_state *target_state)
576 * When the DSP is already in D0I3 and the target state is D0I3,
577 * it could be the case that the DSP is in D0I3 during S0
578 * and the system is suspending to S0Ix. Therefore,
579 * hda_dsp_set_D0_state() must be called to disable trace DMA
580 * by sending the PM_GATE IPC to the FW.
582 if (target_state->substate == SOF_HDA_DSP_PM_D0I3 &&
583 sdev->system_suspend_target == SOF_SUSPEND_S0IX)
587 * For all other cases, return without doing anything if
588 * the DSP is already in the target state.
590 if (target_state->state == sdev->dsp_power_state.state &&
591 target_state->substate == sdev->dsp_power_state.substate)
595 switch (target_state->state) {
597 ret = hda_dsp_set_D0_state(sdev, target_state);
600 /* The only allowed transition is: D0I0 -> D3 */
601 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0 &&
602 sdev->dsp_power_state.substate == SOF_HDA_DSP_PM_D0I0)
606 "error: transition from %d to %d not allowed\n",
607 sdev->dsp_power_state.state, target_state->state);
610 dev_err(sdev->dev, "error: target state unsupported %d\n",
611 target_state->state);
616 "failed to set requested target DSP state %d substate %d\n",
617 target_state->state, target_state->substate);
621 sdev->dsp_power_state = *target_state;
622 hda_dsp_state_log(sdev);
627 * Audio DSP states may transform as below:-
629 * Opportunistic D0I3 in S0
630 * Runtime +---------------------+ Delayed D0i3 work timeout
631 * suspend | +--------------------+
632 * +------------+ D0I0(active) | |
633 * | | <---------------+ |
634 * | +--------> | New IPC | |
635 * | |Runtime +--^--+---------^--+--+ (via mailbox) | |
636 * | |resume | | | | | |
638 * | | System| | | | | |
639 * | | resume| | S3/S0IX | | | |
640 * | | | | suspend | | S0IX | |
641 * | | | | | |suspend | |
644 * +-v---+-----------+--v-------+ | | +------+----v----+
645 * | | | +-----------> |
646 * | D3 (suspended) | | | D0I3 |
647 * | | +--------------+ |
648 * | | System resume | |
649 * +----------------------------+ +----------------+
651 * S0IX suspend: The DSP is in D0I3 if any D0I3-compatible streams
652 * ignored the suspend trigger. Otherwise the DSP
656 static int hda_suspend(struct snd_sof_dev *sdev, bool runtime_suspend)
658 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
659 const struct sof_intel_dsp_desc *chip = hda->desc;
660 struct hdac_bus *bus = sof_to_bus(sdev);
664 * The memory used for IMR boot loses its content in deeper than S3 state
665 * We must not try IMR boot on next power up (as it will fail).
667 * In case of firmware crash or boot failure set the skip_imr_boot to true
668 * as well in order to try to re-load the firmware to do a 'cold' boot.
670 if (sdev->system_suspend_target > SOF_SUSPEND_S3 ||
671 sdev->fw_state == SOF_FW_CRASHED ||
672 sdev->fw_state == SOF_FW_BOOT_FAILED)
673 hda->skip_imr_boot = true;
675 ret = chip->disable_interrupts(sdev);
679 hda_codec_jack_wake_enable(sdev, runtime_suspend);
681 /* power down all hda links */
682 hda_bus_ml_suspend(bus);
684 ret = chip->power_down_dsp(sdev);
686 dev_err(sdev->dev, "failed to power down DSP during suspend\n");
690 /* reset ref counts for all cores */
691 for (j = 0; j < chip->cores_num; j++)
692 sdev->dsp_core_ref_count[j] = 0;
694 /* disable ppcap interrupt */
695 hda_dsp_ctrl_ppcap_enable(sdev, false);
696 hda_dsp_ctrl_ppcap_int_enable(sdev, false);
698 /* disable hda bus irq and streams */
699 hda_dsp_ctrl_stop_chip(sdev);
701 /* disable LP retention mode */
702 snd_sof_pci_update_bits(sdev, PCI_PGCTL,
703 PCI_PGCTL_LSRMD_MASK, PCI_PGCTL_LSRMD_MASK);
705 /* reset controller */
706 ret = hda_dsp_ctrl_link_reset(sdev, true);
709 "error: failed to reset controller during suspend\n");
713 /* display codec can powered off after link reset */
714 hda_codec_i915_display_power(sdev, false);
719 static int hda_resume(struct snd_sof_dev *sdev, bool runtime_resume)
723 /* display codec must be powered before link reset */
724 hda_codec_i915_display_power(sdev, true);
727 * clear TCSEL to clear playback on some HD Audio
728 * codecs. PCI TCSEL is defined in the Intel manuals.
730 snd_sof_pci_update_bits(sdev, PCI_TCSEL, 0x07, 0);
732 /* reset and start hda controller */
733 ret = hda_dsp_ctrl_init_chip(sdev);
736 "error: failed to start controller after resume\n");
740 /* check jack status */
741 if (runtime_resume) {
742 hda_codec_jack_wake_enable(sdev, false);
743 if (sdev->system_suspend_target == SOF_SUSPEND_NONE)
744 hda_codec_jack_check(sdev);
747 /* enable ppcap interrupt */
748 hda_dsp_ctrl_ppcap_enable(sdev, true);
749 hda_dsp_ctrl_ppcap_int_enable(sdev, true);
752 /* display codec can powered off after controller init */
753 hda_codec_i915_display_power(sdev, false);
758 int hda_dsp_resume(struct snd_sof_dev *sdev)
760 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
761 struct hdac_bus *bus = sof_to_bus(sdev);
762 struct pci_dev *pci = to_pci_dev(sdev->dev);
763 const struct sof_dsp_power_state target_state = {
764 .state = SOF_DSP_PM_D0,
765 .substate = SOF_HDA_DSP_PM_D0I0,
769 /* resume from D0I3 */
770 if (sdev->dsp_power_state.state == SOF_DSP_PM_D0) {
771 ret = hda_bus_ml_resume(bus);
774 "error %d in %s: failed to power up links",
779 /* set up CORB/RIRB buffers if was on before suspend */
780 hda_codec_resume_cmd_io(sdev);
782 /* Set DSP power state */
783 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
785 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
786 target_state.state, target_state.substate);
790 /* restore L1SEN bit */
791 if (hda->l1_support_changed)
792 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
794 HDA_VS_INTEL_EM2_L1SEN, 0);
796 /* restore and disable the system wakeup */
797 pci_restore_state(pci);
798 disable_irq_wake(pci->irq);
802 /* init hda controller. DSP cores will be powered up during fw boot */
803 ret = hda_resume(sdev, false);
807 return snd_sof_dsp_set_power_state(sdev, &target_state);
810 int hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
812 const struct sof_dsp_power_state target_state = {
813 .state = SOF_DSP_PM_D0,
817 /* init hda controller. DSP cores will be powered up during fw boot */
818 ret = hda_resume(sdev, true);
822 return snd_sof_dsp_set_power_state(sdev, &target_state);
825 int hda_dsp_runtime_idle(struct snd_sof_dev *sdev)
827 struct hdac_bus *hbus = sof_to_bus(sdev);
829 if (hbus->codec_powered) {
830 dev_dbg(sdev->dev, "some codecs still powered (%08X), not idle\n",
831 (unsigned int)hbus->codec_powered);
838 int hda_dsp_runtime_suspend(struct snd_sof_dev *sdev)
840 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
841 const struct sof_dsp_power_state target_state = {
842 .state = SOF_DSP_PM_D3,
846 /* cancel any attempt for DSP D0I3 */
847 cancel_delayed_work_sync(&hda->d0i3_work);
849 /* stop hda controller and power dsp off */
850 ret = hda_suspend(sdev, true);
854 return snd_sof_dsp_set_power_state(sdev, &target_state);
857 int hda_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
859 struct sof_intel_hda_dev *hda = sdev->pdata->hw_pdata;
860 struct hdac_bus *bus = sof_to_bus(sdev);
861 struct pci_dev *pci = to_pci_dev(sdev->dev);
862 const struct sof_dsp_power_state target_dsp_state = {
863 .state = target_state,
864 .substate = target_state == SOF_DSP_PM_D0 ?
865 SOF_HDA_DSP_PM_D0I3 : 0,
869 /* cancel any attempt for DSP D0I3 */
870 cancel_delayed_work_sync(&hda->d0i3_work);
872 if (target_state == SOF_DSP_PM_D0) {
873 /* Set DSP power state */
874 ret = snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
876 dev_err(sdev->dev, "error: setting dsp state %d substate %d\n",
877 target_dsp_state.state,
878 target_dsp_state.substate);
882 /* enable L1SEN to make sure the system can enter S0Ix */
883 hda->l1_support_changed =
884 snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
886 HDA_VS_INTEL_EM2_L1SEN,
887 HDA_VS_INTEL_EM2_L1SEN);
889 /* stop the CORB/RIRB DMA if it is On */
890 hda_codec_suspend_cmd_io(sdev);
892 /* no link can be powered in s0ix state */
893 ret = hda_bus_ml_suspend(bus);
896 "error %d in %s: failed to power down links",
901 /* enable the system waking up via IPC IRQ */
902 enable_irq_wake(pci->irq);
907 /* stop hda controller and power dsp off */
908 ret = hda_suspend(sdev, false);
910 dev_err(bus->dev, "error: suspending dsp\n");
914 return snd_sof_dsp_set_power_state(sdev, &target_dsp_state);
917 static unsigned int hda_dsp_check_for_dma_streams(struct snd_sof_dev *sdev)
919 struct hdac_bus *bus = sof_to_bus(sdev);
920 struct hdac_stream *s;
921 unsigned int active_streams = 0;
925 list_for_each_entry(s, &bus->stream_list, list) {
926 sd_offset = SOF_STREAM_SD_OFFSET(s);
927 val = snd_sof_dsp_read(sdev, HDA_DSP_HDA_BAR,
929 if (val & SOF_HDA_SD_CTL_DMA_START)
930 active_streams |= BIT(s->index);
933 return active_streams;
936 static int hda_dsp_s5_quirk(struct snd_sof_dev *sdev)
941 * Do not assume a certain timing between the prior
942 * suspend flow, and running of this quirk function.
943 * This is needed if the controller was just put
944 * to reset before calling this function.
946 usleep_range(500, 1000);
949 * Take controller out of reset to flush DMA
952 ret = hda_dsp_ctrl_link_reset(sdev, false);
956 usleep_range(500, 1000);
958 /* Restore state for shutdown, back to reset */
959 ret = hda_dsp_ctrl_link_reset(sdev, true);
966 int hda_dsp_shutdown_dma_flush(struct snd_sof_dev *sdev)
968 unsigned int active_streams;
971 /* check if DMA cleanup has been successful */
972 active_streams = hda_dsp_check_for_dma_streams(sdev);
974 sdev->system_suspend_target = SOF_SUSPEND_S3;
975 ret = snd_sof_suspend(sdev->dev);
977 if (active_streams) {
979 "There were active DSP streams (%#x) at shutdown, trying to recover\n",
981 ret2 = hda_dsp_s5_quirk(sdev);
983 dev_err(sdev->dev, "shutdown recovery failed (%d)\n", ret2);
989 int hda_dsp_shutdown(struct snd_sof_dev *sdev)
991 sdev->system_suspend_target = SOF_SUSPEND_S3;
992 return snd_sof_suspend(sdev->dev);
995 int hda_dsp_set_hw_params_upon_resume(struct snd_sof_dev *sdev)
999 /* make sure all DAI resources are freed */
1000 ret = hda_dsp_dais_suspend(sdev);
1002 dev_warn(sdev->dev, "%s: failure in hda_dsp_dais_suspend\n", __func__);
1007 void hda_dsp_d0i3_work(struct work_struct *work)
1009 struct sof_intel_hda_dev *hdev = container_of(work,
1010 struct sof_intel_hda_dev,
1012 struct hdac_bus *bus = &hdev->hbus.core;
1013 struct snd_sof_dev *sdev = dev_get_drvdata(bus->dev);
1014 struct sof_dsp_power_state target_state = {
1015 .state = SOF_DSP_PM_D0,
1016 .substate = SOF_HDA_DSP_PM_D0I3,
1020 /* DSP can enter D0I3 iff only D0I3-compatible streams are active */
1021 if (!snd_sof_dsp_only_d0i3_compatible_stream_active(sdev))
1022 /* remain in D0I0 */
1025 /* This can fail but error cannot be propagated */
1026 ret = snd_sof_dsp_set_power_state(sdev, &target_state);
1028 dev_err_ratelimited(sdev->dev,
1029 "error: failed to set DSP state %d substate %d\n",
1030 target_state.state, target_state.substate);
1033 int hda_dsp_core_get(struct snd_sof_dev *sdev, int core)
1035 const struct sof_ipc_pm_ops *pm_ops = sdev->ipc->ops->pm;
1039 ret = hda_dsp_enable_core(sdev, BIT(core));
1041 dev_err(sdev->dev, "failed to power up core %d with err: %d\n",
1046 /* No need to send IPC for primary core or if FW boot is not complete */
1047 if (sdev->fw_state != SOF_FW_BOOT_COMPLETE || core == SOF_DSP_PRIMARY_CORE)
1050 /* No need to continue the set_core_state ops is not available */
1051 if (!pm_ops->set_core_state)
1054 /* Now notify DSP for secondary cores */
1055 ret = pm_ops->set_core_state(sdev, core, true);
1057 dev_err(sdev->dev, "failed to enable secondary core '%d' failed with %d\n",
1065 /* power down core if it is host managed and return the original error if this fails too */
1066 ret1 = hda_dsp_core_reset_power_down(sdev, BIT(core));
1068 dev_err(sdev->dev, "failed to power down core: %d with err: %d\n", core, ret1);
1073 int hda_dsp_disable_interrupts(struct snd_sof_dev *sdev)
1075 hda_sdw_int_enable(sdev, false);
1076 hda_dsp_ipc_int_disable(sdev);