1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
6 // Copyright(c) 2018 Intel Corporation. All rights reserved.
8 // Authors: Liam Girdwood <liam.r.girdwood@linux.intel.com>
9 // Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
10 // Rander Wang <rander.wang@intel.com>
11 // Keyon Jie <yang.jie@linux.intel.com>
15 * Hardware interface for audio DSP on Cannonlake.
21 static const struct snd_sof_debugfs_map cnl_dsp_debugfs[] = {
22 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
23 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
24 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
27 static void cnl_ipc_host_done(struct snd_sof_dev *sdev);
28 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev);
30 static irqreturn_t cnl_ipc_irq_thread(int irq, void *context)
32 struct snd_sof_dev *sdev = context;
41 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
42 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
43 hipctdd = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDD);
44 hipci = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR);
46 /* reply message from DSP */
47 if (hipcida & CNL_DSP_REG_HIPCIDA_DONE) {
48 msg_ext = hipci & CNL_DSP_REG_HIPCIDR_MSG_MASK;
49 msg = hipcida & CNL_DSP_REG_HIPCIDA_MSG_MASK;
52 "ipc: firmware response, msg:0x%x, msg_ext:0x%x\n",
55 /* mask Done interrupt */
56 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
58 CNL_DSP_REG_HIPCCTL_DONE, 0);
60 spin_lock_irq(&sdev->ipc_lock);
62 /* handle immediate reply from DSP core */
63 hda_dsp_ipc_get_reply(sdev);
64 snd_sof_ipc_reply(sdev, msg);
66 if (sdev->code_loading) {
67 sdev->code_loading = 0;
68 wake_up(&sdev->waitq);
71 cnl_ipc_dsp_done(sdev);
73 spin_unlock_irq(&sdev->ipc_lock);
78 /* new message from DSP */
79 if (hipctdr & CNL_DSP_REG_HIPCTDR_BUSY) {
80 msg = hipctdr & CNL_DSP_REG_HIPCTDR_MSG_MASK;
81 msg_ext = hipctdd & CNL_DSP_REG_HIPCTDD_MSG_MASK;
84 "ipc: firmware initiated, msg:0x%x, msg_ext:0x%x\n",
87 /* handle messages from DSP */
88 if ((hipctdr & SOF_IPC_PANIC_MAGIC_MASK) ==
89 SOF_IPC_PANIC_MAGIC) {
90 snd_sof_dsp_panic(sdev, HDA_DSP_PANIC_OFFSET(msg_ext));
92 snd_sof_ipc_msgs_rx(sdev);
95 cnl_ipc_host_done(sdev);
102 * This interrupt is not shared so no need to return IRQ_NONE.
104 dev_err_ratelimited(sdev->dev,
105 "error: nothing to do in IRQ thread\n");
108 /* re-enable IPC interrupt */
109 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, HDA_DSP_REG_ADSPIC,
110 HDA_DSP_ADSPIC_IPC, HDA_DSP_ADSPIC_IPC);
115 static void cnl_ipc_host_done(struct snd_sof_dev *sdev)
118 * clear busy interrupt to tell dsp controller this
119 * interrupt has been accepted, not trigger it again
121 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
123 CNL_DSP_REG_HIPCTDR_BUSY,
124 CNL_DSP_REG_HIPCTDR_BUSY);
126 * set done bit to ack dsp the msg has been
127 * processed and send reply msg to dsp
129 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
131 CNL_DSP_REG_HIPCTDA_DONE,
132 CNL_DSP_REG_HIPCTDA_DONE);
135 static void cnl_ipc_dsp_done(struct snd_sof_dev *sdev)
138 * set DONE bit - tell DSP we have received the reply msg
139 * from DSP, and processed it, don't send more reply to host
141 snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
143 CNL_DSP_REG_HIPCIDA_DONE,
144 CNL_DSP_REG_HIPCIDA_DONE);
146 /* unmask Done interrupt */
147 snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR,
149 CNL_DSP_REG_HIPCCTL_DONE,
150 CNL_DSP_REG_HIPCCTL_DONE);
153 static int cnl_ipc_send_msg(struct snd_sof_dev *sdev,
154 struct snd_sof_ipc_msg *msg)
156 /* send the message */
157 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
159 snd_sof_dsp_write(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDR,
160 CNL_DSP_REG_HIPCIDR_BUSY);
165 static void cnl_ipc_dump(struct snd_sof_dev *sdev)
171 hda_ipc_irq_dump(sdev);
173 /* read IPC status */
174 hipcida = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCIDA);
175 hipcctl = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCCTL);
176 hipctdr = snd_sof_dsp_read(sdev, HDA_DSP_BAR, CNL_DSP_REG_HIPCTDR);
178 /* dump the IPC regs */
179 /* TODO: parse the raw msg */
181 "error: host status 0x%8.8x dsp status 0x%8.8x mask 0x%8.8x\n",
182 hipcida, hipctdr, hipcctl);
186 const struct snd_sof_dsp_ops sof_cnl_ops = {
187 /* probe and remove */
188 .probe = hda_dsp_probe,
189 .remove = hda_dsp_remove,
192 .write = sof_io_write,
194 .write64 = sof_io_write64,
195 .read64 = sof_io_read64,
198 .block_read = sof_block_read,
199 .block_write = sof_block_write,
202 .irq_handler = hda_dsp_ipc_irq_handler,
203 .irq_thread = cnl_ipc_irq_thread,
206 .send_msg = cnl_ipc_send_msg,
207 .fw_ready = hda_dsp_ipc_fw_ready,
209 .ipc_msg_data = hda_ipc_msg_data,
210 .ipc_pcm_params = hda_ipc_pcm_params,
213 .debug_map = cnl_dsp_debugfs,
214 .debug_map_count = ARRAY_SIZE(cnl_dsp_debugfs),
215 .dbg_dump = hda_dsp_dump,
216 .ipc_dump = cnl_ipc_dump,
218 /* stream callbacks */
219 .pcm_open = hda_dsp_pcm_open,
220 .pcm_close = hda_dsp_pcm_close,
221 .pcm_hw_params = hda_dsp_pcm_hw_params,
222 .pcm_hw_free = hda_dsp_stream_hw_free,
223 .pcm_trigger = hda_dsp_pcm_trigger,
224 .pcm_pointer = hda_dsp_pcm_pointer,
226 /* firmware loading */
227 .load_firmware = snd_sof_load_firmware_raw,
229 /* pre/post fw run */
230 .pre_fw_run = hda_dsp_pre_fw_run,
231 .post_fw_run = hda_dsp_post_fw_run,
233 /* dsp core power up/down */
234 .core_power_up = hda_dsp_enable_core,
235 .core_power_down = hda_dsp_core_reset_power_down,
238 .run = hda_dsp_cl_boot_firmware,
241 .trace_init = hda_dsp_trace_init,
242 .trace_release = hda_dsp_trace_release,
243 .trace_trigger = hda_dsp_trace_trigger,
247 .num_drv = SOF_SKL_NUM_DAIS,
250 .suspend = hda_dsp_suspend,
251 .resume = hda_dsp_resume,
252 .runtime_suspend = hda_dsp_runtime_suspend,
253 .runtime_resume = hda_dsp_runtime_resume,
254 .runtime_idle = hda_dsp_runtime_idle,
255 .set_hw_params_upon_resume = hda_dsp_set_hw_params_upon_resume,
257 EXPORT_SYMBOL(sof_cnl_ops);
259 const struct sof_intel_dsp_desc cnl_chip_info = {
263 .cores_mask = HDA_DSP_CORE_MASK(0) |
264 HDA_DSP_CORE_MASK(1) |
265 HDA_DSP_CORE_MASK(2) |
266 HDA_DSP_CORE_MASK(3),
267 .ipc_req = CNL_DSP_REG_HIPCIDR,
268 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
269 .ipc_ack = CNL_DSP_REG_HIPCIDA,
270 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
271 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
272 .rom_init_timeout = 300,
273 .ssp_count = CNL_SSP_COUNT,
274 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
276 EXPORT_SYMBOL(cnl_chip_info);
278 const struct sof_intel_dsp_desc icl_chip_info = {
282 .cores_mask = HDA_DSP_CORE_MASK(0) |
283 HDA_DSP_CORE_MASK(1) |
284 HDA_DSP_CORE_MASK(2) |
285 HDA_DSP_CORE_MASK(3),
286 .ipc_req = CNL_DSP_REG_HIPCIDR,
287 .ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
288 .ipc_ack = CNL_DSP_REG_HIPCIDA,
289 .ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
290 .ipc_ctl = CNL_DSP_REG_HIPCCTL,
291 .rom_init_timeout = 300,
292 .ssp_count = ICL_SSP_COUNT,
293 .ssp_base_offset = CNL_SSP_BASE_OFFSET,
295 EXPORT_SYMBOL(icl_chip_info);