2 * Renesas R-Car Gen1 SRU/SSI support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
14 void __iomem *base[RSND_BASE_MAX];
16 struct rsnd_gen_ops *ops;
18 struct regmap *regmap;
19 struct regmap_field *regs[RSND_REG_MAX];
22 #define rsnd_priv_to_gen(p) ((struct rsnd_gen *)(p)->gen)
24 #define RSND_REG_SET(gen, id, reg_id, offset, _id_offset, _id_size) \
26 .reg = (unsigned int)gen->base[reg_id] + offset, \
29 .id_size = _id_size, \
30 .id_offset = _id_offset, \
36 static int rsnd_regmap_write32(void *context, const void *_data, size_t count)
38 struct rsnd_priv *priv = context;
39 struct device *dev = rsnd_priv_to_dev(priv);
40 u32 *data = (u32 *)_data;
42 void __iomem *reg = (void *)data[0];
46 dev_dbg(dev, "w %p : %08x\n", reg, val);
51 static int rsnd_regmap_read32(void *context,
52 const void *_data, size_t reg_size,
53 void *_val, size_t val_size)
55 struct rsnd_priv *priv = context;
56 struct device *dev = rsnd_priv_to_dev(priv);
57 u32 *data = (u32 *)_data;
58 u32 *val = (u32 *)_val;
59 void __iomem *reg = (void *)data[0];
63 dev_dbg(dev, "r %p : %08x\n", reg, *val);
68 static struct regmap_bus rsnd_regmap_bus = {
69 .write = rsnd_regmap_write32,
70 .read = rsnd_regmap_read32,
71 .reg_format_endian_default = REGMAP_ENDIAN_NATIVE,
72 .val_format_endian_default = REGMAP_ENDIAN_NATIVE,
75 static int rsnd_is_accessible_reg(struct rsnd_priv *priv,
76 struct rsnd_gen *gen, enum rsnd_reg reg)
78 if (!gen->regs[reg]) {
79 struct device *dev = rsnd_priv_to_dev(priv);
81 dev_err(dev, "unsupported register access %x\n", reg);
88 u32 rsnd_read(struct rsnd_priv *priv,
89 struct rsnd_mod *mod, enum rsnd_reg reg)
91 struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
94 if (!rsnd_is_accessible_reg(priv, gen, reg))
97 regmap_fields_read(gen->regs[reg], rsnd_mod_id(mod), &val);
102 void rsnd_write(struct rsnd_priv *priv,
103 struct rsnd_mod *mod,
104 enum rsnd_reg reg, u32 data)
106 struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
108 if (!rsnd_is_accessible_reg(priv, gen, reg))
111 regmap_fields_write(gen->regs[reg], rsnd_mod_id(mod), data);
114 void rsnd_bset(struct rsnd_priv *priv, struct rsnd_mod *mod,
115 enum rsnd_reg reg, u32 mask, u32 data)
117 struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
119 if (!rsnd_is_accessible_reg(priv, gen, reg))
122 regmap_fields_update_bits(gen->regs[reg], rsnd_mod_id(mod),
126 static int rsnd_gen_regmap_init(struct rsnd_priv *priv,
127 struct rsnd_gen *gen,
128 struct reg_field *regf)
131 struct device *dev = rsnd_priv_to_dev(priv);
132 struct regmap_config regc;
134 memset(®c, 0, sizeof(regc));
138 gen->regmap = devm_regmap_init(dev, &rsnd_regmap_bus, priv, ®c);
139 if (IS_ERR(gen->regmap)) {
140 dev_err(dev, "regmap error %ld\n", PTR_ERR(gen->regmap));
141 return PTR_ERR(gen->regmap);
144 for (i = 0; i < RSND_REG_MAX; i++) {
149 gen->regs[i] = devm_regmap_field_alloc(dev, gen->regmap, regf[i]);
150 if (IS_ERR(gen->regs[i]))
151 return PTR_ERR(gen->regs[i]);
162 /* single address mapping */
163 #define RSND_GEN2_S_REG(gen, reg, id, offset) \
164 RSND_REG_SET(gen, RSND_REG_##id, RSND_GEN2_##reg, offset, 0, 10)
166 /* multi address mapping */
167 #define RSND_GEN2_M_REG(gen, reg, id, offset, _id_offset) \
168 RSND_REG_SET(gen, RSND_REG_##id, RSND_GEN2_##reg, offset, _id_offset, 10)
170 static int rsnd_gen2_regmap_init(struct rsnd_priv *priv, struct rsnd_gen *gen)
172 struct reg_field regf[RSND_REG_MAX] = {
173 RSND_GEN2_S_REG(gen, SSIU, SSI_MODE0, 0x800),
174 RSND_GEN2_S_REG(gen, SSIU, SSI_MODE1, 0x804),
175 /* FIXME: it needs SSI_MODE2/3 in the future */
176 RSND_GEN2_M_REG(gen, SSIU, SSI_BUSIF_MODE, 0x0, 0x80),
177 RSND_GEN2_M_REG(gen, SSIU, SSI_BUSIF_ADINR,0x4, 0x80),
178 RSND_GEN2_M_REG(gen, SSIU, SSI_CTRL, 0x10, 0x80),
179 RSND_GEN2_M_REG(gen, SSIU, INT_ENABLE, 0x18, 0x80),
181 RSND_GEN2_M_REG(gen, SCU, SRC_BUSIF_MODE, 0x0, 0x20),
182 RSND_GEN2_M_REG(gen, SCU, SRC_ROUTE_MODE0,0xc, 0x20),
183 RSND_GEN2_M_REG(gen, SCU, SRC_CTRL, 0x10, 0x20),
184 RSND_GEN2_M_REG(gen, SCU, CMD_ROUTE_SLCT, 0x18c, 0x20),
185 RSND_GEN2_M_REG(gen, SCU, CMD_CTRL, 0x190, 0x20),
186 RSND_GEN2_M_REG(gen, SCU, SRC_SWRSR, 0x200, 0x40),
187 RSND_GEN2_M_REG(gen, SCU, SRC_SRCIR, 0x204, 0x40),
188 RSND_GEN2_M_REG(gen, SCU, SRC_ADINR, 0x214, 0x40),
189 RSND_GEN2_M_REG(gen, SCU, SRC_IFSCR, 0x21c, 0x40),
190 RSND_GEN2_M_REG(gen, SCU, SRC_IFSVR, 0x220, 0x40),
191 RSND_GEN2_M_REG(gen, SCU, SRC_SRCCR, 0x224, 0x40),
192 RSND_GEN2_M_REG(gen, SCU, SRC_BSDSR, 0x22c, 0x40),
193 RSND_GEN2_M_REG(gen, SCU, SRC_BSISR, 0x238, 0x40),
194 RSND_GEN2_M_REG(gen, SCU, DVC_SWRSR, 0xe00, 0x100),
195 RSND_GEN2_M_REG(gen, SCU, DVC_DVUIR, 0xe04, 0x100),
196 RSND_GEN2_M_REG(gen, SCU, DVC_ADINR, 0xe08, 0x100),
197 RSND_GEN2_M_REG(gen, SCU, DVC_DVUCR, 0xe10, 0x100),
198 RSND_GEN2_M_REG(gen, SCU, DVC_ZCMCR, 0xe14, 0x100),
199 RSND_GEN2_M_REG(gen, SCU, DVC_VOL0R, 0xe28, 0x100),
200 RSND_GEN2_M_REG(gen, SCU, DVC_VOL1R, 0xe2c, 0x100),
201 RSND_GEN2_M_REG(gen, SCU, DVC_DVUER, 0xe48, 0x100),
203 RSND_GEN2_S_REG(gen, ADG, BRRA, 0x00),
204 RSND_GEN2_S_REG(gen, ADG, BRRB, 0x04),
205 RSND_GEN2_S_REG(gen, ADG, SSICKR, 0x08),
206 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL0, 0x0c),
207 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL1, 0x10),
208 RSND_GEN2_S_REG(gen, ADG, AUDIO_CLK_SEL2, 0x14),
209 RSND_GEN2_S_REG(gen, ADG, DIV_EN, 0x30),
210 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL0, 0x34),
211 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL1, 0x38),
212 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL2, 0x3c),
213 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL3, 0x40),
214 RSND_GEN2_S_REG(gen, ADG, SRCIN_TIMSEL4, 0x44),
215 RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL0, 0x48),
216 RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL1, 0x4c),
217 RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL2, 0x50),
218 RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL3, 0x54),
219 RSND_GEN2_S_REG(gen, ADG, SRCOUT_TIMSEL4, 0x58),
220 RSND_GEN2_S_REG(gen, ADG, CMDOUT_TIMSEL, 0x5c),
222 RSND_GEN2_M_REG(gen, SSI, SSICR, 0x00, 0x40),
223 RSND_GEN2_M_REG(gen, SSI, SSISR, 0x04, 0x40),
224 RSND_GEN2_M_REG(gen, SSI, SSITDR, 0x08, 0x40),
225 RSND_GEN2_M_REG(gen, SSI, SSIRDR, 0x0c, 0x40),
226 RSND_GEN2_M_REG(gen, SSI, SSIWSR, 0x20, 0x40),
229 return rsnd_gen_regmap_init(priv, gen, regf);
232 static int rsnd_gen2_probe(struct platform_device *pdev,
233 struct rsnd_priv *priv)
235 struct device *dev = rsnd_priv_to_dev(priv);
236 struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
237 struct resource *scu_res;
238 struct resource *adg_res;
239 struct resource *ssiu_res;
240 struct resource *ssi_res;
246 scu_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN2_SCU);
247 adg_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN2_ADG);
248 ssiu_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN2_SSIU);
249 ssi_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN2_SSI);
251 gen->base[RSND_GEN2_SCU] = devm_ioremap_resource(dev, scu_res);
252 gen->base[RSND_GEN2_ADG] = devm_ioremap_resource(dev, adg_res);
253 gen->base[RSND_GEN2_SSIU] = devm_ioremap_resource(dev, ssiu_res);
254 gen->base[RSND_GEN2_SSI] = devm_ioremap_resource(dev, ssi_res);
255 if (IS_ERR(gen->base[RSND_GEN2_SCU]) ||
256 IS_ERR(gen->base[RSND_GEN2_ADG]) ||
257 IS_ERR(gen->base[RSND_GEN2_SSIU]) ||
258 IS_ERR(gen->base[RSND_GEN2_SSI]))
261 ret = rsnd_gen2_regmap_init(priv, gen);
265 dev_dbg(dev, "Gen2 device probed\n");
266 dev_dbg(dev, "SCU : %08x => %p\n", scu_res->start,
267 gen->base[RSND_GEN2_SCU]);
268 dev_dbg(dev, "ADG : %08x => %p\n", adg_res->start,
269 gen->base[RSND_GEN2_ADG]);
270 dev_dbg(dev, "SSIU : %08x => %p\n", ssiu_res->start,
271 gen->base[RSND_GEN2_SSIU]);
272 dev_dbg(dev, "SSI : %08x => %p\n", ssi_res->start,
273 gen->base[RSND_GEN2_SSI]);
282 /* single address mapping */
283 #define RSND_GEN1_S_REG(gen, reg, id, offset) \
284 RSND_REG_SET(gen, RSND_REG_##id, RSND_GEN1_##reg, offset, 0, 9)
286 /* multi address mapping */
287 #define RSND_GEN1_M_REG(gen, reg, id, offset, _id_offset) \
288 RSND_REG_SET(gen, RSND_REG_##id, RSND_GEN1_##reg, offset, _id_offset, 9)
290 static int rsnd_gen1_regmap_init(struct rsnd_priv *priv, struct rsnd_gen *gen)
292 struct reg_field regf[RSND_REG_MAX] = {
293 RSND_GEN1_S_REG(gen, SRU, SRC_ROUTE_SEL, 0x00),
294 RSND_GEN1_S_REG(gen, SRU, SRC_TMG_SEL0, 0x08),
295 RSND_GEN1_S_REG(gen, SRU, SRC_TMG_SEL1, 0x0c),
296 RSND_GEN1_S_REG(gen, SRU, SRC_TMG_SEL2, 0x10),
297 RSND_GEN1_S_REG(gen, SRU, SRC_ROUTE_CTRL, 0xc0),
298 RSND_GEN1_S_REG(gen, SRU, SSI_MODE0, 0xD0),
299 RSND_GEN1_S_REG(gen, SRU, SSI_MODE1, 0xD4),
300 RSND_GEN1_M_REG(gen, SRU, SRC_BUSIF_MODE, 0x20, 0x4),
301 RSND_GEN1_M_REG(gen, SRU, SRC_ROUTE_MODE0,0x50, 0x8),
302 RSND_GEN1_M_REG(gen, SRU, SRC_SWRSR, 0x200, 0x40),
303 RSND_GEN1_M_REG(gen, SRU, SRC_SRCIR, 0x204, 0x40),
304 RSND_GEN1_M_REG(gen, SRU, SRC_ADINR, 0x214, 0x40),
305 RSND_GEN1_M_REG(gen, SRU, SRC_IFSCR, 0x21c, 0x40),
306 RSND_GEN1_M_REG(gen, SRU, SRC_IFSVR, 0x220, 0x40),
307 RSND_GEN1_M_REG(gen, SRU, SRC_SRCCR, 0x224, 0x40),
308 RSND_GEN1_M_REG(gen, SRU, SRC_MNFSR, 0x228, 0x40),
310 RSND_GEN1_S_REG(gen, ADG, BRRA, 0x00),
311 RSND_GEN1_S_REG(gen, ADG, BRRB, 0x04),
312 RSND_GEN1_S_REG(gen, ADG, SSICKR, 0x08),
313 RSND_GEN1_S_REG(gen, ADG, AUDIO_CLK_SEL0, 0x0c),
314 RSND_GEN1_S_REG(gen, ADG, AUDIO_CLK_SEL1, 0x10),
315 RSND_GEN1_S_REG(gen, ADG, AUDIO_CLK_SEL3, 0x18),
316 RSND_GEN1_S_REG(gen, ADG, AUDIO_CLK_SEL4, 0x1c),
317 RSND_GEN1_S_REG(gen, ADG, AUDIO_CLK_SEL5, 0x20),
319 RSND_GEN1_M_REG(gen, SSI, SSICR, 0x00, 0x40),
320 RSND_GEN1_M_REG(gen, SSI, SSISR, 0x04, 0x40),
321 RSND_GEN1_M_REG(gen, SSI, SSITDR, 0x08, 0x40),
322 RSND_GEN1_M_REG(gen, SSI, SSIRDR, 0x0c, 0x40),
323 RSND_GEN1_M_REG(gen, SSI, SSIWSR, 0x20, 0x40),
326 return rsnd_gen_regmap_init(priv, gen, regf);
329 static int rsnd_gen1_probe(struct platform_device *pdev,
330 struct rsnd_priv *priv)
332 struct device *dev = rsnd_priv_to_dev(priv);
333 struct rsnd_gen *gen = rsnd_priv_to_gen(priv);
334 struct resource *sru_res;
335 struct resource *adg_res;
336 struct resource *ssi_res;
342 sru_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN1_SRU);
343 adg_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN1_ADG);
344 ssi_res = platform_get_resource(pdev, IORESOURCE_MEM, RSND_GEN1_SSI);
346 gen->base[RSND_GEN1_SRU] = devm_ioremap_resource(dev, sru_res);
347 gen->base[RSND_GEN1_ADG] = devm_ioremap_resource(dev, adg_res);
348 gen->base[RSND_GEN1_SSI] = devm_ioremap_resource(dev, ssi_res);
349 if (IS_ERR(gen->base[RSND_GEN1_SRU]) ||
350 IS_ERR(gen->base[RSND_GEN1_ADG]) ||
351 IS_ERR(gen->base[RSND_GEN1_SSI]))
354 ret = rsnd_gen1_regmap_init(priv, gen);
358 dev_dbg(dev, "Gen1 device probed\n");
359 dev_dbg(dev, "SRU : %08x => %p\n", sru_res->start,
360 gen->base[RSND_GEN1_SRU]);
361 dev_dbg(dev, "ADG : %08x => %p\n", adg_res->start,
362 gen->base[RSND_GEN1_ADG]);
363 dev_dbg(dev, "SSI : %08x => %p\n", ssi_res->start,
364 gen->base[RSND_GEN1_SSI]);
373 static void rsnd_of_parse_gen(struct platform_device *pdev,
374 const struct rsnd_of_data *of_data,
375 struct rsnd_priv *priv)
377 struct rcar_snd_info *info = priv->info;
382 info->flags = of_data->flags;
385 int rsnd_gen_probe(struct platform_device *pdev,
386 const struct rsnd_of_data *of_data,
387 struct rsnd_priv *priv)
389 struct device *dev = rsnd_priv_to_dev(priv);
390 struct rsnd_gen *gen;
393 rsnd_of_parse_gen(pdev, of_data, priv);
395 gen = devm_kzalloc(dev, sizeof(*gen), GFP_KERNEL);
397 dev_err(dev, "GEN allocate failed\n");
404 if (rsnd_is_gen1(priv))
405 ret = rsnd_gen1_probe(pdev, priv);
406 else if (rsnd_is_gen2(priv))
407 ret = rsnd_gen2_probe(pdev, priv);
410 dev_err(dev, "unknown generation R-Car sound device\n");