2 * pxa-ssp.c -- ALSA Soc Audio Layer
4 * Copyright 2005,2008 Wolfson Microelectronics PLC.
5 * Author: Liam Girdwood
6 * Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 * o Test network mode for > 16bit sample size
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/slab.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
23 #include <linux/pxa2xx_ssp.h>
25 #include <linux/dmaengine.h>
29 #include <sound/core.h>
30 #include <sound/pcm.h>
31 #include <sound/initval.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc.h>
34 #include <sound/pxa2xx-lib.h>
35 #include <sound/dmaengine_pcm.h>
40 * SSP audio private data
43 struct ssp_device *ssp;
45 unsigned long ssp_clk;
48 unsigned int configured_dai_fmt;
57 static void dump_registers(struct ssp_device *ssp)
59 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n",
60 pxa_ssp_read_reg(ssp, SSCR0), pxa_ssp_read_reg(ssp, SSCR1),
61 pxa_ssp_read_reg(ssp, SSTO));
63 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n",
64 pxa_ssp_read_reg(ssp, SSPSP), pxa_ssp_read_reg(ssp, SSSR),
65 pxa_ssp_read_reg(ssp, SSACD));
68 static void pxa_ssp_enable(struct ssp_device *ssp)
72 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) | SSCR0_SSE;
73 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
76 static void pxa_ssp_disable(struct ssp_device *ssp)
80 sscr0 = __raw_readl(ssp->mmio_base + SSCR0) & ~SSCR0_SSE;
81 __raw_writel(sscr0, ssp->mmio_base + SSCR0);
84 static void pxa_ssp_set_dma_params(struct ssp_device *ssp, int width4,
85 int out, struct snd_dmaengine_dai_dma_data *dma)
87 dma->addr_width = width4 ? DMA_SLAVE_BUSWIDTH_4_BYTES :
88 DMA_SLAVE_BUSWIDTH_2_BYTES;
90 dma->addr = ssp->phys_base + SSDR;
93 static int pxa_ssp_startup(struct snd_pcm_substream *substream,
94 struct snd_soc_dai *cpu_dai)
96 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
97 struct ssp_device *ssp = priv->ssp;
98 struct snd_dmaengine_dai_dma_data *dma;
101 if (!cpu_dai->active) {
102 clk_prepare_enable(ssp->clk);
103 pxa_ssp_disable(ssp);
107 clk_prepare_enable(priv->extclk);
109 dma = kzalloc(sizeof(struct snd_dmaengine_dai_dma_data), GFP_KERNEL);
112 dma->chan_name = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
115 snd_soc_dai_set_dma_data(cpu_dai, substream, dma);
120 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream,
121 struct snd_soc_dai *cpu_dai)
123 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
124 struct ssp_device *ssp = priv->ssp;
126 if (!cpu_dai->active) {
127 pxa_ssp_disable(ssp);
128 clk_disable_unprepare(ssp->clk);
132 clk_disable_unprepare(priv->extclk);
134 kfree(snd_soc_dai_get_dma_data(cpu_dai, substream));
135 snd_soc_dai_set_dma_data(cpu_dai, substream, NULL);
140 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai)
142 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
143 struct ssp_device *ssp = priv->ssp;
145 if (!cpu_dai->active)
146 clk_prepare_enable(ssp->clk);
148 priv->cr0 = __raw_readl(ssp->mmio_base + SSCR0);
149 priv->cr1 = __raw_readl(ssp->mmio_base + SSCR1);
150 priv->to = __raw_readl(ssp->mmio_base + SSTO);
151 priv->psp = __raw_readl(ssp->mmio_base + SSPSP);
153 pxa_ssp_disable(ssp);
154 clk_disable_unprepare(ssp->clk);
158 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai)
160 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
161 struct ssp_device *ssp = priv->ssp;
162 uint32_t sssr = SSSR_ROR | SSSR_TUR | SSSR_BCE;
164 clk_prepare_enable(ssp->clk);
166 __raw_writel(sssr, ssp->mmio_base + SSSR);
167 __raw_writel(priv->cr0 & ~SSCR0_SSE, ssp->mmio_base + SSCR0);
168 __raw_writel(priv->cr1, ssp->mmio_base + SSCR1);
169 __raw_writel(priv->to, ssp->mmio_base + SSTO);
170 __raw_writel(priv->psp, ssp->mmio_base + SSPSP);
175 clk_disable_unprepare(ssp->clk);
181 #define pxa_ssp_suspend NULL
182 #define pxa_ssp_resume NULL
186 * ssp_set_clkdiv - set SSP clock divider
187 * @div: serial clock rate divider
189 static void pxa_ssp_set_scr(struct ssp_device *ssp, u32 div)
191 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
193 if (ssp->type == PXA25x_SSP) {
194 sscr0 &= ~0x0000ff00;
195 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */
197 sscr0 &= ~0x000fff00;
198 sscr0 |= (div - 1) << 8; /* 1..4096 */
200 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
204 * Set the SSP ports SYSCLK.
206 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
207 int clk_id, unsigned int freq, int dir)
209 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
210 struct ssp_device *ssp = priv->ssp;
212 u32 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
213 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS);
219 * For DT based boards, if an extclk is given, use it
220 * here and configure PXA_SSP_CLK_EXT.
223 ret = clk_set_rate(priv->extclk, freq);
227 clk_id = PXA_SSP_CLK_EXT;
230 dev_dbg(&ssp->pdev->dev,
231 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n",
232 cpu_dai->id, clk_id, freq);
235 case PXA_SSP_CLK_NET_PLL:
238 case PXA_SSP_CLK_PLL:
239 /* Internal PLL is fixed */
240 if (ssp->type == PXA25x_SSP)
241 priv->sysclk = 1843200;
243 priv->sysclk = 13000000;
245 case PXA_SSP_CLK_EXT:
249 case PXA_SSP_CLK_NET:
251 sscr0 |= SSCR0_NCS | SSCR0_MOD;
253 case PXA_SSP_CLK_AUDIO:
255 pxa_ssp_set_scr(ssp, 1);
262 /* The SSP clock must be disabled when changing SSP clock mode
263 * on PXA2xx. On PXA3xx it must be enabled when doing so. */
264 if (ssp->type != PXA3xx_SSP)
265 clk_disable_unprepare(ssp->clk);
266 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
267 if (ssp->type != PXA3xx_SSP)
268 clk_prepare_enable(ssp->clk);
274 * Configure the PLL frequency pxa27x and (afaik - pxa320 only)
276 static int pxa_ssp_set_pll(struct ssp_priv *priv, unsigned int freq)
278 struct ssp_device *ssp = priv->ssp;
279 u32 ssacd = pxa_ssp_read_reg(ssp, SSACD) & ~0x70;
281 if (ssp->type == PXA3xx_SSP)
282 pxa_ssp_write_reg(ssp, SSACDD, 0);
307 /* PXA3xx has a clock ditherer which can be used to generate
308 * a wider range of frequencies - calculate a value for it.
310 if (ssp->type == PXA3xx_SSP) {
318 val = (val << 16) | 64;
319 pxa_ssp_write_reg(ssp, SSACDD, val);
323 dev_dbg(&ssp->pdev->dev,
324 "Using SSACDD %x to supply %uHz\n",
332 pxa_ssp_write_reg(ssp, SSACD, ssacd);
338 * Set the active slots in TDM/Network mode
340 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
341 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
343 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
344 struct ssp_device *ssp = priv->ssp;
347 sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
348 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS);
352 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16);
354 sscr0 |= SSCR0_DataSize(slot_width);
357 /* enable network mode */
360 /* set number of active slots */
361 sscr0 |= SSCR0_SlotsPerFrm(slots);
363 /* set active slot mask */
364 pxa_ssp_write_reg(ssp, SSTSA, tx_mask);
365 pxa_ssp_write_reg(ssp, SSRSA, rx_mask);
367 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
373 * Tristate the SSP DAI lines
375 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai,
378 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
379 struct ssp_device *ssp = priv->ssp;
382 sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
387 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
392 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
395 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
397 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
398 case SND_SOC_DAIFMT_CBM_CFM:
399 case SND_SOC_DAIFMT_CBM_CFS:
400 case SND_SOC_DAIFMT_CBS_CFS:
406 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
407 case SND_SOC_DAIFMT_NB_NF:
408 case SND_SOC_DAIFMT_NB_IF:
409 case SND_SOC_DAIFMT_IB_IF:
410 case SND_SOC_DAIFMT_IB_NF:
416 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
417 case SND_SOC_DAIFMT_I2S:
418 case SND_SOC_DAIFMT_DSP_A:
419 case SND_SOC_DAIFMT_DSP_B:
426 /* Settings will be applied in hw_params() */
433 * Set up the SSP DAI format.
434 * The SSP Port must be inactive before calling this function as the
435 * physical interface format is changed.
437 static int pxa_ssp_configure_dai_fmt(struct ssp_priv *priv)
439 struct ssp_device *ssp = priv->ssp;
440 u32 sscr0, sscr1, sspsp, scfr;
442 /* check if we need to change anything at all */
443 if (priv->configured_dai_fmt == priv->dai_fmt)
446 /* reset port settings */
447 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) &
448 ~(SSCR0_PSP | SSCR0_MOD);
449 sscr1 = pxa_ssp_read_reg(ssp, SSCR1) &
450 ~(SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR |
451 SSCR1_RWOT | SSCR1_TRAIL | SSCR1_TFT | SSCR1_RFT);
452 sspsp = pxa_ssp_read_reg(ssp, SSPSP) &
453 ~(SSPSP_SFRMP | SSPSP_SCMODE(3));
455 sscr1 |= SSCR1_RxTresh(8) | SSCR1_TxTresh(7);
457 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
458 case SND_SOC_DAIFMT_CBM_CFM:
459 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR | SSCR1_SCFR;
461 case SND_SOC_DAIFMT_CBM_CFS:
462 sscr1 |= SSCR1_SCLKDIR | SSCR1_SCFR;
464 case SND_SOC_DAIFMT_CBS_CFS:
470 switch (priv->dai_fmt & SND_SOC_DAIFMT_INV_MASK) {
471 case SND_SOC_DAIFMT_NB_NF:
472 sspsp |= SSPSP_SFRMP;
474 case SND_SOC_DAIFMT_NB_IF:
476 case SND_SOC_DAIFMT_IB_IF:
477 sspsp |= SSPSP_SCMODE(2);
479 case SND_SOC_DAIFMT_IB_NF:
480 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP;
486 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
487 case SND_SOC_DAIFMT_I2S:
489 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL;
490 /* See hw_params() */
493 case SND_SOC_DAIFMT_DSP_A:
496 case SND_SOC_DAIFMT_DSP_B:
497 sscr0 |= SSCR0_MOD | SSCR0_PSP;
498 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT;
505 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
506 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
507 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
509 switch (priv->dai_fmt & SND_SOC_DAIFMT_MASTER_MASK) {
510 case SND_SOC_DAIFMT_CBM_CFM:
511 case SND_SOC_DAIFMT_CBM_CFS:
512 scfr = pxa_ssp_read_reg(ssp, SSCR1) | SSCR1_SCFR;
513 pxa_ssp_write_reg(ssp, SSCR1, scfr);
515 while (pxa_ssp_read_reg(ssp, SSSR) & SSSR_BSY)
522 /* Since we are configuring the timings for the format by hand
523 * we have to defer some things until hw_params() where we
524 * know parameters like the sample size.
526 priv->configured_dai_fmt = priv->dai_fmt;
531 struct pxa_ssp_clock_mode {
538 static const struct pxa_ssp_clock_mode pxa_ssp_clock_modes[] = {
539 { .rate = 8000, .pll = 32842000, .acds = SSACD_ACDS_32, .scdb = SSACD_SCDB_4X },
540 { .rate = 11025, .pll = 5622000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_4X },
541 { .rate = 16000, .pll = 32842000, .acds = SSACD_ACDS_16, .scdb = SSACD_SCDB_4X },
542 { .rate = 22050, .pll = 5622000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
543 { .rate = 44100, .pll = 11345000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
544 { .rate = 48000, .pll = 12235000, .acds = SSACD_ACDS_2, .scdb = SSACD_SCDB_4X },
545 { .rate = 96000, .pll = 12235000, .acds = SSACD_ACDS_4, .scdb = SSACD_SCDB_1X },
550 * Set the SSP audio DMA parameters and sample size.
551 * Can be called multiple times by oss emulation.
553 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream,
554 struct snd_pcm_hw_params *params,
555 struct snd_soc_dai *cpu_dai)
557 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
558 struct ssp_device *ssp = priv->ssp;
559 int chn = params_channels(params);
561 int width = snd_pcm_format_physical_width(params_format(params));
562 int ttsa = pxa_ssp_read_reg(ssp, SSTSA) & 0xf;
563 struct snd_dmaengine_dai_dma_data *dma_data;
564 int rate = params_rate(params);
565 int bclk = rate * chn * (width / 8);
568 dma_data = snd_soc_dai_get_dma_data(cpu_dai, substream);
570 /* Network mode with one active slot (ttsa == 1) can be used
571 * to force 16-bit frame width on the wire (for S16_LE), even
572 * with two channels. Use 16-bit DMA transfers for this case.
574 pxa_ssp_set_dma_params(ssp,
575 ((chn == 2) && (ttsa != 1)) || (width == 32),
576 substream->stream == SNDRV_PCM_STREAM_PLAYBACK, dma_data);
578 /* we can only change the settings if the port is not in use */
579 if (pxa_ssp_read_reg(ssp, SSCR0) & SSCR0_SSE)
582 ret = pxa_ssp_configure_dai_fmt(priv);
586 /* clear selected SSP bits */
587 sscr0 = pxa_ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS);
590 switch (params_format(params)) {
591 case SNDRV_PCM_FORMAT_S16_LE:
592 if (ssp->type == PXA3xx_SSP)
593 sscr0 |= SSCR0_FPCKE;
594 sscr0 |= SSCR0_DataSize(16);
596 case SNDRV_PCM_FORMAT_S24_LE:
597 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8));
599 case SNDRV_PCM_FORMAT_S32_LE:
600 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16));
603 pxa_ssp_write_reg(ssp, SSCR0, sscr0);
605 if (sscr0 & SSCR0_ACS) {
606 ret = pxa_ssp_set_pll(priv, bclk);
609 * If we were able to generate the bclk directly,
610 * all is fine. Otherwise, look up the closest rate
611 * from the table and also set the dividers.
615 const struct pxa_ssp_clock_mode *m;
618 for (m = pxa_ssp_clock_modes; m->rate; m++) {
628 /* The values in the table are for 16 bits */
632 ret = pxa_ssp_set_pll(priv, bclk);
636 ssacd = pxa_ssp_read_reg(ssp, SSACD);
637 ssacd &= ~(SSACD_ACDS(7) | SSACD_SCDB_1X);
638 ssacd |= SSACD_ACDS(m->acds);
640 pxa_ssp_write_reg(ssp, SSACD, ssacd);
642 } else if (sscr0 & SSCR0_ECS) {
644 * For setups with external clocking, the PLL and its diviers
645 * are not active. Instead, the SCR bits in SSCR0 can be used
646 * to divide the clock.
648 pxa_ssp_set_scr(ssp, bclk / rate);
651 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
652 case SND_SOC_DAIFMT_I2S:
653 sspsp = pxa_ssp_read_reg(ssp, SSPSP);
655 if (((priv->sysclk / bclk) == 64) && (width == 16)) {
656 /* This is a special case where the bitclk is 64fs
657 * and we're not dealing with 2*32 bits of audio
660 * The SSP values used for that are all found out by
661 * trying and failing a lot; some of the registers
662 * needed for that mode are only available on PXA3xx.
664 if (ssp->type != PXA3xx_SSP)
667 sspsp |= SSPSP_SFRMWDTH(width * 2);
668 sspsp |= SSPSP_SFRMDLY(width * 4);
669 sspsp |= SSPSP_EDMYSTOP(3);
670 sspsp |= SSPSP_DMYSTOP(3);
671 sspsp |= SSPSP_DMYSTRT(1);
673 /* The frame width is the width the LRCLK is
674 * asserted for; the delay is expressed in
675 * half cycle units. We need the extra cycle
676 * because the data starts clocking out one BCLK
677 * after LRCLK changes polarity.
679 sspsp |= SSPSP_SFRMWDTH(width + 1);
680 sspsp |= SSPSP_SFRMDLY((width + 1) * 2);
681 sspsp |= SSPSP_DMYSTRT(1);
684 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
690 /* When we use a network mode, we always require TDM slots
691 * - complain loudly and fail if they've not been set up yet.
693 if ((sscr0 & SSCR0_MOD) && !ttsa) {
694 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n");
703 static void pxa_ssp_set_running_bit(struct snd_pcm_substream *substream,
704 struct ssp_device *ssp, int value)
706 uint32_t sscr0 = pxa_ssp_read_reg(ssp, SSCR0);
707 uint32_t sscr1 = pxa_ssp_read_reg(ssp, SSCR1);
708 uint32_t sspsp = pxa_ssp_read_reg(ssp, SSPSP);
709 uint32_t sssr = pxa_ssp_read_reg(ssp, SSSR);
711 if (value && (sscr0 & SSCR0_SSE))
712 pxa_ssp_write_reg(ssp, SSCR0, sscr0 & ~SSCR0_SSE);
714 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
718 sscr1 &= ~SSCR1_TSRE;
723 sscr1 &= ~SSCR1_RSRE;
726 pxa_ssp_write_reg(ssp, SSCR1, sscr1);
729 pxa_ssp_write_reg(ssp, SSSR, sssr);
730 pxa_ssp_write_reg(ssp, SSPSP, sspsp);
731 pxa_ssp_write_reg(ssp, SSCR0, sscr0 | SSCR0_SSE);
735 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd,
736 struct snd_soc_dai *cpu_dai)
739 struct ssp_priv *priv = snd_soc_dai_get_drvdata(cpu_dai);
740 struct ssp_device *ssp = priv->ssp;
744 case SNDRV_PCM_TRIGGER_RESUME:
747 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
748 pxa_ssp_set_running_bit(substream, ssp, 1);
749 val = pxa_ssp_read_reg(ssp, SSSR);
750 pxa_ssp_write_reg(ssp, SSSR, val);
752 case SNDRV_PCM_TRIGGER_START:
753 pxa_ssp_set_running_bit(substream, ssp, 1);
755 case SNDRV_PCM_TRIGGER_STOP:
756 pxa_ssp_set_running_bit(substream, ssp, 0);
758 case SNDRV_PCM_TRIGGER_SUSPEND:
759 pxa_ssp_disable(ssp);
761 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
762 pxa_ssp_set_running_bit(substream, ssp, 0);
774 static int pxa_ssp_probe(struct snd_soc_dai *dai)
776 struct device *dev = dai->dev;
777 struct ssp_priv *priv;
780 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL);
785 struct device_node *ssp_handle;
787 ssp_handle = of_parse_phandle(dev->of_node, "port", 0);
789 dev_err(dev, "unable to get 'port' phandle\n");
794 priv->ssp = pxa_ssp_request_of(ssp_handle, "SoC audio");
795 if (priv->ssp == NULL) {
800 priv->extclk = devm_clk_get(dev, "extclk");
801 if (IS_ERR(priv->extclk)) {
802 ret = PTR_ERR(priv->extclk);
803 if (ret == -EPROBE_DEFER)
809 priv->ssp = pxa_ssp_request(dai->id + 1, "SoC audio");
810 if (priv->ssp == NULL) {
816 priv->dai_fmt = (unsigned int) -1;
817 snd_soc_dai_set_drvdata(dai, priv);
826 static int pxa_ssp_remove(struct snd_soc_dai *dai)
828 struct ssp_priv *priv = snd_soc_dai_get_drvdata(dai);
830 pxa_ssp_free(priv->ssp);
835 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
836 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
837 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
838 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_64000 | \
839 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
841 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE)
843 static const struct snd_soc_dai_ops pxa_ssp_dai_ops = {
844 .startup = pxa_ssp_startup,
845 .shutdown = pxa_ssp_shutdown,
846 .trigger = pxa_ssp_trigger,
847 .hw_params = pxa_ssp_hw_params,
848 .set_sysclk = pxa_ssp_set_dai_sysclk,
849 .set_fmt = pxa_ssp_set_dai_fmt,
850 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot,
851 .set_tristate = pxa_ssp_set_dai_tristate,
854 static struct snd_soc_dai_driver pxa_ssp_dai = {
855 .probe = pxa_ssp_probe,
856 .remove = pxa_ssp_remove,
857 .suspend = pxa_ssp_suspend,
858 .resume = pxa_ssp_resume,
862 .rates = PXA_SSP_RATES,
863 .formats = PXA_SSP_FORMATS,
868 .rates = PXA_SSP_RATES,
869 .formats = PXA_SSP_FORMATS,
871 .ops = &pxa_ssp_dai_ops,
874 static const struct snd_soc_component_driver pxa_ssp_component = {
876 .ops = &pxa2xx_pcm_ops,
877 .pcm_new = pxa2xx_soc_pcm_new,
878 .pcm_free = pxa2xx_pcm_free_dma_buffers,
882 static const struct of_device_id pxa_ssp_of_ids[] = {
883 { .compatible = "mrvl,pxa-ssp-dai" },
886 MODULE_DEVICE_TABLE(of, pxa_ssp_of_ids);
889 static int asoc_ssp_probe(struct platform_device *pdev)
891 return devm_snd_soc_register_component(&pdev->dev, &pxa_ssp_component,
895 static struct platform_driver asoc_ssp_driver = {
897 .name = "pxa-ssp-dai",
898 .of_match_table = of_match_ptr(pxa_ssp_of_ids),
901 .probe = asoc_ssp_probe,
904 module_platform_driver(asoc_ssp_driver);
906 /* Module information */
907 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
908 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface");
909 MODULE_LICENSE("GPL");
910 MODULE_ALIAS("platform:pxa-ssp-dai");