2 * omap-mcbsp.c -- OMAP ALSA SoC DAI driver using McBSP port
4 * Copyright (C) 2008 Nokia Corporation
6 * Contact: Jarkko Nikula <jarkko.nikula@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/init.h>
25 #include <linux/module.h>
26 #include <linux/device.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/initval.h>
31 #include <sound/soc.h>
33 #include <mach/control.h>
35 #include <mach/mcbsp.h>
36 #include "omap-mcbsp.h"
39 #define OMAP_MCBSP_RATES (SNDRV_PCM_RATE_8000_96000)
41 struct omap_mcbsp_data {
43 struct omap_mcbsp_reg_cfg regs;
46 * Flags indicating is the bus already activated and configured by
53 #define to_mcbsp(priv) container_of((priv), struct omap_mcbsp_data, bus_id)
55 static struct omap_mcbsp_data mcbsp_data[NUM_LINKS];
58 * Stream DMA parameters. DMA request line and port address are set runtime
59 * since they are different between OMAP1 and later OMAPs
61 static struct omap_pcm_dma_data omap_mcbsp_dai_dma_params[NUM_LINKS][2];
63 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
64 static const int omap1_dma_reqs[][2] = {
65 { OMAP_DMA_MCBSP1_TX, OMAP_DMA_MCBSP1_RX },
66 { OMAP_DMA_MCBSP2_TX, OMAP_DMA_MCBSP2_RX },
67 { OMAP_DMA_MCBSP3_TX, OMAP_DMA_MCBSP3_RX },
69 static const unsigned long omap1_mcbsp_port[][2] = {
70 { OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
71 OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
72 { OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
73 OMAP1510_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
74 { OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DXR1,
75 OMAP1510_MCBSP3_BASE + OMAP_MCBSP_REG_DRR1 },
78 static const int omap1_dma_reqs[][2] = {};
79 static const unsigned long omap1_mcbsp_port[][2] = {};
82 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
83 static const int omap24xx_dma_reqs[][2] = {
84 { OMAP24XX_DMA_MCBSP1_TX, OMAP24XX_DMA_MCBSP1_RX },
85 { OMAP24XX_DMA_MCBSP2_TX, OMAP24XX_DMA_MCBSP2_RX },
86 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
87 { OMAP24XX_DMA_MCBSP3_TX, OMAP24XX_DMA_MCBSP3_RX },
88 { OMAP24XX_DMA_MCBSP4_TX, OMAP24XX_DMA_MCBSP4_RX },
89 { OMAP24XX_DMA_MCBSP5_TX, OMAP24XX_DMA_MCBSP5_RX },
93 static const int omap24xx_dma_reqs[][2] = {};
96 #if defined(CONFIG_ARCH_OMAP2420)
97 static const unsigned long omap2420_mcbsp_port[][2] = {
98 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1,
99 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1 },
100 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1,
101 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1 },
104 static const unsigned long omap2420_mcbsp_port[][2] = {};
107 #if defined(CONFIG_ARCH_OMAP2430)
108 static const unsigned long omap2430_mcbsp_port[][2] = {
109 { OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
110 OMAP24XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
111 { OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
112 OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
113 { OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
114 OMAP2430_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
115 { OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
116 OMAP2430_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
117 { OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
118 OMAP2430_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
121 static const unsigned long omap2430_mcbsp_port[][2] = {};
124 #if defined(CONFIG_ARCH_OMAP34XX)
125 static const unsigned long omap34xx_mcbsp_port[][2] = {
126 { OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DXR,
127 OMAP34XX_MCBSP1_BASE + OMAP_MCBSP_REG_DRR },
128 { OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR,
129 OMAP34XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR },
130 { OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DXR,
131 OMAP34XX_MCBSP3_BASE + OMAP_MCBSP_REG_DRR },
132 { OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DXR,
133 OMAP34XX_MCBSP4_BASE + OMAP_MCBSP_REG_DRR },
134 { OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DXR,
135 OMAP34XX_MCBSP5_BASE + OMAP_MCBSP_REG_DRR },
138 static const unsigned long omap34xx_mcbsp_port[][2] = {};
141 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
142 struct snd_soc_dai *dai)
144 struct snd_soc_pcm_runtime *rtd = substream->private_data;
145 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
146 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
149 if (cpu_is_omap343x() && mcbsp_data->bus_id == 1) {
151 * McBSP2 in OMAP3 has 1024 * 32-bit internal audio buffer.
152 * Set constraint for minimum buffer size to the same than FIFO
153 * size in order to avoid underruns in playback startup because
154 * HW is keeping the DMA request active until FIFO is filled.
156 snd_pcm_hw_constraint_minmax(substream->runtime,
157 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 4096, UINT_MAX);
160 if (!cpu_dai->active)
161 err = omap_mcbsp_request(mcbsp_data->bus_id);
166 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
167 struct snd_soc_dai *dai)
169 struct snd_soc_pcm_runtime *rtd = substream->private_data;
170 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
171 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
173 if (!cpu_dai->active) {
174 omap_mcbsp_free(mcbsp_data->bus_id);
175 mcbsp_data->configured = 0;
179 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
180 struct snd_soc_dai *dai)
182 struct snd_soc_pcm_runtime *rtd = substream->private_data;
183 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
184 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
188 case SNDRV_PCM_TRIGGER_START:
189 case SNDRV_PCM_TRIGGER_RESUME:
190 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
191 if (!mcbsp_data->active++)
192 omap_mcbsp_start(mcbsp_data->bus_id);
195 case SNDRV_PCM_TRIGGER_STOP:
196 case SNDRV_PCM_TRIGGER_SUSPEND:
197 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
198 if (!--mcbsp_data->active)
199 omap_mcbsp_stop(mcbsp_data->bus_id);
208 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
209 struct snd_pcm_hw_params *params,
210 struct snd_soc_dai *dai)
212 struct snd_soc_pcm_runtime *rtd = substream->private_data;
213 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
214 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
215 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
216 int dma, bus_id = mcbsp_data->bus_id, id = cpu_dai->id;
217 int wlen, channels, wpf;
221 if (cpu_class_is_omap1()) {
222 dma = omap1_dma_reqs[bus_id][substream->stream];
223 port = omap1_mcbsp_port[bus_id][substream->stream];
224 } else if (cpu_is_omap2420()) {
225 dma = omap24xx_dma_reqs[bus_id][substream->stream];
226 port = omap2420_mcbsp_port[bus_id][substream->stream];
227 } else if (cpu_is_omap2430()) {
228 dma = omap24xx_dma_reqs[bus_id][substream->stream];
229 port = omap2430_mcbsp_port[bus_id][substream->stream];
230 } else if (cpu_is_omap343x()) {
231 dma = omap24xx_dma_reqs[bus_id][substream->stream];
232 port = omap34xx_mcbsp_port[bus_id][substream->stream];
236 omap_mcbsp_dai_dma_params[id][substream->stream].name =
237 substream->stream ? "Audio Capture" : "Audio Playback";
238 omap_mcbsp_dai_dma_params[id][substream->stream].dma_req = dma;
239 omap_mcbsp_dai_dma_params[id][substream->stream].port_addr = port;
240 cpu_dai->dma_data = &omap_mcbsp_dai_dma_params[id][substream->stream];
242 if (mcbsp_data->configured) {
243 /* McBSP already configured by another stream */
247 format = mcbsp_data->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
248 wpf = channels = params_channels(params);
251 if (format == SND_SOC_DAIFMT_I2S) {
252 /* Use dual-phase frames */
253 regs->rcr2 |= RPHASE;
254 regs->xcr2 |= XPHASE;
255 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
257 regs->rcr2 |= RFRLEN2(wpf - 1);
258 regs->xcr2 |= XFRLEN2(wpf - 1);
261 /* Set word per (McBSP) frame for phase1 */
262 regs->rcr1 |= RFRLEN1(wpf - 1);
263 regs->xcr1 |= XFRLEN1(wpf - 1);
266 /* Unsupported number of channels */
270 switch (params_format(params)) {
271 case SNDRV_PCM_FORMAT_S16_LE:
272 /* Set word lengths */
274 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16);
275 regs->rcr1 |= RWDLEN1(OMAP_MCBSP_WORD_16);
276 regs->xcr2 |= XWDLEN2(OMAP_MCBSP_WORD_16);
277 regs->xcr1 |= XWDLEN1(OMAP_MCBSP_WORD_16);
280 /* Unsupported PCM format */
284 /* Set FS period and length in terms of bit clock periods */
286 case SND_SOC_DAIFMT_I2S:
287 regs->srgr2 |= FPER(wlen * channels - 1);
288 regs->srgr1 |= FWID(wlen - 1);
290 case SND_SOC_DAIFMT_DSP_A:
291 case SND_SOC_DAIFMT_DSP_B:
292 regs->srgr2 |= FPER(wlen * channels - 1);
293 regs->srgr1 |= FWID(wlen * channels - 2);
297 omap_mcbsp_config(bus_id, &mcbsp_data->regs);
298 mcbsp_data->configured = 1;
304 * This must be called before _set_clkdiv and _set_sysclk since McBSP register
305 * cache is initialized here
307 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
310 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
311 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
313 if (mcbsp_data->configured)
316 mcbsp_data->fmt = fmt;
317 memset(regs, 0, sizeof(*regs));
318 /* Generic McBSP register settings */
319 regs->spcr2 |= XINTM(3) | FREE;
320 regs->spcr1 |= RINTM(3);
323 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
324 regs->xccr = DXENDLY(1) | XDMAEN;
325 regs->rccr = RFULL_CYCLE | RDMAEN;
328 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
329 case SND_SOC_DAIFMT_I2S:
330 /* 1-bit data delay */
331 regs->rcr2 |= RDATDLY(1);
332 regs->xcr2 |= XDATDLY(1);
334 case SND_SOC_DAIFMT_DSP_A:
335 /* 1-bit data delay */
336 regs->rcr2 |= RDATDLY(1);
337 regs->xcr2 |= XDATDLY(1);
338 /* Invert FS polarity configuration */
339 temp_fmt ^= SND_SOC_DAIFMT_NB_IF;
341 case SND_SOC_DAIFMT_DSP_B:
342 /* 0-bit data delay */
343 regs->rcr2 |= RDATDLY(0);
344 regs->xcr2 |= XDATDLY(0);
347 /* Unsupported data format */
351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
352 case SND_SOC_DAIFMT_CBS_CFS:
353 /* McBSP master. Set FS and bit clocks as outputs */
354 regs->pcr0 |= FSXM | FSRM |
356 /* Sample rate generator drives the FS */
359 case SND_SOC_DAIFMT_CBM_CFM:
363 /* Unsupported master/slave configuration */
367 /* Set bit clock (CLKX/CLKR) and FS polarities */
368 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
369 case SND_SOC_DAIFMT_NB_NF:
372 * FS active low. TX data driven on falling edge of bit clock
373 * and RX data sampled on rising edge of bit clock.
375 regs->pcr0 |= FSXP | FSRP |
378 case SND_SOC_DAIFMT_NB_IF:
379 regs->pcr0 |= CLKXP | CLKRP;
381 case SND_SOC_DAIFMT_IB_NF:
382 regs->pcr0 |= FSXP | FSRP;
384 case SND_SOC_DAIFMT_IB_IF:
393 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
396 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
397 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
399 if (div_id != OMAP_MCBSP_CLKGDV)
402 regs->srgr1 |= CLKGDV(div - 1);
407 static int omap_mcbsp_dai_set_clks_src(struct omap_mcbsp_data *mcbsp_data,
411 u16 reg, reg_devconf1 = OMAP243X_CONTROL_DEVCONF1;
413 if (cpu_class_is_omap1()) {
414 /* OMAP1's can use only external source clock */
415 if (unlikely(clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK))
421 if (cpu_is_omap2420() && mcbsp_data->bus_id > 1)
424 if (cpu_is_omap343x())
425 reg_devconf1 = OMAP343X_CONTROL_DEVCONF1;
427 switch (mcbsp_data->bus_id) {
429 reg = OMAP2_CONTROL_DEVCONF0;
433 reg = OMAP2_CONTROL_DEVCONF0;
452 if (clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK)
453 omap_ctrl_writel(omap_ctrl_readl(reg) & ~(1 << sel_bit), reg);
455 omap_ctrl_writel(omap_ctrl_readl(reg) | (1 << sel_bit), reg);
460 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
461 int clk_id, unsigned int freq,
464 struct omap_mcbsp_data *mcbsp_data = to_mcbsp(cpu_dai->private_data);
465 struct omap_mcbsp_reg_cfg *regs = &mcbsp_data->regs;
469 case OMAP_MCBSP_SYSCLK_CLK:
470 regs->srgr2 |= CLKSM;
472 case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
473 case OMAP_MCBSP_SYSCLK_CLKS_EXT:
474 err = omap_mcbsp_dai_set_clks_src(mcbsp_data, clk_id);
477 case OMAP_MCBSP_SYSCLK_CLKX_EXT:
478 regs->srgr2 |= CLKSM;
479 case OMAP_MCBSP_SYSCLK_CLKR_EXT:
480 regs->pcr0 |= SCLKME;
489 static struct snd_soc_dai_ops omap_mcbsp_dai_ops = {
490 .startup = omap_mcbsp_dai_startup,
491 .shutdown = omap_mcbsp_dai_shutdown,
492 .trigger = omap_mcbsp_dai_trigger,
493 .hw_params = omap_mcbsp_dai_hw_params,
494 .set_fmt = omap_mcbsp_dai_set_dai_fmt,
495 .set_clkdiv = omap_mcbsp_dai_set_clkdiv,
496 .set_sysclk = omap_mcbsp_dai_set_dai_sysclk,
499 #define OMAP_MCBSP_DAI_BUILDER(link_id) \
501 .name = "omap-mcbsp-dai-"#link_id, \
506 .rates = OMAP_MCBSP_RATES, \
507 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
512 .rates = OMAP_MCBSP_RATES, \
513 .formats = SNDRV_PCM_FMTBIT_S16_LE, \
515 .ops = &omap_mcbsp_dai_ops, \
516 .private_data = &mcbsp_data[(link_id)].bus_id, \
519 struct snd_soc_dai omap_mcbsp_dai[] = {
520 OMAP_MCBSP_DAI_BUILDER(0),
521 OMAP_MCBSP_DAI_BUILDER(1),
523 OMAP_MCBSP_DAI_BUILDER(2),
526 OMAP_MCBSP_DAI_BUILDER(3),
527 OMAP_MCBSP_DAI_BUILDER(4),
531 EXPORT_SYMBOL_GPL(omap_mcbsp_dai);
533 static int __init snd_omap_mcbsp_init(void)
535 return snd_soc_register_dais(omap_mcbsp_dai,
536 ARRAY_SIZE(omap_mcbsp_dai));
538 module_init(snd_omap_mcbsp_init);
540 static void __exit snd_omap_mcbsp_exit(void)
542 snd_soc_unregister_dais(omap_mcbsp_dai, ARRAY_SIZE(omap_mcbsp_dai));
544 module_exit(snd_omap_mcbsp_exit);
546 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@nokia.com>");
547 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
548 MODULE_LICENSE("GPL");