1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011 Freescale Semiconductor, Inc.
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/of_device.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/clk.h>
14 #include <linux/clk-provider.h>
15 #include <linux/delay.h>
17 #include <linux/time.h>
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/soc.h>
25 #define MXS_SET_ADDR 0x4
26 #define MXS_CLR_ADDR 0x8
28 static struct mxs_saif *mxs_saif[2];
31 * SAIF is a little different with other normal SOC DAIs on clock using.
33 * For MXS, two SAIF modules are instantiated on-chip.
34 * Each SAIF has a set of clock pins and can be operating in master
35 * mode simultaneously if they are connected to different off-chip codecs.
36 * Also, one of the two SAIFs can master or drive the clock pins while the
37 * other SAIF, in slave mode, receives clocking from the master SAIF.
38 * This also means that both SAIFs must operate at the same sample rate.
40 * We abstract this as each saif has a master, the master could be
41 * itself or other saifs. In the generic saif driver, saif does not need
42 * to know the different clkmux. Saif only needs to know who is its master
43 * and operating its master to generate the proper clock rate for it.
44 * The master id is provided in mach-specific layer according to different
48 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
49 int clk_id, unsigned int freq, int dir)
51 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
64 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
65 * is provided by other SAIF, we provide a interface here to get its master
67 * Note that the master could be itself.
69 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
71 return mxs_saif[saif->master_id];
75 * Set SAIF clock and MCLK
77 static int mxs_saif_set_clk(struct mxs_saif *saif,
83 struct mxs_saif *master_saif;
85 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
87 /* Set master saif to generate proper clock */
88 master_saif = mxs_saif_get_master(saif);
92 dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
94 /* Checking if can playback and capture simutaneously */
95 if (master_saif->ongoing && rate != master_saif->cur_rate) {
97 "can not change clock, master saif%d(rate %d) is ongoing\n",
98 master_saif->id, master_saif->cur_rate);
102 scr = __raw_readl(master_saif->base + SAIF_CTRL);
103 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
104 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
109 * The SAIF clock should be either 384*fs or 512*fs.
110 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
111 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
112 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
114 * If MCLK is not used, we just set saif clk to 512*fs.
116 ret = clk_prepare_enable(master_saif->clk);
120 if (master_saif->mclk_in_use) {
121 switch (mclk / rate) {
127 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
128 ret = clk_set_rate(master_saif->clk, 512 * rate);
134 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
135 ret = clk_set_rate(master_saif->clk, 384 * rate);
138 /* SAIF MCLK should be a sub-rate of 512x or 384x */
139 clk_disable_unprepare(master_saif->clk);
143 ret = clk_set_rate(master_saif->clk, 512 * rate);
144 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
147 clk_disable_unprepare(master_saif->clk);
152 master_saif->cur_rate = rate;
154 if (!master_saif->mclk_in_use) {
155 __raw_writel(scr, master_saif->base + SAIF_CTRL);
160 * Program the over-sample rate for MCLK output
162 * The available MCLK range is 32x, 48x... 512x. The rate
163 * could be from 8kHz to 192kH.
165 switch (mclk / rate) {
167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
173 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
176 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
188 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
191 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
197 __raw_writel(scr, master_saif->base + SAIF_CTRL);
203 * Put and disable MCLK.
205 int mxs_saif_put_mclk(unsigned int saif_id)
207 struct mxs_saif *saif = mxs_saif[saif_id];
213 stat = __raw_readl(saif->base + SAIF_STAT);
214 if (stat & BM_SAIF_STAT_BUSY) {
215 dev_err(saif->dev, "error: busy\n");
219 clk_disable_unprepare(saif->clk);
221 /* disable MCLK output */
222 __raw_writel(BM_SAIF_CTRL_CLKGATE,
223 saif->base + SAIF_CTRL + MXS_SET_ADDR);
224 __raw_writel(BM_SAIF_CTRL_RUN,
225 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
227 saif->mclk_in_use = 0;
230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk);
233 * Get MCLK and set clock rate, then enable it
235 * This interface is used for codecs who are using MCLK provided
238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
241 struct mxs_saif *saif = mxs_saif[saif_id];
244 struct mxs_saif *master_saif;
250 __raw_writel(BM_SAIF_CTRL_SFTRST,
251 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
253 /* FIXME: need clear clk gate for register r/w */
254 __raw_writel(BM_SAIF_CTRL_CLKGATE,
255 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
257 master_saif = mxs_saif_get_master(saif);
258 if (saif != master_saif) {
259 dev_err(saif->dev, "can not get mclk from a non-master saif\n");
263 stat = __raw_readl(saif->base + SAIF_STAT);
264 if (stat & BM_SAIF_STAT_BUSY) {
265 dev_err(saif->dev, "error: busy\n");
269 saif->mclk_in_use = 1;
270 ret = mxs_saif_set_clk(saif, mclk, rate);
274 ret = clk_prepare_enable(saif->clk);
278 /* enable MCLK output */
279 __raw_writel(BM_SAIF_CTRL_RUN,
280 saif->base + SAIF_CTRL + MXS_SET_ADDR);
284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk);
287 * SAIF DAI format configuration.
288 * Should only be called when port is inactive.
290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
296 stat = __raw_readl(saif->base + SAIF_STAT);
297 if (stat & BM_SAIF_STAT_BUSY) {
298 dev_err(cpu_dai->dev, "error: busy\n");
302 /* If SAIF1 is configured as slave, the clk gate needs to be cleared
303 * before the register can be written.
305 if (saif->id != saif->master_id) {
306 __raw_writel(BM_SAIF_CTRL_SFTRST,
307 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
308 __raw_writel(BM_SAIF_CTRL_CLKGATE,
309 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
312 scr0 = __raw_readl(saif->base + SAIF_CTRL);
313 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
314 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
318 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
319 case SND_SOC_DAIFMT_I2S:
320 /* data frame low 1clk before data */
321 scr |= BM_SAIF_CTRL_DELAY;
322 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
324 case SND_SOC_DAIFMT_LEFT_J:
325 /* data frame high with data */
326 scr &= ~BM_SAIF_CTRL_DELAY;
327 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
328 scr &= ~BM_SAIF_CTRL_JUSTIFY;
334 /* DAI clock inversion */
335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
336 case SND_SOC_DAIFMT_IB_IF:
337 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
338 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
340 case SND_SOC_DAIFMT_IB_NF:
341 scr |= BM_SAIF_CTRL_BITCLK_EDGE;
342 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
344 case SND_SOC_DAIFMT_NB_IF:
345 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
346 scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
348 case SND_SOC_DAIFMT_NB_NF:
349 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
350 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
355 * Note: We simply just support master mode since SAIF TX can only
357 * Here the master is relative to codec side.
358 * Saif internally could be slave when working on EXTMASTER mode.
359 * We just hide this to machine driver.
361 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
362 case SND_SOC_DAIFMT_CBS_CFS:
363 if (saif->id == saif->master_id)
364 scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
366 scr |= BM_SAIF_CTRL_SLAVE_MODE;
368 __raw_writel(scr | scr0, saif->base + SAIF_CTRL);
377 static int mxs_saif_startup(struct snd_pcm_substream *substream,
378 struct snd_soc_dai *cpu_dai)
380 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
383 /* clear error status to 0 for each re-open */
384 saif->fifo_underrun = 0;
385 saif->fifo_overrun = 0;
387 /* Clear Reset for normal operations */
388 __raw_writel(BM_SAIF_CTRL_SFTRST,
389 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
391 /* clear clock gate */
392 __raw_writel(BM_SAIF_CTRL_CLKGATE,
393 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
395 ret = clk_prepare(saif->clk);
402 static void mxs_saif_shutdown(struct snd_pcm_substream *substream,
403 struct snd_soc_dai *cpu_dai)
405 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
407 clk_unprepare(saif->clk);
411 * Should only be called when port is inactive.
412 * although can be called multiple times by upper layers.
414 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
415 struct snd_pcm_hw_params *params,
416 struct snd_soc_dai *cpu_dai)
418 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
419 struct mxs_saif *master_saif;
423 master_saif = mxs_saif_get_master(saif);
427 /* mclk should already be set */
428 if (!saif->mclk && saif->mclk_in_use) {
429 dev_err(cpu_dai->dev, "set mclk first\n");
433 stat = __raw_readl(saif->base + SAIF_STAT);
434 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) {
435 dev_err(cpu_dai->dev, "error: busy\n");
440 * Set saif clk based on sample rate.
441 * If mclk is used, we also set mclk, if not, saif->mclk is
442 * default 0, means not used.
444 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
446 dev_err(cpu_dai->dev, "unable to get proper clk\n");
450 if (saif != master_saif) {
452 * Set an initial clock rate for the saif internal logic to work
453 * properly. This is important when working in EXTMASTER mode
454 * that uses the other saif's BITCLK&LRCLK but it still needs a
455 * basic clock which should be fast enough for the internal
458 ret = clk_enable(saif->clk);
462 ret = clk_set_rate(saif->clk, 24000000);
463 clk_disable(saif->clk);
467 ret = clk_prepare(master_saif->clk);
472 scr = __raw_readl(saif->base + SAIF_CTRL);
474 scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
475 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
476 switch (params_format(params)) {
477 case SNDRV_PCM_FORMAT_S16_LE:
478 scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
480 case SNDRV_PCM_FORMAT_S20_3LE:
481 scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
482 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
484 case SNDRV_PCM_FORMAT_S24_LE:
485 scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
486 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
495 scr &= ~BM_SAIF_CTRL_READ_MODE;
498 scr |= BM_SAIF_CTRL_READ_MODE;
501 __raw_writel(scr, saif->base + SAIF_CTRL);
505 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
506 struct snd_soc_dai *cpu_dai)
508 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
510 /* enable FIFO error irqs */
511 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
512 saif->base + SAIF_CTRL + MXS_SET_ADDR);
517 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
518 struct snd_soc_dai *cpu_dai)
520 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
521 struct mxs_saif *master_saif;
525 master_saif = mxs_saif_get_master(saif);
530 case SNDRV_PCM_TRIGGER_START:
531 case SNDRV_PCM_TRIGGER_RESUME:
532 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
533 if (saif->state == MXS_SAIF_STATE_RUNNING)
536 dev_dbg(cpu_dai->dev, "start\n");
538 ret = clk_enable(master_saif->clk);
540 dev_err(saif->dev, "Failed to enable master clock\n");
545 * If the saif's master is not itself, we also need to enable
546 * itself clk for its internal basic logic to work.
548 if (saif != master_saif) {
549 ret = clk_enable(saif->clk);
551 dev_err(saif->dev, "Failed to enable master clock\n");
552 clk_disable(master_saif->clk);
556 __raw_writel(BM_SAIF_CTRL_RUN,
557 saif->base + SAIF_CTRL + MXS_SET_ADDR);
560 if (!master_saif->mclk_in_use)
561 __raw_writel(BM_SAIF_CTRL_RUN,
562 master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
564 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
566 * write data to saif data register to trigger
568 * For 24-bit format the 32-bit FIFO register stores
569 * only one channel, so we need to write twice.
570 * This is also safe for the other non 24-bit formats.
572 __raw_writel(0, saif->base + SAIF_DATA);
573 __raw_writel(0, saif->base + SAIF_DATA);
576 * read data from saif data register to trigger
578 * For 24-bit format the 32-bit FIFO register stores
579 * only one channel, so we need to read twice.
580 * This is also safe for the other non 24-bit formats.
582 __raw_readl(saif->base + SAIF_DATA);
583 __raw_readl(saif->base + SAIF_DATA);
586 master_saif->ongoing = 1;
587 saif->state = MXS_SAIF_STATE_RUNNING;
589 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
590 __raw_readl(saif->base + SAIF_CTRL),
591 __raw_readl(saif->base + SAIF_STAT));
593 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
594 __raw_readl(master_saif->base + SAIF_CTRL),
595 __raw_readl(master_saif->base + SAIF_STAT));
597 case SNDRV_PCM_TRIGGER_SUSPEND:
598 case SNDRV_PCM_TRIGGER_STOP:
599 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
600 if (saif->state == MXS_SAIF_STATE_STOPPED)
603 dev_dbg(cpu_dai->dev, "stop\n");
605 /* wait a while for the current sample to complete */
606 delay = USEC_PER_SEC / master_saif->cur_rate;
608 if (!master_saif->mclk_in_use) {
609 __raw_writel(BM_SAIF_CTRL_RUN,
610 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
613 clk_disable(master_saif->clk);
615 if (saif != master_saif) {
616 __raw_writel(BM_SAIF_CTRL_RUN,
617 saif->base + SAIF_CTRL + MXS_CLR_ADDR);
619 clk_disable(saif->clk);
622 master_saif->ongoing = 0;
623 saif->state = MXS_SAIF_STATE_STOPPED;
633 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000
634 #define MXS_SAIF_FORMATS \
635 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
636 SNDRV_PCM_FMTBIT_S24_LE)
638 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
639 .startup = mxs_saif_startup,
640 .shutdown = mxs_saif_shutdown,
641 .trigger = mxs_saif_trigger,
642 .prepare = mxs_saif_prepare,
643 .hw_params = mxs_saif_hw_params,
644 .set_sysclk = mxs_saif_set_dai_sysclk,
645 .set_fmt = mxs_saif_set_dai_fmt,
648 static struct snd_soc_dai_driver mxs_saif_dai = {
653 .rates = MXS_SAIF_RATES,
654 .formats = MXS_SAIF_FORMATS,
659 .rates = MXS_SAIF_RATES,
660 .formats = MXS_SAIF_FORMATS,
662 .ops = &mxs_saif_dai_ops,
665 static const struct snd_soc_component_driver mxs_saif_component = {
669 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
671 struct mxs_saif *saif = dev_id;
674 stat = __raw_readl(saif->base + SAIF_STAT);
675 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
676 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
679 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
680 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
681 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
682 saif->base + SAIF_STAT + MXS_CLR_ADDR);
685 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
686 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
687 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
688 saif->base + SAIF_STAT + MXS_CLR_ADDR);
691 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
692 __raw_readl(saif->base + SAIF_CTRL),
693 __raw_readl(saif->base + SAIF_STAT));
698 static int mxs_saif_mclk_init(struct platform_device *pdev)
700 struct mxs_saif *saif = platform_get_drvdata(pdev);
701 struct device_node *np = pdev->dev.of_node;
705 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk",
706 __clk_get_name(saif->clk), 0,
707 saif->base + SAIF_CTRL,
708 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3,
714 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret);
718 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
725 static int mxs_saif_probe(struct platform_device *pdev)
727 struct device_node *np = pdev->dev.of_node;
728 struct mxs_saif *saif;
730 struct device_node *master;
732 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
736 ret = of_alias_get_id(np, "saif");
742 if (saif->id >= ARRAY_SIZE(mxs_saif)) {
743 dev_err(&pdev->dev, "get wrong saif id\n");
748 * If there is no "fsl,saif-master" phandle, it's a saif
749 * master. Otherwise, it's a slave and its phandle points
752 master = of_parse_phandle(np, "fsl,saif-master", 0);
754 saif->master_id = saif->id;
756 ret = of_alias_get_id(master, "saif");
761 saif->master_id = ret;
763 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
764 dev_err(&pdev->dev, "get wrong master id\n");
769 mxs_saif[saif->id] = saif;
771 saif->clk = devm_clk_get(&pdev->dev, NULL);
772 if (IS_ERR(saif->clk)) {
773 ret = PTR_ERR(saif->clk);
774 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
779 saif->base = devm_platform_ioremap_resource(pdev, 0);
780 if (IS_ERR(saif->base))
781 return PTR_ERR(saif->base);
783 irq = platform_get_irq(pdev, 0);
787 saif->dev = &pdev->dev;
788 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
789 dev_name(&pdev->dev), saif);
791 dev_err(&pdev->dev, "failed to request irq\n");
795 platform_set_drvdata(pdev, saif);
797 /* We only support saif0 being tx and clock master */
799 ret = mxs_saif_mclk_init(pdev);
801 dev_warn(&pdev->dev, "failed to init clocks\n");
804 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
807 dev_err(&pdev->dev, "register DAI failed\n");
811 ret = mxs_pcm_platform_register(&pdev->dev);
813 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
820 static const struct of_device_id mxs_saif_dt_ids[] = {
821 { .compatible = "fsl,imx28-saif", },
824 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids);
826 static struct platform_driver mxs_saif_driver = {
827 .probe = mxs_saif_probe,
831 .of_match_table = mxs_saif_dt_ids,
835 module_platform_driver(mxs_saif_driver);
837 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
838 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
839 MODULE_LICENSE("GPL");
840 MODULE_ALIAS("platform:mxs-saif");