1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 // Copyright (c) 2018 BayLibre, SAS.
4 // Author: Jerome Brunet <jbrunet@baylibre.com>
7 #include <linux/module.h>
8 #include <linux/of_platform.h>
9 #include <sound/pcm_params.h>
10 #include <sound/soc.h>
11 #include <sound/soc-dai.h>
15 /* Maximum bit clock frequency according the datasheets */
16 #define MAX_SCLK 100000000 /* Hz */
23 static unsigned int axg_tdm_slots_total(u32 *mask)
25 unsigned int slots = 0;
31 /* Count the total number of slots provided by all 4 lanes */
32 for (i = 0; i < AXG_TDM_NUM_LANES; i++)
33 slots += hweight32(mask[i]);
38 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask,
39 u32 *rx_mask, unsigned int slots,
40 unsigned int slot_width)
42 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
43 struct axg_tdm_stream *tx = snd_soc_dai_dma_data_get_playback(dai);
44 struct axg_tdm_stream *rx = snd_soc_dai_dma_data_get_capture(dai);
45 unsigned int tx_slots, rx_slots;
48 tx_slots = axg_tdm_slots_total(tx_mask);
49 rx_slots = axg_tdm_slots_total(rx_mask);
51 /* We should at least have a slot for a valid interface */
52 if (!tx_slots && !rx_slots) {
53 dev_err(dai->dev, "interface has no slot\n");
64 fmt |= SNDRV_PCM_FMTBIT_S32_LE;
67 fmt |= SNDRV_PCM_FMTBIT_S24_LE;
68 fmt |= SNDRV_PCM_FMTBIT_S20_LE;
71 fmt |= SNDRV_PCM_FMTBIT_S16_LE;
74 fmt |= SNDRV_PCM_FMTBIT_S8;
77 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
81 iface->slot_width = slot_width;
83 /* Amend the dai driver and let dpcm merge do its job */
86 dai->driver->playback.channels_max = tx_slots;
87 dai->driver->playback.formats = fmt;
92 dai->driver->capture.channels_max = rx_slots;
93 dai->driver->capture.formats = fmt;
98 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
100 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id,
101 unsigned int freq, int dir)
103 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
106 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) {
108 dev_warn(dai->dev, "master clock not provided\n");
110 ret = clk_set_rate(iface->mclk, freq);
112 iface->mclk_rate = freq;
119 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
121 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
123 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
124 case SND_SOC_DAIFMT_BP_FP:
126 dev_err(dai->dev, "cpu clock master: mclk missing\n");
131 case SND_SOC_DAIFMT_BC_FC:
134 case SND_SOC_DAIFMT_BP_FC:
135 case SND_SOC_DAIFMT_BC_FP:
136 dev_err(dai->dev, "only BP_FP and BC_FC are supported\n");
146 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream,
147 struct snd_soc_dai *dai)
149 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
150 struct axg_tdm_stream *ts =
151 snd_soc_dai_get_dma_data(dai, substream);
154 if (!axg_tdm_slots_total(ts->mask)) {
155 dev_err(dai->dev, "interface has not slots\n");
159 if (snd_soc_component_active(dai->component)) {
160 /* Apply component wide rate symmetry */
161 ret = snd_pcm_hw_constraint_single(substream->runtime,
162 SNDRV_PCM_HW_PARAM_RATE,
166 /* Limit rate according to the slot number and width */
167 unsigned int max_rate =
168 MAX_SCLK / (iface->slots * iface->slot_width);
169 ret = snd_pcm_hw_constraint_minmax(substream->runtime,
170 SNDRV_PCM_HW_PARAM_RATE,
175 dev_err(dai->dev, "can't set iface rate constraint\n");
182 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream,
183 struct snd_pcm_hw_params *params,
184 struct snd_soc_dai *dai)
186 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
187 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
188 unsigned int channels = params_channels(params);
189 unsigned int width = params_width(params);
191 /* Save rate and sample_bits for component symmetry */
192 iface->rate = params_rate(params);
194 /* Make sure this interface can cope with the stream */
195 if (axg_tdm_slots_total(ts->mask) < channels) {
196 dev_err(dai->dev, "not enough slots for channels\n");
200 if (iface->slot_width < width) {
201 dev_err(dai->dev, "incompatible slots width for stream\n");
205 /* Save the parameter for tdmout/tdmin widgets */
206 ts->physical_width = params_physical_width(params);
207 ts->width = params_width(params);
208 ts->channels = params_channels(params);
213 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai,
214 struct snd_pcm_hw_params *params)
216 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
217 unsigned int ratio_num;
220 ret = clk_set_rate(iface->lrclk, params_rate(params));
222 dev_err(dai->dev, "setting sample clock failed: %d\n", ret);
226 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
227 case SND_SOC_DAIFMT_I2S:
228 case SND_SOC_DAIFMT_LEFT_J:
229 case SND_SOC_DAIFMT_RIGHT_J:
230 /* 50% duty cycle ratio */
234 case SND_SOC_DAIFMT_DSP_A:
235 case SND_SOC_DAIFMT_DSP_B:
237 * A zero duty cycle ratio will result in setting the mininum
238 * ratio possible which, for this clock, is 1 cycle of the
239 * parent bclk clock high and the rest low, This is exactly
249 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2);
252 "setting sample clock duty cycle failed: %d\n", ret);
256 /* Set sample clock inversion */
257 ret = clk_set_phase(iface->lrclk,
258 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0);
261 "setting sample clock phase failed: %d\n", ret);
268 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai,
269 struct snd_pcm_hw_params *params)
271 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
275 srate = iface->slots * iface->slot_width * params_rate(params);
277 if (!iface->mclk_rate) {
278 /* If no specific mclk is requested, default to bit clock * 2 */
279 clk_set_rate(iface->mclk, 2 * srate);
281 /* Check if we can actually get the bit clock from mclk */
282 if (iface->mclk_rate % srate) {
284 "can't derive sclk %lu from mclk %lu\n",
285 srate, iface->mclk_rate);
290 ret = clk_set_rate(iface->sclk, srate);
292 dev_err(dai->dev, "setting bit clock failed: %d\n", ret);
296 /* Set the bit clock inversion */
297 ret = clk_set_phase(iface->sclk,
298 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180);
300 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret);
307 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream,
308 struct snd_pcm_hw_params *params,
309 struct snd_soc_dai *dai)
311 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
312 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
315 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
316 case SND_SOC_DAIFMT_I2S:
317 case SND_SOC_DAIFMT_LEFT_J:
318 case SND_SOC_DAIFMT_RIGHT_J:
319 if (iface->slots > 2) {
320 dev_err(dai->dev, "bad slot number for format: %d\n",
326 case SND_SOC_DAIFMT_DSP_A:
327 case SND_SOC_DAIFMT_DSP_B:
331 dev_err(dai->dev, "unsupported dai format\n");
335 ret = axg_tdm_iface_set_stream(substream, params, dai);
339 if ((iface->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) ==
340 SND_SOC_DAIFMT_BP_FP) {
341 ret = axg_tdm_iface_set_sclk(dai, params);
345 ret = axg_tdm_iface_set_lrclk(dai, params);
350 ret = axg_tdm_stream_set_cont_clocks(ts, iface->fmt);
352 dev_err(dai->dev, "failed to apply continuous clock setting\n");
357 static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream,
358 struct snd_soc_dai *dai)
360 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream);
362 return axg_tdm_stream_set_cont_clocks(ts, 0);
365 static int axg_tdm_iface_trigger(struct snd_pcm_substream *substream,
367 struct snd_soc_dai *dai)
369 struct axg_tdm_stream *ts =
370 snd_soc_dai_get_dma_data(dai, substream);
373 case SNDRV_PCM_TRIGGER_START:
374 case SNDRV_PCM_TRIGGER_RESUME:
375 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
376 axg_tdm_stream_start(ts);
378 case SNDRV_PCM_TRIGGER_SUSPEND:
379 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
380 case SNDRV_PCM_TRIGGER_STOP:
381 axg_tdm_stream_stop(ts);
390 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai)
394 for_each_pcm_streams(stream) {
395 struct axg_tdm_stream *ts = snd_soc_dai_dma_data_get(dai, stream);
398 axg_tdm_stream_free(ts);
404 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai)
406 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai);
409 for_each_pcm_streams(stream) {
410 struct axg_tdm_stream *ts;
412 if (!snd_soc_dai_get_widget(dai, stream))
415 ts = axg_tdm_stream_alloc(iface);
417 axg_tdm_iface_remove_dai(dai);
420 snd_soc_dai_dma_data_set(dai, stream, ts);
426 static const struct snd_soc_dai_ops axg_tdm_iface_ops = {
427 .probe = axg_tdm_iface_probe_dai,
428 .remove = axg_tdm_iface_remove_dai,
429 .set_sysclk = axg_tdm_iface_set_sysclk,
430 .set_fmt = axg_tdm_iface_set_fmt,
431 .startup = axg_tdm_iface_startup,
432 .hw_params = axg_tdm_iface_hw_params,
433 .hw_free = axg_tdm_iface_hw_free,
434 .trigger = axg_tdm_iface_trigger,
437 /* TDM Backend DAIs */
438 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = {
442 .stream_name = "Playback",
444 .channels_max = AXG_TDM_CHANNEL_MAX,
445 .rates = AXG_TDM_RATES,
446 .formats = AXG_TDM_FORMATS,
449 .stream_name = "Capture",
451 .channels_max = AXG_TDM_CHANNEL_MAX,
452 .rates = AXG_TDM_RATES,
453 .formats = AXG_TDM_FORMATS,
456 .ops = &axg_tdm_iface_ops,
458 [TDM_IFACE_LOOPBACK] = {
459 .name = "TDM Loopback",
461 .stream_name = "Loopback",
463 .channels_max = AXG_TDM_CHANNEL_MAX,
464 .rates = AXG_TDM_RATES,
465 .formats = AXG_TDM_FORMATS,
467 .id = TDM_IFACE_LOOPBACK,
468 .ops = &axg_tdm_iface_ops,
472 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component,
473 enum snd_soc_bias_level level)
475 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component);
476 enum snd_soc_bias_level now =
477 snd_soc_component_get_bias_level(component);
481 case SND_SOC_BIAS_PREPARE:
482 if (now == SND_SOC_BIAS_STANDBY)
483 ret = clk_prepare_enable(iface->mclk);
486 case SND_SOC_BIAS_STANDBY:
487 if (now == SND_SOC_BIAS_PREPARE)
488 clk_disable_unprepare(iface->mclk);
491 case SND_SOC_BIAS_OFF:
492 case SND_SOC_BIAS_ON:
499 static const struct snd_soc_dapm_widget axg_tdm_iface_dapm_widgets[] = {
500 SND_SOC_DAPM_SIGGEN("Playback Signal"),
503 static const struct snd_soc_dapm_route axg_tdm_iface_dapm_routes[] = {
504 { "Loopback", NULL, "Playback Signal" },
507 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = {
508 .dapm_widgets = axg_tdm_iface_dapm_widgets,
509 .num_dapm_widgets = ARRAY_SIZE(axg_tdm_iface_dapm_widgets),
510 .dapm_routes = axg_tdm_iface_dapm_routes,
511 .num_dapm_routes = ARRAY_SIZE(axg_tdm_iface_dapm_routes),
512 .set_bias_level = axg_tdm_iface_set_bias_level,
515 static const struct of_device_id axg_tdm_iface_of_match[] = {
516 { .compatible = "amlogic,axg-tdm-iface", },
519 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match);
521 static int axg_tdm_iface_probe(struct platform_device *pdev)
523 struct device *dev = &pdev->dev;
524 struct snd_soc_dai_driver *dai_drv;
525 struct axg_tdm_iface *iface;
528 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL);
531 platform_set_drvdata(pdev, iface);
534 * Duplicate dai driver: depending on the slot masks configuration
535 * We'll change the number of channel provided by DAI stream, so dpcm
536 * channel merge can be done properly
538 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv),
539 sizeof(*dai_drv), GFP_KERNEL);
543 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++)
544 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i],
547 /* Bit clock provided on the pad */
548 iface->sclk = devm_clk_get(dev, "sclk");
549 if (IS_ERR(iface->sclk))
550 return dev_err_probe(dev, PTR_ERR(iface->sclk), "failed to get sclk\n");
552 /* Sample clock provided on the pad */
553 iface->lrclk = devm_clk_get(dev, "lrclk");
554 if (IS_ERR(iface->lrclk))
555 return dev_err_probe(dev, PTR_ERR(iface->lrclk), "failed to get lrclk\n");
558 * mclk maybe be missing when the cpu dai is in slave mode and
559 * the codec does not require it to provide a master clock.
560 * At this point, ignore the error if mclk is missing. We'll
561 * throw an error if the cpu dai is master and mclk is missing
563 iface->mclk = devm_clk_get_optional(dev, "mclk");
564 if (IS_ERR(iface->mclk))
565 return dev_err_probe(dev, PTR_ERR(iface->mclk), "failed to get mclk\n");
567 return devm_snd_soc_register_component(dev,
568 &axg_tdm_iface_component_drv, dai_drv,
569 ARRAY_SIZE(axg_tdm_iface_dai_drv));
572 static struct platform_driver axg_tdm_iface_pdrv = {
573 .probe = axg_tdm_iface_probe,
575 .name = "axg-tdm-iface",
576 .of_match_table = axg_tdm_iface_of_match,
579 module_platform_driver(axg_tdm_iface_pdrv);
581 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver");
582 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>");
583 MODULE_LICENSE("GPL v2");