1 // SPDX-License-Identifier: GPL-2.0-only
3 * skl.c - Implementation of ASoC Intel SKL HD Audio driver
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
8 * Derived mostly from Intel HDA driver with following copyrights:
9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
10 * PeiSen Hou <pshou@realtek.com.tw>
11 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/delay.h>
22 #include <sound/pcm.h>
23 #include <sound/soc-acpi.h>
24 #include <sound/soc-acpi-intel-match.h>
25 #include <sound/hda_register.h>
26 #include <sound/hdaudio.h>
27 #include <sound/hda_i915.h>
28 #include <sound/hda_codec.h>
29 #include <sound/intel-nhlt.h>
31 #include "skl-sst-dsp.h"
32 #include "skl-sst-ipc.h"
34 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
35 #include "../../../soc/codecs/hdac_hda.h"
37 static int skl_pci_binding;
38 module_param_named(pci_binding, skl_pci_binding, int, 0444);
39 MODULE_PARM_DESC(pci_binding, "PCI binding (0=auto, 1=only legacy, 2=only asoc");
42 * initialize the PCI registers
44 static void skl_update_pci_byte(struct pci_dev *pci, unsigned int reg,
45 unsigned char mask, unsigned char val)
49 pci_read_config_byte(pci, reg, &data);
52 pci_write_config_byte(pci, reg, data);
55 static void skl_init_pci(struct skl_dev *skl)
57 struct hdac_bus *bus = skl_to_bus(skl);
60 * Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
61 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
62 * Ensuring these bits are 0 clears playback static on some HD Audio
64 * The PCI register TCSEL is defined in the Intel manuals.
66 dev_dbg(bus->dev, "Clearing TCSEL\n");
67 skl_update_pci_byte(skl->pci, AZX_PCIREG_TCSEL, 0x07, 0);
70 static void update_pci_dword(struct pci_dev *pci,
71 unsigned int reg, u32 mask, u32 val)
75 pci_read_config_dword(pci, reg, &data);
78 pci_write_config_dword(pci, reg, data);
82 * skl_enable_miscbdcge - enable/dsiable CGCTL.MISCBDCGE bits
84 * @dev: device pointer
85 * @enable: enable/disable flag
87 static void skl_enable_miscbdcge(struct device *dev, bool enable)
89 struct pci_dev *pci = to_pci_dev(dev);
92 val = enable ? AZX_CGCTL_MISCBDCGE_MASK : 0;
94 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val);
98 * skl_clock_power_gating: Enable/Disable clock and power gating
100 * @dev: Device pointer
101 * @enable: Enable/Disable flag
103 static void skl_clock_power_gating(struct device *dev, bool enable)
105 struct pci_dev *pci = to_pci_dev(dev);
106 struct hdac_bus *bus = pci_get_drvdata(pci);
109 /* Update PDCGE bit of CGCTL register */
110 val = enable ? AZX_CGCTL_ADSPDCGE : 0;
111 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val);
113 /* Update L1SEN bit of EM2 register */
114 val = enable ? AZX_REG_VS_EM2_L1SEN : 0;
115 snd_hdac_chip_updatel(bus, VS_EM2, AZX_REG_VS_EM2_L1SEN, val);
117 /* Update ADSPPGD bit of PGCTL register */
118 val = enable ? 0 : AZX_PGCTL_ADSPPGD;
119 update_pci_dword(pci, AZX_PCIREG_PGCTL, AZX_PGCTL_ADSPPGD, val);
123 * While performing reset, controller may not come back properly causing
124 * issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
125 * (init chip) and then again set CGCTL.MISCBDCGE to 1
127 static int skl_init_chip(struct hdac_bus *bus, bool full_reset)
129 struct hdac_ext_link *hlink;
132 skl_enable_miscbdcge(bus->dev, false);
133 ret = snd_hdac_bus_init_chip(bus, full_reset);
135 /* Reset stream-to-link mapping */
136 list_for_each_entry(hlink, &bus->hlink_list, list)
137 writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
139 skl_enable_miscbdcge(bus->dev, true);
144 void skl_update_d0i3c(struct device *dev, bool enable)
146 struct pci_dev *pci = to_pci_dev(dev);
147 struct hdac_bus *bus = pci_get_drvdata(pci);
151 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
152 /* Do not write to D0I3C until command in progress bit is cleared */
153 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
155 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
158 /* Highly unlikely. But if it happens, flag error explicitly */
160 dev_err(bus->dev, "Before D0I3C update: D0I3C CIP timeout\n");
165 reg = reg | AZX_REG_VS_D0I3C_I3;
167 reg = reg & (~AZX_REG_VS_D0I3C_I3);
169 snd_hdac_chip_writeb(bus, VS_D0I3C, reg);
172 /* Wait for cmd in progress to be cleared before exiting the function */
173 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
174 while ((reg & AZX_REG_VS_D0I3C_CIP) && --timeout) {
176 reg = snd_hdac_chip_readb(bus, VS_D0I3C);
179 /* Highly unlikely. But if it happens, flag error explicitly */
181 dev_err(bus->dev, "After D0I3C update: D0I3C CIP timeout\n");
185 dev_dbg(bus->dev, "D0I3C register = 0x%x\n",
186 snd_hdac_chip_readb(bus, VS_D0I3C));
190 * skl_dum_set - set DUM bit in EM2 register
191 * @bus: HD-audio core bus
193 * Addresses incorrect position reporting for capture streams.
194 * Used on device power up.
196 static void skl_dum_set(struct hdac_bus *bus)
198 /* For the DUM bit to be set, CRST needs to be out of reset state */
199 if (!(snd_hdac_chip_readb(bus, GCTL) & AZX_GCTL_RESET)) {
200 skl_enable_miscbdcge(bus->dev, false);
201 snd_hdac_bus_exit_link_reset(bus);
202 skl_enable_miscbdcge(bus->dev, true);
205 snd_hdac_chip_updatel(bus, VS_EM2, AZX_VS_EM2_DUM, AZX_VS_EM2_DUM);
208 /* called from IRQ */
209 static void skl_stream_update(struct hdac_bus *bus, struct hdac_stream *hstr)
211 snd_pcm_period_elapsed(hstr->substream);
214 static irqreturn_t skl_interrupt(int irq, void *dev_id)
216 struct hdac_bus *bus = dev_id;
219 if (!pm_runtime_active(bus->dev))
222 spin_lock(&bus->reg_lock);
224 status = snd_hdac_chip_readl(bus, INTSTS);
225 if (status == 0 || status == 0xffffffff) {
226 spin_unlock(&bus->reg_lock);
231 status = snd_hdac_chip_readb(bus, RIRBSTS);
232 if (status & RIRB_INT_MASK) {
233 if (status & RIRB_INT_RESPONSE)
234 snd_hdac_bus_update_rirb(bus);
235 snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
238 spin_unlock(&bus->reg_lock);
240 return snd_hdac_chip_readl(bus, INTSTS) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
243 static irqreturn_t skl_threaded_handler(int irq, void *dev_id)
245 struct hdac_bus *bus = dev_id;
248 status = snd_hdac_chip_readl(bus, INTSTS);
250 snd_hdac_bus_handle_stream_irq(bus, status, skl_stream_update);
255 static int skl_acquire_irq(struct hdac_bus *bus, int do_disconnect)
257 struct skl_dev *skl = bus_to_skl(bus);
260 ret = request_threaded_irq(skl->pci->irq, skl_interrupt,
261 skl_threaded_handler,
263 KBUILD_MODNAME, bus);
266 "unable to grab IRQ %d, disabling device\n",
271 bus->irq = skl->pci->irq;
272 pci_intx(skl->pci, 1);
277 static int skl_suspend_late(struct device *dev)
279 struct pci_dev *pci = to_pci_dev(dev);
280 struct hdac_bus *bus = pci_get_drvdata(pci);
281 struct skl_dev *skl = bus_to_skl(bus);
283 return skl_suspend_late_dsp(skl);
287 static int _skl_suspend(struct hdac_bus *bus)
289 struct skl_dev *skl = bus_to_skl(bus);
290 struct pci_dev *pci = to_pci_dev(bus->dev);
293 snd_hdac_ext_bus_link_power_down_all(bus);
295 ret = skl_suspend_dsp(skl);
299 snd_hdac_bus_stop_chip(bus);
300 update_pci_dword(pci, AZX_PCIREG_PGCTL,
301 AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
302 skl_enable_miscbdcge(bus->dev, false);
303 snd_hdac_bus_enter_link_reset(bus);
304 skl_enable_miscbdcge(bus->dev, true);
305 skl_cleanup_resources(skl);
310 static int _skl_resume(struct hdac_bus *bus)
312 struct skl_dev *skl = bus_to_skl(bus);
316 skl_init_chip(bus, true);
318 return skl_resume_dsp(skl);
322 #ifdef CONFIG_PM_SLEEP
326 static int skl_suspend(struct device *dev)
328 struct pci_dev *pci = to_pci_dev(dev);
329 struct hdac_bus *bus = pci_get_drvdata(pci);
330 struct skl_dev *skl = bus_to_skl(bus);
334 * Do not suspend if streams which are marked ignore suspend are
335 * running, we need to save the state for these and continue
337 if (skl->supend_active) {
338 /* turn off the links and stop the CORB/RIRB DMA if it is On */
339 snd_hdac_ext_bus_link_power_down_all(bus);
341 if (bus->cmd_dma_state)
342 snd_hdac_bus_stop_cmd_io(bus);
344 enable_irq_wake(bus->irq);
347 ret = _skl_suspend(bus);
350 skl->fw_loaded = false;
356 static int skl_resume(struct device *dev)
358 struct pci_dev *pci = to_pci_dev(dev);
359 struct hdac_bus *bus = pci_get_drvdata(pci);
360 struct skl_dev *skl = bus_to_skl(bus);
361 struct hdac_ext_link *hlink = NULL;
365 * resume only when we are not in suspend active, otherwise need to
368 if (skl->supend_active) {
369 pci_restore_state(pci);
370 snd_hdac_ext_bus_link_power_up_all(bus);
371 disable_irq_wake(bus->irq);
373 * turn On the links which are On before active suspend
374 * and start the CORB/RIRB DMA if On before
377 list_for_each_entry(hlink, &bus->hlink_list, list) {
378 if (hlink->ref_count)
379 snd_hdac_ext_bus_link_power_up(hlink);
383 if (bus->cmd_dma_state)
384 snd_hdac_bus_init_cmd_io(bus);
386 ret = _skl_resume(bus);
388 /* turn off the links which are off before suspend */
389 list_for_each_entry(hlink, &bus->hlink_list, list) {
390 if (!hlink->ref_count)
391 snd_hdac_ext_bus_link_power_down(hlink);
394 if (!bus->cmd_dma_state)
395 snd_hdac_bus_stop_cmd_io(bus);
400 #endif /* CONFIG_PM_SLEEP */
403 static int skl_runtime_suspend(struct device *dev)
405 struct pci_dev *pci = to_pci_dev(dev);
406 struct hdac_bus *bus = pci_get_drvdata(pci);
408 dev_dbg(bus->dev, "in %s\n", __func__);
410 return _skl_suspend(bus);
413 static int skl_runtime_resume(struct device *dev)
415 struct pci_dev *pci = to_pci_dev(dev);
416 struct hdac_bus *bus = pci_get_drvdata(pci);
418 dev_dbg(bus->dev, "in %s\n", __func__);
420 return _skl_resume(bus);
422 #endif /* CONFIG_PM */
424 static const struct dev_pm_ops skl_pm = {
425 SET_SYSTEM_SLEEP_PM_OPS(skl_suspend, skl_resume)
426 SET_RUNTIME_PM_OPS(skl_runtime_suspend, skl_runtime_resume, NULL)
427 .suspend_late = skl_suspend_late,
433 static int skl_free(struct hdac_bus *bus)
435 struct skl_dev *skl = bus_to_skl(bus);
437 skl->init_done = 0; /* to be sure */
439 snd_hdac_ext_stop_streams(bus);
442 free_irq(bus->irq, (void *)bus);
443 snd_hdac_bus_free_stream_pages(bus);
444 snd_hdac_stream_free_all(bus);
445 snd_hdac_link_free_all(bus);
448 iounmap(bus->remap_addr);
450 pci_release_regions(skl->pci);
451 pci_disable_device(skl->pci);
453 snd_hdac_ext_bus_exit(bus);
455 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
456 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
457 snd_hdac_i915_exit(bus);
464 * For each ssp there are 3 clocks (mclk/sclk/sclkfs).
465 * e.g. for ssp0, clocks will be named as
466 * "ssp0_mclk", "ssp0_sclk", "ssp0_sclkfs"
467 * So for skl+, there are 6 ssps, so 18 clocks will be created.
469 static struct skl_ssp_clk skl_ssp_clks[] = {
470 {.name = "ssp0_mclk"}, {.name = "ssp1_mclk"}, {.name = "ssp2_mclk"},
471 {.name = "ssp3_mclk"}, {.name = "ssp4_mclk"}, {.name = "ssp5_mclk"},
472 {.name = "ssp0_sclk"}, {.name = "ssp1_sclk"}, {.name = "ssp2_sclk"},
473 {.name = "ssp3_sclk"}, {.name = "ssp4_sclk"}, {.name = "ssp5_sclk"},
474 {.name = "ssp0_sclkfs"}, {.name = "ssp1_sclkfs"},
475 {.name = "ssp2_sclkfs"},
476 {.name = "ssp3_sclkfs"}, {.name = "ssp4_sclkfs"},
477 {.name = "ssp5_sclkfs"},
480 static struct snd_soc_acpi_mach *skl_find_hda_machine(struct skl_dev *skl,
481 struct snd_soc_acpi_mach *machines)
483 struct hdac_bus *bus = skl_to_bus(skl);
484 struct snd_soc_acpi_mach *mach;
486 /* check if we have any codecs detected on bus */
487 if (bus->codec_mask == 0)
490 /* point to common table */
491 mach = snd_soc_acpi_intel_hda_machines;
493 /* all entries in the machine table use the same firmware */
494 mach->fw_filename = machines->fw_filename;
499 static int skl_find_machine(struct skl_dev *skl, void *driver_data)
501 struct hdac_bus *bus = skl_to_bus(skl);
502 struct snd_soc_acpi_mach *mach = driver_data;
503 struct skl_machine_pdata *pdata;
505 mach = snd_soc_acpi_find_machine(mach);
507 dev_dbg(bus->dev, "No matching I2S machine driver found\n");
508 mach = skl_find_hda_machine(skl, driver_data);
510 dev_err(bus->dev, "No matching machine driver found\n");
516 skl->fw_name = mach->fw_filename;
520 skl->use_tplg_pcm = pdata->use_tplg_pcm;
521 mach->mach_params.dmic_num =
522 intel_nhlt_get_dmic_geo(&skl->pci->dev,
529 static int skl_machine_device_register(struct skl_dev *skl)
531 struct snd_soc_acpi_mach *mach = skl->mach;
532 struct hdac_bus *bus = skl_to_bus(skl);
533 struct platform_device *pdev;
536 pdev = platform_device_alloc(mach->drv_name, -1);
538 dev_err(bus->dev, "platform device alloc failed\n");
542 mach->mach_params.platform = dev_name(bus->dev);
543 mach->mach_params.codec_mask = bus->codec_mask;
545 ret = platform_device_add_data(pdev, (const void *)mach, sizeof(*mach));
547 dev_err(bus->dev, "failed to add machine device platform data\n");
548 platform_device_put(pdev);
552 ret = platform_device_add(pdev);
554 dev_err(bus->dev, "failed to add machine device\n");
555 platform_device_put(pdev);
565 static void skl_machine_device_unregister(struct skl_dev *skl)
568 platform_device_unregister(skl->i2s_dev);
571 static int skl_dmic_device_register(struct skl_dev *skl)
573 struct hdac_bus *bus = skl_to_bus(skl);
574 struct platform_device *pdev;
577 /* SKL has one dmic port, so allocate dmic device for this */
578 pdev = platform_device_alloc("dmic-codec", -1);
580 dev_err(bus->dev, "failed to allocate dmic device\n");
584 ret = platform_device_add(pdev);
586 dev_err(bus->dev, "failed to add dmic device: %d\n", ret);
587 platform_device_put(pdev);
590 skl->dmic_dev = pdev;
595 static void skl_dmic_device_unregister(struct skl_dev *skl)
598 platform_device_unregister(skl->dmic_dev);
601 static struct skl_clk_parent_src skl_clk_src[] = {
602 { .clk_id = SKL_XTAL, .name = "xtal" },
603 { .clk_id = SKL_CARDINAL, .name = "cardinal", .rate = 24576000 },
604 { .clk_id = SKL_PLL, .name = "pll", .rate = 96000000 },
607 struct skl_clk_parent_src *skl_get_parent_clk(u8 clk_id)
611 for (i = 0; i < ARRAY_SIZE(skl_clk_src); i++) {
612 if (skl_clk_src[i].clk_id == clk_id)
613 return &skl_clk_src[i];
619 static void init_skl_xtal_rate(int pci_id)
624 skl_clk_src[0].rate = 24000000;
628 skl_clk_src[0].rate = 19200000;
633 static int skl_clock_device_register(struct skl_dev *skl)
635 struct platform_device_info pdevinfo = {NULL};
636 struct skl_clk_pdata *clk_pdata;
638 clk_pdata = devm_kzalloc(&skl->pci->dev, sizeof(*clk_pdata),
643 init_skl_xtal_rate(skl->pci->device);
645 clk_pdata->parent_clks = skl_clk_src;
646 clk_pdata->ssp_clks = skl_ssp_clks;
647 clk_pdata->num_clks = ARRAY_SIZE(skl_ssp_clks);
649 /* Query NHLT to fill the rates and parent */
650 skl_get_clks(skl, clk_pdata->ssp_clks);
651 clk_pdata->pvt_data = skl;
653 /* Register Platform device */
654 pdevinfo.parent = &skl->pci->dev;
656 pdevinfo.name = "skl-ssp-clk";
657 pdevinfo.data = clk_pdata;
658 pdevinfo.size_data = sizeof(*clk_pdata);
659 skl->clk_dev = platform_device_register_full(&pdevinfo);
660 return PTR_ERR_OR_ZERO(skl->clk_dev);
663 static void skl_clock_device_unregister(struct skl_dev *skl)
666 platform_device_unregister(skl->clk_dev);
669 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
671 #define IDISP_INTEL_VENDOR_ID 0x80860000
674 * load the legacy codec driver
676 static void load_codec_module(struct hda_codec *codec)
679 char modalias[MODULE_NAME_LEN];
680 const char *mod = NULL;
682 snd_hdac_codec_modalias(&codec->core, modalias, sizeof(modalias));
684 dev_dbg(&codec->core.dev, "loading %s codec module\n", mod);
689 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
692 * Probe the given codec address
694 static int probe_codec(struct hdac_bus *bus, int addr)
696 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
697 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
698 unsigned int res = -1;
699 struct skl_dev *skl = bus_to_skl(bus);
700 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
701 struct hdac_hda_priv *hda_codec;
704 struct hdac_device *hdev;
706 mutex_lock(&bus->cmd_mutex);
707 snd_hdac_bus_send_cmd(bus, cmd);
708 snd_hdac_bus_get_response(bus, addr, &res);
709 mutex_unlock(&bus->cmd_mutex);
712 dev_dbg(bus->dev, "codec #%d probed OK: %x\n", addr, res);
714 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
715 hda_codec = devm_kzalloc(&skl->pci->dev, sizeof(*hda_codec),
720 hda_codec->codec.bus = skl_to_hbus(skl);
721 hdev = &hda_codec->codec.core;
723 err = snd_hdac_ext_bus_device_init(bus, addr, hdev);
727 /* use legacy bus only for HDA codecs, idisp uses ext bus */
728 if ((res & 0xFFFF0000) != IDISP_INTEL_VENDOR_ID) {
729 hdev->type = HDA_DEV_LEGACY;
730 load_codec_module(&hda_codec->codec);
734 hdev = devm_kzalloc(&skl->pci->dev, sizeof(*hdev), GFP_KERNEL);
738 return snd_hdac_ext_bus_device_init(bus, addr, hdev);
739 #endif /* CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC */
742 /* Codec initialization */
743 static void skl_codec_create(struct hdac_bus *bus)
747 max_slots = HDA_MAX_CODECS;
749 /* First try to probe all given codec slots */
750 for (c = 0; c < max_slots; c++) {
751 if ((bus->codec_mask & (1 << c))) {
752 if (probe_codec(bus, c) < 0) {
754 * Some BIOSen give you wrong codec addresses
758 "Codec #%d probe error; disabling it...\n", c);
759 bus->codec_mask &= ~(1 << c);
761 * More badly, accessing to a non-existing
762 * codec often screws up the controller bus,
763 * and disturbs the further communications.
764 * Thus if an error occurs during probing,
765 * better to reset the controller bus to get
766 * back to the sanity state.
768 snd_hdac_bus_stop_chip(bus);
769 skl_init_chip(bus, true);
775 static const struct hdac_bus_ops bus_core_ops = {
776 .command = snd_hdac_bus_send_cmd,
777 .get_response = snd_hdac_bus_get_response,
780 static int skl_i915_init(struct hdac_bus *bus)
785 * The HDMI codec is in GPU so we need to ensure that it is powered
786 * up and ready for probe
788 err = snd_hdac_i915_init(bus);
792 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, true);
797 static void skl_probe_work(struct work_struct *work)
799 struct skl_dev *skl = container_of(work, struct skl_dev, probe_work);
800 struct hdac_bus *bus = skl_to_bus(skl);
801 struct hdac_ext_link *hlink = NULL;
804 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI)) {
805 err = skl_i915_init(bus);
810 err = skl_init_chip(bus, true);
812 dev_err(bus->dev, "Init chip failed with err: %d\n", err);
816 /* codec detection */
817 if (!bus->codec_mask)
818 dev_info(bus->dev, "no hda codecs found!\n");
820 /* create codec instances */
821 skl_codec_create(bus);
823 /* register platform dai and controls */
824 err = skl_platform_register(bus->dev);
826 dev_err(bus->dev, "platform register failed: %d\n", err);
830 err = skl_machine_device_register(skl);
832 dev_err(bus->dev, "machine register failed: %d\n", err);
837 * we are done probing so decrement link counts
839 list_for_each_entry(hlink, &bus->hlink_list, list)
840 snd_hdac_ext_bus_link_put(bus, hlink);
842 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
843 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
846 pm_runtime_put_noidle(bus->dev);
847 pm_runtime_allow(bus->dev);
853 if (IS_ENABLED(CONFIG_SND_SOC_HDAC_HDMI))
854 snd_hdac_display_power(bus, HDA_CODEC_IDX_CONTROLLER, false);
860 static int skl_create(struct pci_dev *pci,
861 struct skl_dev **rskl)
863 struct hdac_ext_bus_ops *ext_ops = NULL;
865 struct hdac_bus *bus;
866 struct hda_bus *hbus;
871 err = pci_enable_device(pci);
875 skl = devm_kzalloc(&pci->dev, sizeof(*skl), GFP_KERNEL);
877 pci_disable_device(pci);
881 hbus = skl_to_hbus(skl);
882 bus = skl_to_bus(skl);
884 INIT_LIST_HEAD(&skl->ppl_list);
885 INIT_LIST_HEAD(&skl->bind_list);
887 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
888 ext_ops = snd_soc_hdac_hda_get_ops();
890 snd_hdac_ext_bus_init(bus, &pci->dev, &bus_core_ops, ext_ops);
893 INIT_WORK(&skl->probe_work, skl_probe_work);
894 bus->bdl_pos_adj = 0;
896 mutex_init(&hbus->prepare_mutex);
898 hbus->mixer_assigned = -1;
899 hbus->modelname = "sklbus";
906 static int skl_first_init(struct hdac_bus *bus)
908 struct skl_dev *skl = bus_to_skl(bus);
909 struct pci_dev *pci = skl->pci;
912 int cp_streams, pb_streams, start_idx;
914 err = pci_request_regions(pci, "Skylake HD audio");
918 bus->addr = pci_resource_start(pci, 0);
919 bus->remap_addr = pci_ioremap_bar(pci, 0);
920 if (bus->remap_addr == NULL) {
921 dev_err(bus->dev, "ioremap error\n");
925 snd_hdac_bus_reset_link(bus, true);
927 snd_hdac_bus_parse_capabilities(bus);
929 /* check if PPCAP exists */
931 dev_err(bus->dev, "bus ppcap not set, HDaudio or DSP not present?\n");
935 if (skl_acquire_irq(bus, 0) < 0)
939 synchronize_irq(bus->irq);
941 gcap = snd_hdac_chip_readw(bus, GCAP);
942 dev_dbg(bus->dev, "chipset global capabilities = 0x%x\n", gcap);
944 /* read number of streams from GCAP register */
945 cp_streams = (gcap >> 8) & 0x0f;
946 pb_streams = (gcap >> 12) & 0x0f;
948 if (!pb_streams && !cp_streams) {
949 dev_err(bus->dev, "no streams found in GCAP definitions?\n");
953 bus->num_streams = cp_streams + pb_streams;
955 /* allow 64bit DMA address if supported by H/W */
956 if (!dma_set_mask(bus->dev, DMA_BIT_MASK(64))) {
957 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(64));
959 dma_set_mask(bus->dev, DMA_BIT_MASK(32));
960 dma_set_coherent_mask(bus->dev, DMA_BIT_MASK(32));
963 /* initialize streams */
964 snd_hdac_ext_stream_init_all
965 (bus, 0, cp_streams, SNDRV_PCM_STREAM_CAPTURE);
966 start_idx = cp_streams;
967 snd_hdac_ext_stream_init_all
968 (bus, start_idx, pb_streams, SNDRV_PCM_STREAM_PLAYBACK);
970 err = snd_hdac_bus_alloc_stream_pages(bus);
974 /* initialize chip */
978 return skl_init_chip(bus, true);
981 static int skl_probe(struct pci_dev *pci,
982 const struct pci_device_id *pci_id)
985 struct hdac_bus *bus = NULL;
988 switch (skl_pci_binding) {
989 case SND_SKL_PCI_BIND_AUTO:
991 * detect DSP by checking class/subclass/prog-id information
992 * class=04 subclass 03 prog-if 00: no DSP, use legacy driver
993 * class=04 subclass 01 prog-if 00: DSP is present
994 * (and may be required e.g. for DMIC or SSP support)
995 * class=04 subclass 03 prog-if 80: use DSP or legacy mode
997 if (pci->class == 0x040300) {
998 dev_info(&pci->dev, "The DSP is not enabled on this platform, aborting probe\n");
1001 if (pci->class != 0x040100 && pci->class != 0x040380) {
1002 dev_err(&pci->dev, "Unknown PCI class/subclass/prog-if information (0x%06x) found, aborting probe\n", pci->class);
1005 dev_info(&pci->dev, "DSP detected with PCI class/subclass/prog-if info 0x%06x\n", pci->class);
1007 case SND_SKL_PCI_BIND_LEGACY:
1008 dev_info(&pci->dev, "Module parameter forced binding with HDaudio legacy, aborting probe\n");
1010 case SND_SKL_PCI_BIND_ASOC:
1011 dev_info(&pci->dev, "Module parameter forced binding with SKL driver, bypassed detection logic\n");
1014 dev_err(&pci->dev, "invalid value for skl_pci_binding module parameter, ignored\n");
1018 /* we use ext core ops, so provide NULL for ops here */
1019 err = skl_create(pci, &skl);
1023 bus = skl_to_bus(skl);
1025 err = skl_first_init(bus);
1027 dev_err(bus->dev, "skl_first_init failed with err: %d\n", err);
1031 skl->pci_id = pci->device;
1033 device_disable_async_suspend(bus->dev);
1035 skl->nhlt = intel_nhlt_init(bus->dev);
1037 if (skl->nhlt == NULL) {
1038 #if !IS_ENABLED(CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC)
1039 dev_err(bus->dev, "no nhlt info found\n");
1043 dev_warn(bus->dev, "no nhlt info found, continuing to try to enable HDaudio codec\n");
1047 err = skl_nhlt_create_sysfs(skl);
1049 dev_err(bus->dev, "skl_nhlt_create_sysfs failed with err: %d\n", err);
1053 skl_nhlt_update_topology_bin(skl);
1055 /* create device for dsp clk */
1056 err = skl_clock_device_register(skl);
1058 dev_err(bus->dev, "skl_clock_device_register failed with err: %d\n", err);
1063 pci_set_drvdata(skl->pci, bus);
1066 err = skl_find_machine(skl, (void *)pci_id->driver_data);
1068 dev_err(bus->dev, "skl_find_machine failed with err: %d\n", err);
1072 err = skl_init_dsp(skl);
1074 dev_dbg(bus->dev, "error failed to register dsp\n");
1077 skl->enable_miscbdcge = skl_enable_miscbdcge;
1078 skl->clock_power_gating = skl_clock_power_gating;
1081 snd_hdac_ext_bus_get_ml_capabilities(bus);
1083 snd_hdac_bus_stop_chip(bus);
1085 /* create device for soc dmic */
1086 err = skl_dmic_device_register(skl);
1088 dev_err(bus->dev, "skl_dmic_device_register failed with err: %d\n", err);
1092 schedule_work(&skl->probe_work);
1099 skl_clock_device_unregister(skl);
1101 intel_nhlt_free(skl->nhlt);
1108 static void skl_shutdown(struct pci_dev *pci)
1110 struct hdac_bus *bus = pci_get_drvdata(pci);
1111 struct hdac_stream *s;
1112 struct hdac_ext_stream *stream;
1113 struct skl_dev *skl;
1118 skl = bus_to_skl(bus);
1120 if (!skl->init_done)
1123 snd_hdac_ext_stop_streams(bus);
1124 list_for_each_entry(s, &bus->stream_list, list) {
1125 stream = stream_to_hdac_ext_stream(s);
1126 snd_hdac_ext_stream_decouple(bus, stream, false);
1129 snd_hdac_bus_stop_chip(bus);
1132 static void skl_remove(struct pci_dev *pci)
1134 struct hdac_bus *bus = pci_get_drvdata(pci);
1135 struct skl_dev *skl = bus_to_skl(bus);
1137 cancel_work_sync(&skl->probe_work);
1139 pm_runtime_get_noresume(&pci->dev);
1141 /* codec removal, invoke bus_device_remove */
1142 snd_hdac_ext_bus_device_remove(bus);
1144 skl_platform_unregister(&pci->dev);
1146 skl_machine_device_unregister(skl);
1147 skl_dmic_device_unregister(skl);
1148 skl_clock_device_unregister(skl);
1149 skl_nhlt_remove_sysfs(skl);
1150 intel_nhlt_free(skl->nhlt);
1152 dev_set_drvdata(&pci->dev, NULL);
1156 static const struct pci_device_id skl_ids[] = {
1157 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_SKL)
1158 /* Sunrise Point-LP */
1159 { PCI_DEVICE(0x8086, 0x9d70),
1160 .driver_data = (unsigned long)&snd_soc_acpi_intel_skl_machines},
1162 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_APL)
1164 { PCI_DEVICE(0x8086, 0x5a98),
1165 .driver_data = (unsigned long)&snd_soc_acpi_intel_bxt_machines},
1167 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_KBL)
1169 { PCI_DEVICE(0x8086, 0x9D71),
1170 .driver_data = (unsigned long)&snd_soc_acpi_intel_kbl_machines},
1172 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_GLK)
1174 { PCI_DEVICE(0x8086, 0x3198),
1175 .driver_data = (unsigned long)&snd_soc_acpi_intel_glk_machines},
1177 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CNL)
1179 { PCI_DEVICE(0x8086, 0x9dc8),
1180 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1182 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CFL)
1184 { PCI_DEVICE(0x8086, 0xa348),
1185 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1187 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_LP)
1189 { PCI_DEVICE(0x8086, 0x02c8),
1190 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1192 #if IS_ENABLED(CONFIG_SND_SOC_INTEL_CML_H)
1194 { PCI_DEVICE(0x8086, 0x06c8),
1195 .driver_data = (unsigned long)&snd_soc_acpi_intel_cnl_machines},
1199 MODULE_DEVICE_TABLE(pci, skl_ids);
1201 /* pci_driver definition */
1202 static struct pci_driver skl_driver = {
1203 .name = KBUILD_MODNAME,
1204 .id_table = skl_ids,
1206 .remove = skl_remove,
1207 .shutdown = skl_shutdown,
1212 module_pci_driver(skl_driver);
1214 MODULE_LICENSE("GPL v2");
1215 MODULE_DESCRIPTION("Intel Skylake ASoC HDA driver");