2 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
4 * Copyright (C) 2014-2015 Intel Corp
5 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
22 #include <linux/pci.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/delay.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
28 #include "skl-topology.h"
29 #include "skl-sst-dsp.h"
30 #include "skl-sst-ipc.h"
36 static const struct snd_pcm_hardware azx_pcm_hw = {
37 .info = (SNDRV_PCM_INFO_MMAP |
38 SNDRV_PCM_INFO_INTERLEAVED |
39 SNDRV_PCM_INFO_BLOCK_TRANSFER |
40 SNDRV_PCM_INFO_MMAP_VALID |
41 SNDRV_PCM_INFO_PAUSE |
42 SNDRV_PCM_INFO_RESUME |
43 SNDRV_PCM_INFO_SYNC_START |
44 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
45 SNDRV_PCM_INFO_HAS_LINK_ATIME |
46 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
47 .formats = SNDRV_PCM_FMTBIT_S16_LE |
48 SNDRV_PCM_FMTBIT_S32_LE |
49 SNDRV_PCM_FMTBIT_S24_LE,
50 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
56 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
57 .period_bytes_min = 128,
58 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
60 .periods_max = AZX_MAX_FRAG,
65 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
67 return substream->runtime->private_data;
70 static struct hdac_ext_bus *get_bus_ctx(struct snd_pcm_substream *substream)
72 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
73 struct hdac_stream *hstream = hdac_stream(stream);
74 struct hdac_bus *bus = hstream->bus;
76 return hbus_to_ebus(bus);
79 static int skl_substream_alloc_pages(struct hdac_ext_bus *ebus,
80 struct snd_pcm_substream *substream,
83 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
85 hdac_stream(stream)->bufsize = 0;
86 hdac_stream(stream)->period_bytes = 0;
87 hdac_stream(stream)->format_val = 0;
89 return snd_pcm_lib_malloc_pages(substream, size);
92 static int skl_substream_free_pages(struct hdac_bus *bus,
93 struct snd_pcm_substream *substream)
95 return snd_pcm_lib_free_pages(substream);
98 static void skl_set_pcm_constrains(struct hdac_ext_bus *ebus,
99 struct snd_pcm_runtime *runtime)
101 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
103 /* avoid wrap-around with wall-clock */
104 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
108 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_ext_bus *ebus)
110 if ((ebus_to_hbus(ebus))->ppcap)
111 return HDAC_EXT_STREAM_TYPE_HOST;
113 return HDAC_EXT_STREAM_TYPE_COUPLED;
117 * check if the stream opened is marked as ignore_suspend by machine, if so
118 * then enable suspend_active refcount
120 * The count supend_active does not need lock as it is used in open/close
121 * and suspend context
123 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
124 struct snd_soc_dai *dai, bool enable)
126 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
127 struct snd_soc_dapm_widget *w;
128 struct skl *skl = ebus_to_skl(ebus);
130 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
131 w = dai->playback_widget;
133 w = dai->capture_widget;
135 if (w->ignore_suspend && enable)
136 skl->supend_active++;
137 else if (w->ignore_suspend && !enable)
138 skl->supend_active--;
141 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
143 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
144 struct hdac_bus *bus = ebus_to_hbus(ebus);
145 unsigned int format_val;
146 struct hdac_stream *hstream;
147 struct hdac_ext_stream *stream;
150 hstream = snd_hdac_get_stream(bus, params->stream,
151 params->host_dma_id + 1);
155 stream = stream_to_hdac_ext_stream(hstream);
156 snd_hdac_ext_stream_decouple(ebus, stream, true);
158 format_val = snd_hdac_calc_stream_format(params->s_freq,
159 params->ch, params->format, params->host_bps, 0);
161 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
162 format_val, params->s_freq, params->ch, params->format);
164 snd_hdac_stream_reset(hdac_stream(stream));
165 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
169 err = snd_hdac_stream_setup(hdac_stream(stream));
173 hdac_stream(stream)->prepared = 1;
178 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
180 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
181 struct hdac_bus *bus = ebus_to_hbus(ebus);
182 unsigned int format_val;
183 struct hdac_stream *hstream;
184 struct hdac_ext_stream *stream;
185 struct hdac_ext_link *link;
187 hstream = snd_hdac_get_stream(bus, params->stream,
188 params->link_dma_id + 1);
192 stream = stream_to_hdac_ext_stream(hstream);
193 snd_hdac_ext_stream_decouple(ebus, stream, true);
194 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
195 params->format, params->link_bps, 0);
197 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
198 format_val, params->s_freq, params->ch, params->format);
200 snd_hdac_ext_link_stream_reset(stream);
202 snd_hdac_ext_link_stream_setup(stream, format_val);
204 list_for_each_entry(link, &ebus->hlink_list, list) {
205 if (link->index == params->link_index)
206 snd_hdac_ext_link_set_stream_id(link,
207 hstream->stream_tag);
210 stream->link_prepared = 1;
215 static int skl_pcm_open(struct snd_pcm_substream *substream,
216 struct snd_soc_dai *dai)
218 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
219 struct hdac_ext_stream *stream;
220 struct snd_pcm_runtime *runtime = substream->runtime;
221 struct skl_dma_params *dma_params;
222 struct skl *skl = get_skl_ctx(dai->dev);
223 struct skl_module_cfg *mconfig;
225 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
227 stream = snd_hdac_ext_stream_assign(ebus, substream,
228 skl_get_host_stream_type(ebus));
232 skl_set_pcm_constrains(ebus, runtime);
235 * disable WALLCLOCK timestamps for capture streams
236 * until we figure out how to handle digital inputs
238 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
239 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
240 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
243 runtime->private_data = stream;
245 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
249 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
250 snd_soc_dai_set_dma_data(dai, substream, dma_params);
252 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
253 dma_params->stream_tag);
254 skl_set_suspend_active(substream, dai, true);
255 snd_pcm_set_sync(substream);
257 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
261 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
266 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
267 struct snd_soc_dai *dai)
269 struct skl *skl = get_skl_ctx(dai->dev);
270 struct skl_module_cfg *mconfig;
272 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
274 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
276 /* In case of XRUN recovery, reset the FW pipe to clean state */
277 if (mconfig && (substream->runtime->status->state ==
278 SNDRV_PCM_STATE_XRUN))
279 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
284 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
285 struct snd_pcm_hw_params *params,
286 struct snd_soc_dai *dai)
288 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
289 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
290 struct snd_pcm_runtime *runtime = substream->runtime;
291 struct skl_pipe_params p_params = {0};
292 struct skl_module_cfg *m_cfg;
295 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
296 ret = skl_substream_alloc_pages(ebus, substream,
297 params_buffer_bytes(params));
301 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
302 runtime->rate, runtime->channels, runtime->format);
304 dma_id = hdac_stream(stream)->stream_tag - 1;
305 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
307 p_params.s_fmt = snd_pcm_format_width(params_format(params));
308 p_params.ch = params_channels(params);
309 p_params.s_freq = params_rate(params);
310 p_params.host_dma_id = dma_id;
311 p_params.stream = substream->stream;
312 p_params.format = params_format(params);
313 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
314 p_params.host_bps = dai->driver->playback.sig_bits;
316 p_params.host_bps = dai->driver->capture.sig_bits;
319 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
321 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
326 static void skl_pcm_close(struct snd_pcm_substream *substream,
327 struct snd_soc_dai *dai)
329 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
330 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
331 struct skl_dma_params *dma_params = NULL;
332 struct skl *skl = ebus_to_skl(ebus);
333 struct skl_module_cfg *mconfig;
335 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
337 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(ebus));
339 dma_params = snd_soc_dai_get_dma_data(dai, substream);
341 * now we should set this to NULL as we are freeing by the
344 snd_soc_dai_set_dma_data(dai, substream, NULL);
345 skl_set_suspend_active(substream, dai, false);
348 * check if close is for "Reference Pin" and set back the
349 * CGCTL.MISCBDCGE if disabled by driver
351 if (!strncmp(dai->name, "Reference Pin", 13) &&
352 skl->skl_sst->miscbdcg_disabled) {
353 skl->skl_sst->enable_miscbdcge(dai->dev, true);
354 skl->skl_sst->miscbdcg_disabled = false;
357 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
358 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
363 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
364 struct snd_soc_dai *dai)
366 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
367 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
369 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
371 snd_hdac_stream_cleanup(hdac_stream(stream));
372 hdac_stream(stream)->prepared = 0;
374 return skl_substream_free_pages(ebus_to_hbus(ebus), substream);
377 static int skl_be_hw_params(struct snd_pcm_substream *substream,
378 struct snd_pcm_hw_params *params,
379 struct snd_soc_dai *dai)
381 struct skl_pipe_params p_params = {0};
383 p_params.s_fmt = snd_pcm_format_width(params_format(params));
384 p_params.ch = params_channels(params);
385 p_params.s_freq = params_rate(params);
386 p_params.stream = substream->stream;
388 return skl_tplg_be_update_params(dai, &p_params);
391 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
394 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
395 struct hdac_bus *bus = ebus_to_hbus(ebus);
396 struct hdac_ext_stream *stream;
398 unsigned long cookie;
399 struct hdac_stream *hstr;
401 stream = get_hdac_ext_stream(substream);
402 hstr = hdac_stream(stream);
408 case SNDRV_PCM_TRIGGER_START:
409 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
410 case SNDRV_PCM_TRIGGER_RESUME:
414 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
415 case SNDRV_PCM_TRIGGER_SUSPEND:
416 case SNDRV_PCM_TRIGGER_STOP:
424 spin_lock_irqsave(&bus->reg_lock, cookie);
427 snd_hdac_stream_start(hdac_stream(stream), true);
428 snd_hdac_stream_timecounter_init(hstr, 0);
430 snd_hdac_stream_stop(hdac_stream(stream));
433 spin_unlock_irqrestore(&bus->reg_lock, cookie);
438 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
439 struct snd_soc_dai *dai)
441 struct skl *skl = get_skl_ctx(dai->dev);
442 struct skl_sst *ctx = skl->skl_sst;
443 struct skl_module_cfg *mconfig;
444 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
445 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
446 struct snd_soc_dapm_widget *w;
449 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
453 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
454 w = dai->playback_widget;
456 w = dai->capture_widget;
459 case SNDRV_PCM_TRIGGER_RESUME:
460 if (!w->ignore_suspend) {
462 * enable DMA Resume enable bit for the stream, set the
463 * dpib & lpib position to resume before starting the
466 snd_hdac_ext_stream_drsm_enable(ebus, true,
467 hdac_stream(stream)->index);
468 snd_hdac_ext_stream_set_dpibr(ebus, stream,
470 snd_hdac_ext_stream_set_lpib(stream, stream->lpib);
473 case SNDRV_PCM_TRIGGER_START:
474 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
476 * Start HOST DMA and Start FE Pipe.This is to make sure that
477 * there are no underrun/overrun in the case when the FE
478 * pipeline is started but there is a delay in starting the
479 * DMA channel on the host.
481 ret = skl_decoupled_trigger(substream, cmd);
484 return skl_run_pipe(ctx, mconfig->pipe);
487 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
488 case SNDRV_PCM_TRIGGER_SUSPEND:
489 case SNDRV_PCM_TRIGGER_STOP:
491 * Stop FE Pipe first and stop DMA. This is to make sure that
492 * there are no underrun/overrun in the case if there is a delay
493 * between the two operations.
495 ret = skl_stop_pipe(ctx, mconfig->pipe);
499 ret = skl_decoupled_trigger(substream, cmd);
500 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
501 /* save the dpib and lpib positions */
502 stream->dpib = readl(ebus->bus.remap_addr +
503 AZX_REG_VS_SDXDPIB_XBASE +
504 (AZX_REG_VS_SDXDPIB_XINTERVAL *
505 hdac_stream(stream)->index));
507 stream->lpib = snd_hdac_stream_get_pos_lpib(
508 hdac_stream(stream));
509 snd_hdac_ext_stream_decouple(ebus, stream, false);
520 static int skl_link_hw_params(struct snd_pcm_substream *substream,
521 struct snd_pcm_hw_params *params,
522 struct snd_soc_dai *dai)
524 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
525 struct hdac_ext_stream *link_dev;
526 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
527 struct snd_soc_dai *codec_dai = rtd->codec_dai;
528 struct skl_pipe_params p_params = {0};
529 struct hdac_ext_link *link;
532 link_dev = snd_hdac_ext_stream_assign(ebus, substream,
533 HDAC_EXT_STREAM_TYPE_LINK);
537 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
539 link = snd_hdac_ext_bus_get_link(ebus, codec_dai->component->name);
543 stream_tag = hdac_stream(link_dev)->stream_tag;
545 /* set the stream tag in the codec dai dma params */
546 snd_soc_dai_set_tdm_slot(codec_dai, stream_tag, 0, 0, 0);
548 p_params.s_fmt = snd_pcm_format_width(params_format(params));
549 p_params.ch = params_channels(params);
550 p_params.s_freq = params_rate(params);
551 p_params.stream = substream->stream;
552 p_params.link_dma_id = stream_tag - 1;
553 p_params.link_index = link->index;
554 p_params.format = params_format(params);
556 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
557 p_params.link_bps = codec_dai->driver->playback.sig_bits;
559 p_params.link_bps = codec_dai->driver->capture.sig_bits;
561 return skl_tplg_be_update_params(dai, &p_params);
564 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
565 struct snd_soc_dai *dai)
567 struct skl *skl = get_skl_ctx(dai->dev);
568 struct skl_module_cfg *mconfig = NULL;
570 /* In case of XRUN recovery, reset the FW pipe to clean state */
571 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
572 if (mconfig && !mconfig->pipe->passthru &&
573 (substream->runtime->status->state == SNDRV_PCM_STATE_XRUN))
574 skl_reset_pipe(skl->skl_sst, mconfig->pipe);
579 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
580 int cmd, struct snd_soc_dai *dai)
582 struct hdac_ext_stream *link_dev =
583 snd_soc_dai_get_dma_data(dai, substream);
584 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
585 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
587 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
589 case SNDRV_PCM_TRIGGER_RESUME:
590 case SNDRV_PCM_TRIGGER_START:
591 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
592 snd_hdac_ext_link_stream_start(link_dev);
595 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
596 case SNDRV_PCM_TRIGGER_SUSPEND:
597 case SNDRV_PCM_TRIGGER_STOP:
598 snd_hdac_ext_link_stream_clear(link_dev);
599 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
600 snd_hdac_ext_stream_decouple(ebus, stream, false);
609 static int skl_link_hw_free(struct snd_pcm_substream *substream,
610 struct snd_soc_dai *dai)
612 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
613 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
614 struct hdac_ext_stream *link_dev =
615 snd_soc_dai_get_dma_data(dai, substream);
616 struct hdac_ext_link *link;
618 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
620 link_dev->link_prepared = 0;
622 link = snd_hdac_ext_bus_get_link(ebus, rtd->codec_dai->component->name);
626 snd_hdac_ext_link_clear_stream_id(link, hdac_stream(link_dev)->stream_tag);
627 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
631 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
632 .startup = skl_pcm_open,
633 .shutdown = skl_pcm_close,
634 .prepare = skl_pcm_prepare,
635 .hw_params = skl_pcm_hw_params,
636 .hw_free = skl_pcm_hw_free,
637 .trigger = skl_pcm_trigger,
640 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
641 .hw_params = skl_be_hw_params,
644 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
645 .hw_params = skl_be_hw_params,
648 static const struct snd_soc_dai_ops skl_link_dai_ops = {
649 .prepare = skl_link_pcm_prepare,
650 .hw_params = skl_link_hw_params,
651 .hw_free = skl_link_hw_free,
652 .trigger = skl_link_pcm_trigger,
655 static struct snd_soc_dai_driver skl_fe_dai[] = {
657 .name = "System Pin",
658 .ops = &skl_pcm_dai_ops,
660 .stream_name = "System Playback",
661 .channels_min = HDA_MONO,
662 .channels_max = HDA_STEREO,
663 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
664 .formats = SNDRV_PCM_FMTBIT_S16_LE |
665 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
669 .stream_name = "System Capture",
670 .channels_min = HDA_MONO,
671 .channels_max = HDA_STEREO,
672 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
673 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
678 .name = "System Pin2",
679 .ops = &skl_pcm_dai_ops,
681 .stream_name = "Headset Playback",
682 .channels_min = HDA_MONO,
683 .channels_max = HDA_STEREO,
684 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
686 .formats = SNDRV_PCM_FMTBIT_S16_LE |
687 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
691 .name = "Echoref Pin",
692 .ops = &skl_pcm_dai_ops,
694 .stream_name = "Echoreference Capture",
695 .channels_min = HDA_STEREO,
696 .channels_max = HDA_STEREO,
697 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
699 .formats = SNDRV_PCM_FMTBIT_S16_LE |
700 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
704 .name = "Reference Pin",
705 .ops = &skl_pcm_dai_ops,
707 .stream_name = "Reference Capture",
708 .channels_min = HDA_MONO,
709 .channels_max = HDA_QUAD,
710 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
711 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
716 .name = "Deepbuffer Pin",
717 .ops = &skl_pcm_dai_ops,
719 .stream_name = "Deepbuffer Playback",
720 .channels_min = HDA_STEREO,
721 .channels_max = HDA_STEREO,
722 .rates = SNDRV_PCM_RATE_48000,
723 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
728 .name = "LowLatency Pin",
729 .ops = &skl_pcm_dai_ops,
731 .stream_name = "Low Latency Playback",
732 .channels_min = HDA_STEREO,
733 .channels_max = HDA_STEREO,
734 .rates = SNDRV_PCM_RATE_48000,
735 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
741 .ops = &skl_pcm_dai_ops,
743 .stream_name = "DMIC Capture",
744 .channels_min = HDA_MONO,
745 .channels_max = HDA_QUAD,
746 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
747 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
753 .ops = &skl_pcm_dai_ops,
755 .stream_name = "HDMI1 Playback",
756 .channels_min = HDA_STEREO,
758 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
759 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
760 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
761 SNDRV_PCM_RATE_192000,
762 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
763 SNDRV_PCM_FMTBIT_S32_LE,
769 .ops = &skl_pcm_dai_ops,
771 .stream_name = "HDMI2 Playback",
772 .channels_min = HDA_STEREO,
774 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
775 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
776 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
777 SNDRV_PCM_RATE_192000,
778 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
779 SNDRV_PCM_FMTBIT_S32_LE,
785 .ops = &skl_pcm_dai_ops,
787 .stream_name = "HDMI3 Playback",
788 .channels_min = HDA_STEREO,
790 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
791 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
792 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
793 SNDRV_PCM_RATE_192000,
794 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
795 SNDRV_PCM_FMTBIT_S32_LE,
802 static struct snd_soc_dai_driver skl_platform_dai[] = {
805 .ops = &skl_be_ssp_dai_ops,
807 .stream_name = "ssp0 Tx",
808 .channels_min = HDA_STEREO,
809 .channels_max = HDA_STEREO,
810 .rates = SNDRV_PCM_RATE_48000,
811 .formats = SNDRV_PCM_FMTBIT_S16_LE,
814 .stream_name = "ssp0 Rx",
815 .channels_min = HDA_STEREO,
816 .channels_max = HDA_STEREO,
817 .rates = SNDRV_PCM_RATE_48000,
818 .formats = SNDRV_PCM_FMTBIT_S16_LE,
823 .ops = &skl_be_ssp_dai_ops,
825 .stream_name = "ssp1 Tx",
826 .channels_min = HDA_STEREO,
827 .channels_max = HDA_STEREO,
828 .rates = SNDRV_PCM_RATE_48000,
829 .formats = SNDRV_PCM_FMTBIT_S16_LE,
832 .stream_name = "ssp1 Rx",
833 .channels_min = HDA_STEREO,
834 .channels_max = HDA_STEREO,
835 .rates = SNDRV_PCM_RATE_48000,
836 .formats = SNDRV_PCM_FMTBIT_S16_LE,
841 .ops = &skl_be_ssp_dai_ops,
843 .stream_name = "ssp2 Tx",
844 .channels_min = HDA_STEREO,
845 .channels_max = HDA_STEREO,
846 .rates = SNDRV_PCM_RATE_48000,
847 .formats = SNDRV_PCM_FMTBIT_S16_LE,
850 .stream_name = "ssp2 Rx",
851 .channels_min = HDA_STEREO,
852 .channels_max = HDA_STEREO,
853 .rates = SNDRV_PCM_RATE_48000,
854 .formats = SNDRV_PCM_FMTBIT_S16_LE,
859 .ops = &skl_be_ssp_dai_ops,
861 .stream_name = "ssp3 Tx",
862 .channels_min = HDA_STEREO,
863 .channels_max = HDA_STEREO,
864 .rates = SNDRV_PCM_RATE_48000,
865 .formats = SNDRV_PCM_FMTBIT_S16_LE,
868 .stream_name = "ssp3 Rx",
869 .channels_min = HDA_STEREO,
870 .channels_max = HDA_STEREO,
871 .rates = SNDRV_PCM_RATE_48000,
872 .formats = SNDRV_PCM_FMTBIT_S16_LE,
877 .ops = &skl_be_ssp_dai_ops,
879 .stream_name = "ssp4 Tx",
880 .channels_min = HDA_STEREO,
881 .channels_max = HDA_STEREO,
882 .rates = SNDRV_PCM_RATE_48000,
883 .formats = SNDRV_PCM_FMTBIT_S16_LE,
886 .stream_name = "ssp4 Rx",
887 .channels_min = HDA_STEREO,
888 .channels_max = HDA_STEREO,
889 .rates = SNDRV_PCM_RATE_48000,
890 .formats = SNDRV_PCM_FMTBIT_S16_LE,
895 .ops = &skl_be_ssp_dai_ops,
897 .stream_name = "ssp5 Tx",
898 .channels_min = HDA_STEREO,
899 .channels_max = HDA_STEREO,
900 .rates = SNDRV_PCM_RATE_48000,
901 .formats = SNDRV_PCM_FMTBIT_S16_LE,
904 .stream_name = "ssp5 Rx",
905 .channels_min = HDA_STEREO,
906 .channels_max = HDA_STEREO,
907 .rates = SNDRV_PCM_RATE_48000,
908 .formats = SNDRV_PCM_FMTBIT_S16_LE,
912 .name = "iDisp1 Pin",
913 .ops = &skl_link_dai_ops,
915 .stream_name = "iDisp1 Tx",
916 .channels_min = HDA_STEREO,
918 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
919 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
920 SNDRV_PCM_FMTBIT_S24_LE,
924 .name = "iDisp2 Pin",
925 .ops = &skl_link_dai_ops,
927 .stream_name = "iDisp2 Tx",
928 .channels_min = HDA_STEREO,
930 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
931 SNDRV_PCM_RATE_48000,
932 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
933 SNDRV_PCM_FMTBIT_S24_LE,
937 .name = "iDisp3 Pin",
938 .ops = &skl_link_dai_ops,
940 .stream_name = "iDisp3 Tx",
941 .channels_min = HDA_STEREO,
943 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
944 SNDRV_PCM_RATE_48000,
945 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
946 SNDRV_PCM_FMTBIT_S24_LE,
950 .name = "DMIC01 Pin",
951 .ops = &skl_dmic_dai_ops,
953 .stream_name = "DMIC01 Rx",
954 .channels_min = HDA_MONO,
955 .channels_max = HDA_QUAD,
956 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
957 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
961 .name = "HD-Codec Pin",
962 .ops = &skl_link_dai_ops,
964 .stream_name = "HD-Codec Tx",
965 .channels_min = HDA_STEREO,
966 .channels_max = HDA_STEREO,
967 .rates = SNDRV_PCM_RATE_48000,
968 .formats = SNDRV_PCM_FMTBIT_S16_LE,
971 .stream_name = "HD-Codec Rx",
972 .channels_min = HDA_STEREO,
973 .channels_max = HDA_STEREO,
974 .rates = SNDRV_PCM_RATE_48000,
975 .formats = SNDRV_PCM_FMTBIT_S16_LE,
980 int skl_dai_load(struct snd_soc_component *cmp,
981 struct snd_soc_dai_driver *pcm_dai)
983 pcm_dai->ops = &skl_pcm_dai_ops;
988 static int skl_platform_open(struct snd_pcm_substream *substream)
990 struct snd_soc_pcm_runtime *rtd = substream->private_data;
991 struct snd_soc_dai_link *dai_link = rtd->dai_link;
993 dev_dbg(rtd->cpu_dai->dev, "In %s:%s\n", __func__,
994 dai_link->cpu_dai_name);
996 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1001 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1004 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1005 struct hdac_bus *bus = ebus_to_hbus(ebus);
1006 struct hdac_ext_stream *stream;
1007 struct snd_pcm_substream *s;
1010 unsigned long cookie;
1011 struct hdac_stream *hstr;
1013 stream = get_hdac_ext_stream(substream);
1014 hstr = hdac_stream(stream);
1016 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1018 if (!hstr->prepared)
1022 case SNDRV_PCM_TRIGGER_START:
1023 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1024 case SNDRV_PCM_TRIGGER_RESUME:
1028 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1029 case SNDRV_PCM_TRIGGER_SUSPEND:
1030 case SNDRV_PCM_TRIGGER_STOP:
1038 snd_pcm_group_for_each_entry(s, substream) {
1039 if (s->pcm->card != substream->pcm->card)
1041 stream = get_hdac_ext_stream(s);
1042 sbits |= 1 << hdac_stream(stream)->index;
1043 snd_pcm_trigger_done(s, substream);
1046 spin_lock_irqsave(&bus->reg_lock, cookie);
1048 /* first, set SYNC bits of corresponding streams */
1049 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1051 snd_pcm_group_for_each_entry(s, substream) {
1052 if (s->pcm->card != substream->pcm->card)
1054 stream = get_hdac_ext_stream(s);
1056 snd_hdac_stream_start(hdac_stream(stream), true);
1058 snd_hdac_stream_stop(hdac_stream(stream));
1060 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1062 snd_hdac_stream_sync(hstr, start, sbits);
1064 spin_lock_irqsave(&bus->reg_lock, cookie);
1066 /* reset SYNC bits */
1067 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1069 snd_hdac_stream_timecounter_init(hstr, sbits);
1070 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1075 static int skl_platform_pcm_trigger(struct snd_pcm_substream *substream,
1078 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1080 if (!(ebus_to_hbus(ebus))->ppcap)
1081 return skl_coupled_trigger(substream, cmd);
1086 static snd_pcm_uframes_t skl_platform_pcm_pointer
1087 (struct snd_pcm_substream *substream)
1089 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1090 struct hdac_ext_bus *ebus = get_bus_ctx(substream);
1094 * Use DPIB for Playback stream as the periodic DMA Position-in-
1095 * Buffer Writes may be scheduled at the same time or later than
1096 * the MSI and does not guarantee to reflect the Position of the
1097 * last buffer that was transferred. Whereas DPIB register in
1098 * HAD space reflects the actual data that is transferred.
1099 * Use the position buffer for capture, as DPIB write gets
1100 * completed earlier than the actual data written to the DDR.
1102 * For capture stream following workaround is required to fix the
1103 * incorrect position reporting.
1105 * 1. Wait for 20us before reading the DMA position in buffer once
1106 * the interrupt is generated for stream completion as update happens
1107 * on the HDA frame boundary i.e. 20.833uSec.
1108 * 2. Read DPIB register to flush the DMA position value. This dummy
1109 * read is required to flush DMA position value.
1110 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1111 * or greater than period boundary.
1114 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1115 pos = readl(ebus->bus.remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1116 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1117 hdac_stream(hstream)->index));
1120 readl(ebus->bus.remap_addr +
1121 AZX_REG_VS_SDXDPIB_XBASE +
1122 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1123 hdac_stream(hstream)->index));
1124 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1127 if (pos >= hdac_stream(hstream)->bufsize)
1130 return bytes_to_frames(substream->runtime, pos);
1133 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1136 struct snd_soc_pcm_runtime *rtd = snd_pcm_substream_chip(substream);
1137 struct snd_soc_dai *codec_dai = rtd->codec_dai;
1138 u64 codec_frames, codec_nsecs;
1140 if (!codec_dai->driver->ops->delay)
1143 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1144 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1145 substream->runtime->rate);
1147 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1148 return nsec + codec_nsecs;
1150 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1153 static int skl_get_time_info(struct snd_pcm_substream *substream,
1154 struct timespec *system_ts, struct timespec *audio_ts,
1155 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1156 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1158 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1159 struct hdac_stream *hstr = hdac_stream(sstream);
1162 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1163 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1165 snd_pcm_gettime(substream->runtime, system_ts);
1167 nsec = timecounter_read(&hstr->tc);
1168 nsec = div_u64(nsec, 3); /* can be optimized */
1169 if (audio_tstamp_config->report_delay)
1170 nsec = skl_adjust_codec_delay(substream, nsec);
1172 *audio_ts = ns_to_timespec(nsec);
1174 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1175 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1176 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1179 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1185 static const struct snd_pcm_ops skl_platform_ops = {
1186 .open = skl_platform_open,
1187 .ioctl = snd_pcm_lib_ioctl,
1188 .trigger = skl_platform_pcm_trigger,
1189 .pointer = skl_platform_pcm_pointer,
1190 .get_time_info = skl_get_time_info,
1191 .mmap = snd_pcm_lib_default_mmap,
1192 .page = snd_pcm_sgbuf_ops_page,
1195 static void skl_pcm_free(struct snd_pcm *pcm)
1197 snd_pcm_lib_preallocate_free_for_all(pcm);
1200 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1202 static int skl_pcm_new(struct snd_soc_pcm_runtime *rtd)
1204 struct snd_soc_dai *dai = rtd->cpu_dai;
1205 struct hdac_ext_bus *ebus = dev_get_drvdata(dai->dev);
1206 struct snd_pcm *pcm = rtd->pcm;
1209 struct skl *skl = ebus_to_skl(ebus);
1211 if (dai->driver->playback.channels_min ||
1212 dai->driver->capture.channels_min) {
1213 /* buffer pre-allocation */
1214 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1215 if (size > MAX_PREALLOC_SIZE)
1216 size = MAX_PREALLOC_SIZE;
1217 retval = snd_pcm_lib_preallocate_pages_for_all(pcm,
1218 SNDRV_DMA_TYPE_DEV_SG,
1219 snd_dma_pci_data(skl->pci),
1220 size, MAX_PREALLOC_SIZE);
1222 dev_err(dai->dev, "dma buffer allocation fail\n");
1230 static int skl_get_module_info(struct skl *skl, struct skl_module_cfg *mconfig)
1232 struct skl_sst *ctx = skl->skl_sst;
1233 struct skl_module_inst_id *pin_id;
1234 uuid_le *uuid_mod, *uuid_tplg;
1235 struct skl_module *skl_module;
1236 struct uuid_module *module;
1239 uuid_mod = (uuid_le *)mconfig->guid;
1241 if (list_empty(&ctx->uuid_list)) {
1242 dev_err(ctx->dev, "Module list is empty\n");
1246 list_for_each_entry(module, &ctx->uuid_list, list) {
1247 if (uuid_le_cmp(*uuid_mod, module->uuid) == 0) {
1248 mconfig->id.module_id = module->id;
1249 if (mconfig->module)
1250 mconfig->module->loadable = module->is_loadable;
1259 uuid_mod = &module->uuid;
1261 for (i = 0; i < skl->nr_modules; i++) {
1262 skl_module = skl->modules[i];
1263 uuid_tplg = &skl_module->uuid;
1264 if (!uuid_le_cmp(*uuid_mod, *uuid_tplg)) {
1265 mconfig->module = skl_module;
1270 if (skl->nr_modules && ret)
1273 list_for_each_entry(module, &ctx->uuid_list, list) {
1274 for (i = 0; i < MAX_IN_QUEUE; i++) {
1275 pin_id = &mconfig->m_in_pin[i].id;
1276 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1277 pin_id->module_id = module->id;
1280 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1281 pin_id = &mconfig->m_out_pin[i].id;
1282 if (!uuid_le_cmp(pin_id->mod_uuid, module->uuid))
1283 pin_id->module_id = module->id;
1290 static int skl_populate_modules(struct skl *skl)
1292 struct skl_pipeline *p;
1293 struct skl_pipe_module *m;
1294 struct snd_soc_dapm_widget *w;
1295 struct skl_module_cfg *mconfig;
1298 list_for_each_entry(p, &skl->ppl_list, node) {
1299 list_for_each_entry(m, &p->pipe->w_list, node) {
1303 ret = skl_get_module_info(skl, mconfig);
1305 dev_err(skl->skl_sst->dev,
1306 "query module info failed\n");
1315 static int skl_platform_soc_probe(struct snd_soc_platform *platform)
1317 struct hdac_ext_bus *ebus = dev_get_drvdata(platform->dev);
1318 struct skl *skl = ebus_to_skl(ebus);
1319 const struct skl_dsp_ops *ops;
1322 pm_runtime_get_sync(platform->dev);
1323 if ((ebus_to_hbus(ebus))->ppcap) {
1324 skl->platform = platform;
1327 skl->debugfs = skl_debugfs_init(skl);
1329 ret = skl_tplg_init(platform, ebus);
1331 dev_err(platform->dev, "Failed to init topology!\n");
1335 /* load the firmwares, since all is set */
1336 ops = skl_get_dsp_ops(skl->pci->device);
1340 if (skl->skl_sst->is_first_boot == false) {
1341 dev_err(platform->dev, "DSP reports first boot done!!!\n");
1345 ret = ops->init_fw(platform->dev, skl->skl_sst);
1347 dev_err(platform->dev, "Failed to boot first fw: %d\n", ret);
1350 skl_populate_modules(skl);
1351 skl->skl_sst->update_d0i3c = skl_update_d0i3c;
1352 skl_dsp_enable_notification(skl->skl_sst, false);
1354 if (skl->cfg.astate_cfg != NULL) {
1355 skl_dsp_set_astate_cfg(skl->skl_sst,
1356 skl->cfg.astate_cfg->count,
1357 skl->cfg.astate_cfg);
1360 pm_runtime_mark_last_busy(platform->dev);
1361 pm_runtime_put_autosuspend(platform->dev);
1365 static const struct snd_soc_platform_driver skl_platform_drv = {
1366 .probe = skl_platform_soc_probe,
1367 .ops = &skl_platform_ops,
1368 .pcm_new = skl_pcm_new,
1369 .pcm_free = skl_pcm_free,
1372 static const struct snd_soc_component_driver skl_component = {
1376 int skl_platform_register(struct device *dev)
1379 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1380 struct skl *skl = ebus_to_skl(ebus);
1381 struct snd_soc_dai_driver *dais;
1382 int num_dais = ARRAY_SIZE(skl_platform_dai);
1384 INIT_LIST_HEAD(&skl->ppl_list);
1385 INIT_LIST_HEAD(&skl->bind_list);
1387 ret = snd_soc_register_platform(dev, &skl_platform_drv);
1389 dev_err(dev, "soc platform registration failed %d\n", ret);
1393 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1400 if (!skl->use_tplg_pcm) {
1401 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1402 sizeof(skl_platform_dai), GFP_KERNEL);
1409 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1410 sizeof(skl_fe_dai));
1411 num_dais += ARRAY_SIZE(skl_fe_dai);
1414 ret = snd_soc_register_component(dev, &skl_component,
1415 skl->dais, num_dais);
1417 dev_err(dev, "soc component registration failed %d\n", ret);
1423 snd_soc_unregister_platform(dev);
1428 int skl_platform_unregister(struct device *dev)
1430 struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
1431 struct skl *skl = ebus_to_skl(ebus);
1432 struct skl_module_deferred_bind *modules, *tmp;
1434 if (!list_empty(&skl->bind_list)) {
1435 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1436 list_del(&modules->node);
1441 snd_soc_unregister_component(dev);
1442 snd_soc_unregister_platform(dev);