1 // SPDX-License-Identifier: GPL-2.0-only
3 * skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
8 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
10 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
13 #include <linux/pci.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/delay.h>
16 #include <sound/hdaudio.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc.h>
20 #include "skl-topology.h"
21 #include "skl-sst-dsp.h"
22 #include "skl-sst-ipc.h"
29 static const struct snd_pcm_hardware azx_pcm_hw = {
30 .info = (SNDRV_PCM_INFO_MMAP |
31 SNDRV_PCM_INFO_INTERLEAVED |
32 SNDRV_PCM_INFO_BLOCK_TRANSFER |
33 SNDRV_PCM_INFO_MMAP_VALID |
34 SNDRV_PCM_INFO_PAUSE |
35 SNDRV_PCM_INFO_RESUME |
36 SNDRV_PCM_INFO_SYNC_START |
37 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
38 SNDRV_PCM_INFO_HAS_LINK_ATIME |
39 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
40 .formats = SNDRV_PCM_FMTBIT_S16_LE |
41 SNDRV_PCM_FMTBIT_S32_LE |
42 SNDRV_PCM_FMTBIT_S24_LE,
43 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
49 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
50 .period_bytes_min = 128,
51 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
53 .periods_max = AZX_MAX_FRAG,
58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
60 return substream->runtime->private_data;
63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
65 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
66 struct hdac_stream *hstream = hdac_stream(stream);
67 struct hdac_bus *bus = hstream->bus;
71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
72 struct snd_pcm_substream *substream,
75 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
77 hdac_stream(stream)->bufsize = 0;
78 hdac_stream(stream)->period_bytes = 0;
79 hdac_stream(stream)->format_val = 0;
84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
85 struct snd_pcm_runtime *runtime)
87 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
89 /* avoid wrap-around with wall-clock */
90 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
97 return HDAC_EXT_STREAM_TYPE_HOST;
99 return HDAC_EXT_STREAM_TYPE_COUPLED;
103 * check if the stream opened is marked as ignore_suspend by machine, if so
104 * then enable suspend_active refcount
106 * The count supend_active does not need lock as it is used in open/close
107 * and suspend context
109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
110 struct snd_soc_dai *dai, bool enable)
112 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
113 struct snd_soc_dapm_widget *w;
114 struct skl_dev *skl = bus_to_skl(bus);
116 w = snd_soc_dai_get_widget(dai, substream->stream);
118 if (w->ignore_suspend && enable)
119 skl->supend_active++;
120 else if (w->ignore_suspend && !enable)
121 skl->supend_active--;
124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
126 struct hdac_bus *bus = dev_get_drvdata(dev);
127 struct skl_dev *skl = bus_to_skl(bus);
128 unsigned int format_val;
129 struct hdac_stream *hstream;
130 struct hdac_ext_stream *stream;
133 hstream = snd_hdac_get_stream(bus, params->stream,
134 params->host_dma_id + 1);
138 stream = stream_to_hdac_ext_stream(hstream);
139 snd_hdac_ext_stream_decouple(bus, stream, true);
141 format_val = snd_hdac_calc_stream_format(params->s_freq,
142 params->ch, params->format, params->host_bps, 0);
144 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
145 format_val, params->s_freq, params->ch, params->format);
147 snd_hdac_stream_reset(hdac_stream(stream));
148 err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
153 * The recommended SDxFMT programming sequence for BXT
154 * platforms is to couple the stream before writing the format
156 if (HDA_CONTROLLER_IS_APL(skl->pci)) {
157 snd_hdac_ext_stream_decouple(bus, stream, false);
158 err = snd_hdac_stream_setup(hdac_stream(stream));
159 snd_hdac_ext_stream_decouple(bus, stream, true);
161 err = snd_hdac_stream_setup(hdac_stream(stream));
167 hdac_stream(stream)->prepared = 1;
172 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
174 struct hdac_bus *bus = dev_get_drvdata(dev);
175 unsigned int format_val;
176 struct hdac_stream *hstream;
177 struct hdac_ext_stream *stream;
178 struct hdac_ext_link *link;
179 unsigned char stream_tag;
181 hstream = snd_hdac_get_stream(bus, params->stream,
182 params->link_dma_id + 1);
186 stream = stream_to_hdac_ext_stream(hstream);
187 snd_hdac_ext_stream_decouple(bus, stream, true);
188 format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
189 params->format, params->link_bps, 0);
191 dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
192 format_val, params->s_freq, params->ch, params->format);
194 snd_hdac_ext_stream_reset(stream);
196 snd_hdac_ext_stream_setup(stream, format_val);
198 stream_tag = hstream->stream_tag;
199 if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
200 list_for_each_entry(link, &bus->hlink_list, list) {
201 if (link->index == params->link_index)
202 snd_hdac_ext_bus_link_set_stream_id(link,
207 stream->link_prepared = 1;
212 static int skl_pcm_open(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
215 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
216 struct hdac_ext_stream *stream;
217 struct snd_pcm_runtime *runtime = substream->runtime;
218 struct skl_dma_params *dma_params;
219 struct skl_dev *skl = get_skl_ctx(dai->dev);
220 struct skl_module_cfg *mconfig;
222 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
224 stream = snd_hdac_ext_stream_assign(bus, substream,
225 skl_get_host_stream_type(bus));
229 skl_set_pcm_constrains(bus, runtime);
232 * disable WALLCLOCK timestamps for capture streams
233 * until we figure out how to handle digital inputs
235 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
236 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
237 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
240 runtime->private_data = stream;
242 dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
246 dma_params->stream_tag = hdac_stream(stream)->stream_tag;
247 snd_soc_dai_set_dma_data(dai, substream, dma_params);
249 dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
250 dma_params->stream_tag);
251 skl_set_suspend_active(substream, dai, true);
252 snd_pcm_set_sync(substream);
254 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
258 skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
263 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
264 struct snd_soc_dai *dai)
266 struct skl_dev *skl = get_skl_ctx(dai->dev);
267 struct skl_module_cfg *mconfig;
270 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
272 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
275 * In case of XRUN recovery or in the case when the application
276 * calls prepare another time, reset the FW pipe to clean state
279 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
280 mconfig->pipe->state == SKL_PIPE_CREATED ||
281 mconfig->pipe->state == SKL_PIPE_PAUSED)) {
283 ret = skl_reset_pipe(skl, mconfig->pipe);
288 ret = skl_pcm_host_dma_prepare(dai->dev,
289 mconfig->pipe->p_params);
297 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
298 struct snd_pcm_hw_params *params,
299 struct snd_soc_dai *dai)
301 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
302 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
303 struct snd_pcm_runtime *runtime = substream->runtime;
304 struct skl_pipe_params p_params = {0};
305 struct skl_module_cfg *m_cfg;
308 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
309 ret = skl_substream_alloc_pages(bus, substream,
310 params_buffer_bytes(params));
314 dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
315 runtime->rate, runtime->channels, runtime->format);
317 dma_id = hdac_stream(stream)->stream_tag - 1;
318 dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
320 p_params.s_fmt = snd_pcm_format_width(params_format(params));
321 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
322 p_params.ch = params_channels(params);
323 p_params.s_freq = params_rate(params);
324 p_params.host_dma_id = dma_id;
325 p_params.stream = substream->stream;
326 p_params.format = params_format(params);
327 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
328 p_params.host_bps = dai->driver->playback.sig_bits;
330 p_params.host_bps = dai->driver->capture.sig_bits;
333 m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
335 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
340 static void skl_pcm_close(struct snd_pcm_substream *substream,
341 struct snd_soc_dai *dai)
343 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
344 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
345 struct skl_dma_params *dma_params = NULL;
346 struct skl_dev *skl = bus_to_skl(bus);
347 struct skl_module_cfg *mconfig;
349 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
351 snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
353 dma_params = snd_soc_dai_get_dma_data(dai, substream);
355 * now we should set this to NULL as we are freeing by the
358 snd_soc_dai_set_dma_data(dai, substream, NULL);
359 skl_set_suspend_active(substream, dai, false);
362 * check if close is for "Reference Pin" and set back the
363 * CGCTL.MISCBDCGE if disabled by driver
365 if (!strncmp(dai->name, "Reference Pin", 13) &&
366 skl->miscbdcg_disabled) {
367 skl->enable_miscbdcge(dai->dev, true);
368 skl->miscbdcg_disabled = false;
371 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
373 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
378 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
379 struct snd_soc_dai *dai)
381 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
382 struct skl_dev *skl = get_skl_ctx(dai->dev);
383 struct skl_module_cfg *mconfig;
386 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
388 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
391 ret = skl_reset_pipe(skl, mconfig->pipe);
393 dev_err(dai->dev, "%s:Reset failed ret =%d",
397 snd_hdac_stream_cleanup(hdac_stream(stream));
398 hdac_stream(stream)->prepared = 0;
403 static int skl_be_hw_params(struct snd_pcm_substream *substream,
404 struct snd_pcm_hw_params *params,
405 struct snd_soc_dai *dai)
407 struct skl_pipe_params p_params = {0};
409 p_params.s_fmt = snd_pcm_format_width(params_format(params));
410 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
411 p_params.ch = params_channels(params);
412 p_params.s_freq = params_rate(params);
413 p_params.stream = substream->stream;
415 return skl_tplg_be_update_params(dai, &p_params);
418 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
421 struct hdac_bus *bus = get_bus_ctx(substream);
422 struct hdac_ext_stream *stream;
424 unsigned long cookie;
425 struct hdac_stream *hstr;
427 stream = get_hdac_ext_stream(substream);
428 hstr = hdac_stream(stream);
434 case SNDRV_PCM_TRIGGER_START:
435 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
436 case SNDRV_PCM_TRIGGER_RESUME:
440 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
441 case SNDRV_PCM_TRIGGER_SUSPEND:
442 case SNDRV_PCM_TRIGGER_STOP:
450 spin_lock_irqsave(&bus->reg_lock, cookie);
453 snd_hdac_stream_start(hdac_stream(stream));
454 snd_hdac_stream_timecounter_init(hstr, 0);
456 snd_hdac_stream_stop(hdac_stream(stream));
459 spin_unlock_irqrestore(&bus->reg_lock, cookie);
464 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
465 struct snd_soc_dai *dai)
467 struct skl_dev *skl = get_skl_ctx(dai->dev);
468 struct skl_module_cfg *mconfig;
469 struct hdac_bus *bus = get_bus_ctx(substream);
470 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
471 struct hdac_stream *hstream = hdac_stream(stream);
472 struct snd_soc_dapm_widget *w;
475 mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
479 w = snd_soc_dai_get_widget(dai, substream->stream);
482 case SNDRV_PCM_TRIGGER_RESUME:
483 if (!w->ignore_suspend) {
485 * enable DMA Resume enable bit for the stream, set the
486 * dpib & lpib position to resume before starting the
489 snd_hdac_stream_drsm_enable(bus, true, hstream->index);
490 snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
491 snd_hdac_stream_set_lpib(hstream, hstream->lpib);
495 case SNDRV_PCM_TRIGGER_START:
496 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
498 * Start HOST DMA and Start FE Pipe.This is to make sure that
499 * there are no underrun/overrun in the case when the FE
500 * pipeline is started but there is a delay in starting the
501 * DMA channel on the host.
503 ret = skl_decoupled_trigger(substream, cmd);
506 return skl_run_pipe(skl, mconfig->pipe);
508 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
509 case SNDRV_PCM_TRIGGER_SUSPEND:
510 case SNDRV_PCM_TRIGGER_STOP:
512 * Stop FE Pipe first and stop DMA. This is to make sure that
513 * there are no underrun/overrun in the case if there is a delay
514 * between the two operations.
516 ret = skl_stop_pipe(skl, mconfig->pipe);
520 ret = skl_decoupled_trigger(substream, cmd);
521 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
522 /* save the dpib and lpib positions */
523 hstream->dpib = readl(bus->remap_addr +
524 AZX_REG_VS_SDXDPIB_XBASE +
525 (AZX_REG_VS_SDXDPIB_XINTERVAL *
528 hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
530 snd_hdac_ext_stream_decouple(bus, stream, false);
542 static int skl_link_hw_params(struct snd_pcm_substream *substream,
543 struct snd_pcm_hw_params *params,
544 struct snd_soc_dai *dai)
546 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
547 struct hdac_ext_stream *link_dev;
548 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
549 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
550 struct skl_pipe_params p_params = {0};
551 struct hdac_ext_link *link;
554 link_dev = snd_hdac_ext_stream_assign(bus, substream,
555 HDAC_EXT_STREAM_TYPE_LINK);
559 snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
561 link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
565 stream_tag = hdac_stream(link_dev)->stream_tag;
567 /* set the hdac_stream in the codec dai */
568 snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
570 p_params.s_fmt = snd_pcm_format_width(params_format(params));
571 p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
572 p_params.ch = params_channels(params);
573 p_params.s_freq = params_rate(params);
574 p_params.stream = substream->stream;
575 p_params.link_dma_id = stream_tag - 1;
576 p_params.link_index = link->index;
577 p_params.format = params_format(params);
579 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
580 p_params.link_bps = codec_dai->driver->playback.sig_bits;
582 p_params.link_bps = codec_dai->driver->capture.sig_bits;
584 return skl_tplg_be_update_params(dai, &p_params);
587 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
588 struct snd_soc_dai *dai)
590 struct skl_dev *skl = get_skl_ctx(dai->dev);
591 struct skl_module_cfg *mconfig = NULL;
593 /* In case of XRUN recovery, reset the FW pipe to clean state */
594 mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
595 if (mconfig && !mconfig->pipe->passthru &&
596 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
597 skl_reset_pipe(skl, mconfig->pipe);
602 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
603 int cmd, struct snd_soc_dai *dai)
605 struct hdac_ext_stream *link_dev =
606 snd_soc_dai_get_dma_data(dai, substream);
607 struct hdac_bus *bus = get_bus_ctx(substream);
608 struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
610 dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
612 case SNDRV_PCM_TRIGGER_RESUME:
613 case SNDRV_PCM_TRIGGER_START:
614 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
615 snd_hdac_ext_stream_start(link_dev);
618 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
619 case SNDRV_PCM_TRIGGER_SUSPEND:
620 case SNDRV_PCM_TRIGGER_STOP:
621 snd_hdac_ext_stream_clear(link_dev);
622 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
623 snd_hdac_ext_stream_decouple(bus, stream, false);
632 static int skl_link_hw_free(struct snd_pcm_substream *substream,
633 struct snd_soc_dai *dai)
635 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
636 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
637 struct hdac_ext_stream *link_dev =
638 snd_soc_dai_get_dma_data(dai, substream);
639 struct hdac_ext_link *link;
640 unsigned char stream_tag;
642 dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
644 link_dev->link_prepared = 0;
646 link = snd_hdac_ext_bus_get_hlink_by_name(bus, asoc_rtd_to_codec(rtd, 0)->component->name);
650 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
651 stream_tag = hdac_stream(link_dev)->stream_tag;
652 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
655 snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
659 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
660 .startup = skl_pcm_open,
661 .shutdown = skl_pcm_close,
662 .prepare = skl_pcm_prepare,
663 .hw_params = skl_pcm_hw_params,
664 .hw_free = skl_pcm_hw_free,
665 .trigger = skl_pcm_trigger,
668 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
669 .hw_params = skl_be_hw_params,
672 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
673 .hw_params = skl_be_hw_params,
676 static const struct snd_soc_dai_ops skl_link_dai_ops = {
677 .prepare = skl_link_pcm_prepare,
678 .hw_params = skl_link_hw_params,
679 .hw_free = skl_link_hw_free,
680 .trigger = skl_link_pcm_trigger,
683 static struct snd_soc_dai_driver skl_fe_dai[] = {
685 .name = "System Pin",
686 .ops = &skl_pcm_dai_ops,
688 .stream_name = "System Playback",
689 .channels_min = HDA_MONO,
690 .channels_max = HDA_STEREO,
691 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
692 .formats = SNDRV_PCM_FMTBIT_S16_LE |
693 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
697 .stream_name = "System Capture",
698 .channels_min = HDA_MONO,
699 .channels_max = HDA_STEREO,
700 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
701 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
706 .name = "System Pin2",
707 .ops = &skl_pcm_dai_ops,
709 .stream_name = "Headset Playback",
710 .channels_min = HDA_MONO,
711 .channels_max = HDA_STEREO,
712 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
714 .formats = SNDRV_PCM_FMTBIT_S16_LE |
715 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
719 .name = "Echoref Pin",
720 .ops = &skl_pcm_dai_ops,
722 .stream_name = "Echoreference Capture",
723 .channels_min = HDA_STEREO,
724 .channels_max = HDA_STEREO,
725 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
727 .formats = SNDRV_PCM_FMTBIT_S16_LE |
728 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
732 .name = "Reference Pin",
733 .ops = &skl_pcm_dai_ops,
735 .stream_name = "Reference Capture",
736 .channels_min = HDA_MONO,
737 .channels_max = HDA_QUAD,
738 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
739 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
744 .name = "Deepbuffer Pin",
745 .ops = &skl_pcm_dai_ops,
747 .stream_name = "Deepbuffer Playback",
748 .channels_min = HDA_STEREO,
749 .channels_max = HDA_STEREO,
750 .rates = SNDRV_PCM_RATE_48000,
751 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
756 .name = "LowLatency Pin",
757 .ops = &skl_pcm_dai_ops,
759 .stream_name = "Low Latency Playback",
760 .channels_min = HDA_STEREO,
761 .channels_max = HDA_STEREO,
762 .rates = SNDRV_PCM_RATE_48000,
763 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
769 .ops = &skl_pcm_dai_ops,
771 .stream_name = "DMIC Capture",
772 .channels_min = HDA_MONO,
773 .channels_max = HDA_QUAD,
774 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
775 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
781 .ops = &skl_pcm_dai_ops,
783 .stream_name = "HDMI1 Playback",
784 .channels_min = HDA_STEREO,
786 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
787 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
788 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
789 SNDRV_PCM_RATE_192000,
790 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
791 SNDRV_PCM_FMTBIT_S32_LE,
797 .ops = &skl_pcm_dai_ops,
799 .stream_name = "HDMI2 Playback",
800 .channels_min = HDA_STEREO,
802 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
803 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
804 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
805 SNDRV_PCM_RATE_192000,
806 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
807 SNDRV_PCM_FMTBIT_S32_LE,
813 .ops = &skl_pcm_dai_ops,
815 .stream_name = "HDMI3 Playback",
816 .channels_min = HDA_STEREO,
818 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
819 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
820 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
821 SNDRV_PCM_RATE_192000,
822 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
823 SNDRV_PCM_FMTBIT_S32_LE,
830 static struct snd_soc_dai_driver skl_platform_dai[] = {
833 .ops = &skl_be_ssp_dai_ops,
835 .stream_name = "ssp0 Tx",
836 .channels_min = HDA_STEREO,
837 .channels_max = HDA_STEREO,
838 .rates = SNDRV_PCM_RATE_48000,
839 .formats = SNDRV_PCM_FMTBIT_S16_LE,
842 .stream_name = "ssp0 Rx",
843 .channels_min = HDA_STEREO,
844 .channels_max = HDA_STEREO,
845 .rates = SNDRV_PCM_RATE_48000,
846 .formats = SNDRV_PCM_FMTBIT_S16_LE,
851 .ops = &skl_be_ssp_dai_ops,
853 .stream_name = "ssp1 Tx",
854 .channels_min = HDA_STEREO,
855 .channels_max = HDA_STEREO,
856 .rates = SNDRV_PCM_RATE_48000,
857 .formats = SNDRV_PCM_FMTBIT_S16_LE,
860 .stream_name = "ssp1 Rx",
861 .channels_min = HDA_STEREO,
862 .channels_max = HDA_STEREO,
863 .rates = SNDRV_PCM_RATE_48000,
864 .formats = SNDRV_PCM_FMTBIT_S16_LE,
869 .ops = &skl_be_ssp_dai_ops,
871 .stream_name = "ssp2 Tx",
872 .channels_min = HDA_STEREO,
873 .channels_max = HDA_STEREO,
874 .rates = SNDRV_PCM_RATE_48000,
875 .formats = SNDRV_PCM_FMTBIT_S16_LE,
878 .stream_name = "ssp2 Rx",
879 .channels_min = HDA_STEREO,
880 .channels_max = HDA_STEREO,
881 .rates = SNDRV_PCM_RATE_48000,
882 .formats = SNDRV_PCM_FMTBIT_S16_LE,
887 .ops = &skl_be_ssp_dai_ops,
889 .stream_name = "ssp3 Tx",
890 .channels_min = HDA_STEREO,
891 .channels_max = HDA_STEREO,
892 .rates = SNDRV_PCM_RATE_48000,
893 .formats = SNDRV_PCM_FMTBIT_S16_LE,
896 .stream_name = "ssp3 Rx",
897 .channels_min = HDA_STEREO,
898 .channels_max = HDA_STEREO,
899 .rates = SNDRV_PCM_RATE_48000,
900 .formats = SNDRV_PCM_FMTBIT_S16_LE,
905 .ops = &skl_be_ssp_dai_ops,
907 .stream_name = "ssp4 Tx",
908 .channels_min = HDA_STEREO,
909 .channels_max = HDA_STEREO,
910 .rates = SNDRV_PCM_RATE_48000,
911 .formats = SNDRV_PCM_FMTBIT_S16_LE,
914 .stream_name = "ssp4 Rx",
915 .channels_min = HDA_STEREO,
916 .channels_max = HDA_STEREO,
917 .rates = SNDRV_PCM_RATE_48000,
918 .formats = SNDRV_PCM_FMTBIT_S16_LE,
923 .ops = &skl_be_ssp_dai_ops,
925 .stream_name = "ssp5 Tx",
926 .channels_min = HDA_STEREO,
927 .channels_max = HDA_STEREO,
928 .rates = SNDRV_PCM_RATE_48000,
929 .formats = SNDRV_PCM_FMTBIT_S16_LE,
932 .stream_name = "ssp5 Rx",
933 .channels_min = HDA_STEREO,
934 .channels_max = HDA_STEREO,
935 .rates = SNDRV_PCM_RATE_48000,
936 .formats = SNDRV_PCM_FMTBIT_S16_LE,
940 .name = "iDisp1 Pin",
941 .ops = &skl_link_dai_ops,
943 .stream_name = "iDisp1 Tx",
944 .channels_min = HDA_STEREO,
946 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
947 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
948 SNDRV_PCM_FMTBIT_S24_LE,
952 .name = "iDisp2 Pin",
953 .ops = &skl_link_dai_ops,
955 .stream_name = "iDisp2 Tx",
956 .channels_min = HDA_STEREO,
958 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
959 SNDRV_PCM_RATE_48000,
960 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
961 SNDRV_PCM_FMTBIT_S24_LE,
965 .name = "iDisp3 Pin",
966 .ops = &skl_link_dai_ops,
968 .stream_name = "iDisp3 Tx",
969 .channels_min = HDA_STEREO,
971 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
972 SNDRV_PCM_RATE_48000,
973 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
974 SNDRV_PCM_FMTBIT_S24_LE,
978 .name = "DMIC01 Pin",
979 .ops = &skl_dmic_dai_ops,
981 .stream_name = "DMIC01 Rx",
982 .channels_min = HDA_MONO,
983 .channels_max = HDA_QUAD,
984 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
985 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
989 .name = "DMIC16k Pin",
990 .ops = &skl_dmic_dai_ops,
992 .stream_name = "DMIC16k Rx",
993 .channels_min = HDA_MONO,
994 .channels_max = HDA_QUAD,
995 .rates = SNDRV_PCM_RATE_16000,
996 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1000 .name = "Analog CPU DAI",
1001 .ops = &skl_link_dai_ops,
1003 .stream_name = "Analog CPU Playback",
1004 .channels_min = HDA_MONO,
1005 .channels_max = HDA_MAX,
1006 .rates = SNDRV_PCM_RATE_8000_192000,
1007 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1008 SNDRV_PCM_FMTBIT_S32_LE,
1011 .stream_name = "Analog CPU Capture",
1012 .channels_min = HDA_MONO,
1013 .channels_max = HDA_MAX,
1014 .rates = SNDRV_PCM_RATE_8000_192000,
1015 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1016 SNDRV_PCM_FMTBIT_S32_LE,
1020 .name = "Alt Analog CPU DAI",
1021 .ops = &skl_link_dai_ops,
1023 .stream_name = "Alt Analog CPU Playback",
1024 .channels_min = HDA_MONO,
1025 .channels_max = HDA_MAX,
1026 .rates = SNDRV_PCM_RATE_8000_192000,
1027 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1028 SNDRV_PCM_FMTBIT_S32_LE,
1031 .stream_name = "Alt Analog CPU Capture",
1032 .channels_min = HDA_MONO,
1033 .channels_max = HDA_MAX,
1034 .rates = SNDRV_PCM_RATE_8000_192000,
1035 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1036 SNDRV_PCM_FMTBIT_S32_LE,
1040 .name = "Digital CPU DAI",
1041 .ops = &skl_link_dai_ops,
1043 .stream_name = "Digital CPU Playback",
1044 .channels_min = HDA_MONO,
1045 .channels_max = HDA_MAX,
1046 .rates = SNDRV_PCM_RATE_8000_192000,
1047 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1048 SNDRV_PCM_FMTBIT_S32_LE,
1051 .stream_name = "Digital CPU Capture",
1052 .channels_min = HDA_MONO,
1053 .channels_max = HDA_MAX,
1054 .rates = SNDRV_PCM_RATE_8000_192000,
1055 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1056 SNDRV_PCM_FMTBIT_S32_LE,
1061 int skl_dai_load(struct snd_soc_component *cmp, int index,
1062 struct snd_soc_dai_driver *dai_drv,
1063 struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1065 dai_drv->ops = &skl_pcm_dai_ops;
1070 static int skl_platform_soc_open(struct snd_soc_component *component,
1071 struct snd_pcm_substream *substream)
1073 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1074 struct snd_soc_dai_link *dai_link = rtd->dai_link;
1076 dev_dbg(asoc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1077 dai_link->cpus->dai_name);
1079 snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1084 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1087 struct hdac_bus *bus = get_bus_ctx(substream);
1088 struct hdac_ext_stream *stream;
1089 struct snd_pcm_substream *s;
1092 unsigned long cookie;
1093 struct hdac_stream *hstr;
1095 stream = get_hdac_ext_stream(substream);
1096 hstr = hdac_stream(stream);
1098 dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1100 if (!hstr->prepared)
1104 case SNDRV_PCM_TRIGGER_START:
1105 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1106 case SNDRV_PCM_TRIGGER_RESUME:
1110 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1111 case SNDRV_PCM_TRIGGER_SUSPEND:
1112 case SNDRV_PCM_TRIGGER_STOP:
1120 snd_pcm_group_for_each_entry(s, substream) {
1121 if (s->pcm->card != substream->pcm->card)
1123 stream = get_hdac_ext_stream(s);
1124 sbits |= 1 << hdac_stream(stream)->index;
1125 snd_pcm_trigger_done(s, substream);
1128 spin_lock_irqsave(&bus->reg_lock, cookie);
1130 /* first, set SYNC bits of corresponding streams */
1131 snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1133 snd_pcm_group_for_each_entry(s, substream) {
1134 if (s->pcm->card != substream->pcm->card)
1136 stream = get_hdac_ext_stream(s);
1138 snd_hdac_stream_start(hdac_stream(stream));
1140 snd_hdac_stream_stop(hdac_stream(stream));
1142 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1144 snd_hdac_stream_sync(hstr, start, sbits);
1146 spin_lock_irqsave(&bus->reg_lock, cookie);
1148 /* reset SYNC bits */
1149 snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1151 snd_hdac_stream_timecounter_init(hstr, sbits);
1152 spin_unlock_irqrestore(&bus->reg_lock, cookie);
1157 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1158 struct snd_pcm_substream *substream,
1161 struct hdac_bus *bus = get_bus_ctx(substream);
1164 return skl_coupled_trigger(substream, cmd);
1169 static snd_pcm_uframes_t skl_platform_soc_pointer(
1170 struct snd_soc_component *component,
1171 struct snd_pcm_substream *substream)
1173 struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1174 struct hdac_bus *bus = get_bus_ctx(substream);
1178 * Use DPIB for Playback stream as the periodic DMA Position-in-
1179 * Buffer Writes may be scheduled at the same time or later than
1180 * the MSI and does not guarantee to reflect the Position of the
1181 * last buffer that was transferred. Whereas DPIB register in
1182 * HAD space reflects the actual data that is transferred.
1183 * Use the position buffer for capture, as DPIB write gets
1184 * completed earlier than the actual data written to the DDR.
1186 * For capture stream following workaround is required to fix the
1187 * incorrect position reporting.
1189 * 1. Wait for 20us before reading the DMA position in buffer once
1190 * the interrupt is generated for stream completion as update happens
1191 * on the HDA frame boundary i.e. 20.833uSec.
1192 * 2. Read DPIB register to flush the DMA position value. This dummy
1193 * read is required to flush DMA position value.
1194 * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1195 * or greater than period boundary.
1198 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1199 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1200 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1201 hdac_stream(hstream)->index));
1204 readl(bus->remap_addr +
1205 AZX_REG_VS_SDXDPIB_XBASE +
1206 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1207 hdac_stream(hstream)->index));
1208 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1211 if (pos >= hdac_stream(hstream)->bufsize)
1214 return bytes_to_frames(substream->runtime, pos);
1217 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1220 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
1221 struct snd_soc_dai *codec_dai = asoc_rtd_to_codec(rtd, 0);
1222 u64 codec_frames, codec_nsecs;
1224 if (!codec_dai->driver->ops->delay)
1227 codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1228 codec_nsecs = div_u64(codec_frames * 1000000000LL,
1229 substream->runtime->rate);
1231 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1232 return nsec + codec_nsecs;
1234 return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1237 static int skl_platform_soc_get_time_info(
1238 struct snd_soc_component *component,
1239 struct snd_pcm_substream *substream,
1240 struct timespec64 *system_ts, struct timespec64 *audio_ts,
1241 struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1242 struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1244 struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1245 struct hdac_stream *hstr = hdac_stream(sstream);
1248 if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1249 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1251 snd_pcm_gettime(substream->runtime, system_ts);
1253 nsec = timecounter_read(&hstr->tc);
1254 if (audio_tstamp_config->report_delay)
1255 nsec = skl_adjust_codec_delay(substream, nsec);
1257 *audio_ts = ns_to_timespec64(nsec);
1259 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1260 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1261 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1264 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1270 #define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
1272 static int skl_platform_soc_new(struct snd_soc_component *component,
1273 struct snd_soc_pcm_runtime *rtd)
1275 struct snd_soc_dai *dai = asoc_rtd_to_cpu(rtd, 0);
1276 struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1277 struct snd_pcm *pcm = rtd->pcm;
1279 struct skl_dev *skl = bus_to_skl(bus);
1281 if (dai->driver->playback.channels_min ||
1282 dai->driver->capture.channels_min) {
1283 /* buffer pre-allocation */
1284 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1285 if (size > MAX_PREALLOC_SIZE)
1286 size = MAX_PREALLOC_SIZE;
1287 snd_pcm_set_managed_buffer_all(pcm,
1288 SNDRV_DMA_TYPE_DEV_SG,
1290 size, MAX_PREALLOC_SIZE);
1296 static int skl_get_module_info(struct skl_dev *skl,
1297 struct skl_module_cfg *mconfig)
1299 struct skl_module_inst_id *pin_id;
1300 guid_t *uuid_mod, *uuid_tplg;
1301 struct skl_module *skl_module;
1302 struct uuid_module *module;
1305 uuid_mod = (guid_t *)mconfig->guid;
1307 if (list_empty(&skl->uuid_list)) {
1308 dev_err(skl->dev, "Module list is empty\n");
1312 for (i = 0; i < skl->nr_modules; i++) {
1313 skl_module = skl->modules[i];
1314 uuid_tplg = &skl_module->uuid;
1315 if (guid_equal(uuid_mod, uuid_tplg)) {
1316 mconfig->module = skl_module;
1322 if (skl->nr_modules && ret)
1326 list_for_each_entry(module, &skl->uuid_list, list) {
1327 if (guid_equal(uuid_mod, &module->uuid)) {
1328 mconfig->id.module_id = module->id;
1329 mconfig->module->loadable = module->is_loadable;
1333 for (i = 0; i < MAX_IN_QUEUE; i++) {
1334 pin_id = &mconfig->m_in_pin[i].id;
1335 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1336 pin_id->module_id = module->id;
1339 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1340 pin_id = &mconfig->m_out_pin[i].id;
1341 if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1342 pin_id->module_id = module->id;
1349 static int skl_populate_modules(struct skl_dev *skl)
1351 struct skl_pipeline *p;
1352 struct skl_pipe_module *m;
1353 struct snd_soc_dapm_widget *w;
1354 struct skl_module_cfg *mconfig;
1357 list_for_each_entry(p, &skl->ppl_list, node) {
1358 list_for_each_entry(m, &p->pipe->w_list, node) {
1362 ret = skl_get_module_info(skl, mconfig);
1365 "query module info failed\n");
1369 skl_tplg_add_moduleid_in_bind_params(skl, w);
1376 static int skl_platform_soc_probe(struct snd_soc_component *component)
1378 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1379 struct skl_dev *skl = bus_to_skl(bus);
1380 const struct skl_dsp_ops *ops;
1383 ret = pm_runtime_resume_and_get(component->dev);
1384 if (ret < 0 && ret != -EACCES)
1388 skl->component = component;
1391 skl->debugfs = skl_debugfs_init(skl);
1393 ret = skl_tplg_init(component, bus);
1395 dev_err(component->dev, "Failed to init topology!\n");
1399 /* load the firmwares, since all is set */
1400 ops = skl_get_dsp_ops(skl->pci->device);
1405 * Disable dynamic clock and power gating during firmware
1406 * and library download
1408 skl->enable_miscbdcge(component->dev, false);
1409 skl->clock_power_gating(component->dev, false);
1411 ret = ops->init_fw(component->dev, skl);
1412 skl->enable_miscbdcge(component->dev, true);
1413 skl->clock_power_gating(component->dev, true);
1415 dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1418 skl_populate_modules(skl);
1419 skl->update_d0i3c = skl_update_d0i3c;
1421 if (skl->cfg.astate_cfg != NULL) {
1422 skl_dsp_set_astate_cfg(skl,
1423 skl->cfg.astate_cfg->count,
1424 skl->cfg.astate_cfg);
1427 pm_runtime_mark_last_busy(component->dev);
1428 pm_runtime_put_autosuspend(component->dev);
1433 static void skl_platform_soc_remove(struct snd_soc_component *component)
1435 struct hdac_bus *bus = dev_get_drvdata(component->dev);
1436 struct skl_dev *skl = bus_to_skl(bus);
1438 skl_tplg_exit(component, bus);
1440 skl_debugfs_exit(skl);
1443 static const struct snd_soc_component_driver skl_component = {
1445 .probe = skl_platform_soc_probe,
1446 .remove = skl_platform_soc_remove,
1447 .open = skl_platform_soc_open,
1448 .trigger = skl_platform_soc_trigger,
1449 .pointer = skl_platform_soc_pointer,
1450 .get_time_info = skl_platform_soc_get_time_info,
1451 .pcm_construct = skl_platform_soc_new,
1452 .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1455 int skl_platform_register(struct device *dev)
1458 struct snd_soc_dai_driver *dais;
1459 int num_dais = ARRAY_SIZE(skl_platform_dai);
1460 struct hdac_bus *bus = dev_get_drvdata(dev);
1461 struct skl_dev *skl = bus_to_skl(bus);
1463 skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1470 if (!skl->use_tplg_pcm) {
1471 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1472 sizeof(skl_platform_dai), GFP_KERNEL);
1479 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1480 sizeof(skl_fe_dai));
1481 num_dais += ARRAY_SIZE(skl_fe_dai);
1484 ret = devm_snd_soc_register_component(dev, &skl_component,
1485 skl->dais, num_dais);
1487 dev_err(dev, "soc component registration failed %d\n", ret);
1492 int skl_platform_unregister(struct device *dev)
1494 struct hdac_bus *bus = dev_get_drvdata(dev);
1495 struct skl_dev *skl = bus_to_skl(bus);
1496 struct skl_module_deferred_bind *modules, *tmp;
1498 list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1499 list_del(&modules->node);