sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/hdaudio.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc.h>
  19 #include "skl.h"
  20 #include "skl-topology.h"
  21 #include "skl-sst-dsp.h"
  22 #include "skl-sst-ipc.h"
  23
  24 #define HDA_MONO 1
  25 #define HDA_STEREO 2
  26 #define HDA_QUAD 4
  27 #define HDA_MAX 8
  28
  29 static const struct snd_pcm_hardware azx_pcm_hw = {
  30         .info =                 (SNDRV_PCM_INFO_MMAP |
  31                                  SNDRV_PCM_INFO_INTERLEAVED |
  32                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  33                                  SNDRV_PCM_INFO_MMAP_VALID |
  34                                  SNDRV_PCM_INFO_PAUSE |
  35                                  SNDRV_PCM_INFO_RESUME |
  36                                  SNDRV_PCM_INFO_SYNC_START |
  37                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  38                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  39                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  40         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  41                                 SNDRV_PCM_FMTBIT_S32_LE |
  42                                 SNDRV_PCM_FMTBIT_S24_LE,
  43         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  44                                 SNDRV_PCM_RATE_8000,
  45         .rate_min =             8000,
  46         .rate_max =             48000,
  47         .channels_min =         1,
  48         .channels_max =         8,
  49         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  50         .period_bytes_min =     128,
  51         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  52         .periods_min =          2,
  53         .periods_max =          AZX_MAX_FRAG,
  54         .fifo_size =            0,
  55 };
  56
  57 static inline
  58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  59 {
  60         return substream->runtime->private_data;
  61 }
  62
  63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  64 {
  65         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  66         struct hdac_stream *hstream = hdac_stream(stream);
  67         struct hdac_bus *bus = hstream->bus;
  68         return bus;
  69 }
  70
  71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  72                                  struct snd_pcm_substream *substream,
  73                                  size_t size)
  74 {
  75         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  76
  77         hdac_stream(stream)->bufsize = 0;
  78         hdac_stream(stream)->period_bytes = 0;
  79         hdac_stream(stream)->format_val = 0;
  80
  81         return 0;
  82 }
  83
  84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  85                                  struct snd_pcm_runtime *runtime)
  86 {
  87         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  88
  89         /* avoid wrap-around with wall-clock */
  90         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  91                                      20, 178000000);
  92 }
  93
  94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  95 {
  96         if (bus->ppcap)
  97                 return HDAC_EXT_STREAM_TYPE_HOST;
  98         else
  99                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 100 }
 101
 102 /*
 103  * check if the stream opened is marked as ignore_suspend by machine, if so
 104  * then enable suspend_active refcount
 105  *
 106  * The count supend_active does not need lock as it is used in open/close
 107  * and suspend context
 108  */
 109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 110                                          struct snd_soc_dai *dai, bool enable)
 111 {
 112         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 113         struct snd_soc_dapm_widget *w;
 114         struct skl_dev *skl = bus_to_skl(bus);
 115
 116         w = snd_soc_dai_get_widget(dai, substream->stream);
 117
 118         if (w->ignore_suspend && enable)
 119                 skl->supend_active++;
 120         else if (w->ignore_suspend && !enable)
 121                 skl->supend_active--;
 122 }
 123
 124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dev);
 127         struct skl_dev *skl = bus_to_skl(bus);
 128         unsigned int format_val;
 129         struct hdac_stream *hstream;
 130         struct hdac_ext_stream *stream;
 131         int err;
 132
 133         hstream = snd_hdac_get_stream(bus, params->stream,
 134                                         params->host_dma_id + 1);
 135         if (!hstream)
 136                 return -EINVAL;
 137
 138         stream = stream_to_hdac_ext_stream(hstream);
 139         snd_hdac_ext_stream_decouple(bus, stream, true);
 140
 141         format_val = snd_hdac_calc_stream_format(params->s_freq,
 142                         params->ch, params->format, params->host_bps, 0);
 143
 144         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 145                 format_val, params->s_freq, params->ch, params->format);
 146
 147         snd_hdac_stream_reset(hdac_stream(stream));
 148         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 149         if (err < 0)
 150                 return err;
 151
 152         /*
 153          * The recommended SDxFMT programming sequence for BXT
 154          * platforms is to couple the stream before writing the format
 155          */
 156         if (HDA_CONTROLLER_IS_APL(skl->pci)) {
 157                 snd_hdac_ext_stream_decouple(bus, stream, false);
 158                 err = snd_hdac_stream_setup(hdac_stream(stream));
 159                 snd_hdac_ext_stream_decouple(bus, stream, true);
 160         } else {
 161                 err = snd_hdac_stream_setup(hdac_stream(stream));
 162         }
 163
 164         if (err < 0)
 165                 return err;
 166
 167         hdac_stream(stream)->prepared = 1;
 168
 169         return 0;
 170 }
 171
 172 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 173 {
 174         struct hdac_bus *bus = dev_get_drvdata(dev);
 175         unsigned int format_val;
 176         struct hdac_stream *hstream;
 177         struct hdac_ext_stream *stream;
 178         struct hdac_ext_link *link;
 179         unsigned char stream_tag;
 180
 181         hstream = snd_hdac_get_stream(bus, params->stream,
 182                                         params->link_dma_id + 1);
 183         if (!hstream)
 184                 return -EINVAL;
 185
 186         stream = stream_to_hdac_ext_stream(hstream);
 187         snd_hdac_ext_stream_decouple(bus, stream, true);
 188         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 189                                         params->format, params->link_bps, 0);
 190
 191         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 192                 format_val, params->s_freq, params->ch, params->format);
 193
 194         snd_hdac_ext_stream_reset(stream);
 195
 196         snd_hdac_ext_stream_setup(stream, format_val);
 197
 198         stream_tag = hstream->stream_tag;
 199         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 200                 list_for_each_entry(link, &bus->hlink_list, list) {
 201                         if (link->index == params->link_index)
 202                                 snd_hdac_ext_bus_link_set_stream_id(link,
 203                                                                     stream_tag);
 204                 }
 205         }
 206
 207         stream->link_prepared = 1;
 208
 209         return 0;
 210 }
 211
 212 static int skl_pcm_open(struct snd_pcm_substream *substream,
 213                 struct snd_soc_dai *dai)
 214 {
 215         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 216         struct hdac_ext_stream *stream;
 217         struct snd_pcm_runtime *runtime = substream->runtime;
 218         struct skl_dma_params *dma_params;
 219         struct skl_dev *skl = get_skl_ctx(dai->dev);
 220         struct skl_module_cfg *mconfig;
 221
 222         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 223
 224         stream = snd_hdac_ext_stream_assign(bus, substream,
 225                                         skl_get_host_stream_type(bus));
 226         if (stream == NULL)
 227                 return -EBUSY;
 228
 229         skl_set_pcm_constrains(bus, runtime);
 230
 231         /*
 232          * disable WALLCLOCK timestamps for capture streams
 233          * until we figure out how to handle digital inputs
 234          */
 235         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 236                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 237                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 238         }
 239
 240         runtime->private_data = stream;
 241
 242         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 243         if (!dma_params)
 244                 return -ENOMEM;
 245
 246         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 247         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 248
 249         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 250                                  dma_params->stream_tag);
 251         skl_set_suspend_active(substream, dai, true);
 252         snd_pcm_set_sync(substream);
 253
 254         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 255         if (!mconfig)
 256                 return -EINVAL;
 257
 258         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 259
 260         return 0;
 261 }
 262
 263 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 264                 struct snd_soc_dai *dai)
 265 {
 266         struct skl_dev *skl = get_skl_ctx(dai->dev);
 267         struct skl_module_cfg *mconfig;
 268         int ret;
 269
 270         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 271
 272         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 273
 274         /*
 275          * In case of XRUN recovery or in the case when the application
 276          * calls prepare another time, reset the FW pipe to clean state
 277          */
 278         if (mconfig &&
 279                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 280                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 281                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 282
 283                 ret = skl_reset_pipe(skl, mconfig->pipe);
 284
 285                 if (ret < 0)
 286                         return ret;
 287
 288                 ret = skl_pcm_host_dma_prepare(dai->dev,
 289                                         mconfig->pipe->p_params);
 290                 if (ret < 0)
 291                         return ret;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 298                                 struct snd_pcm_hw_params *params,
 299                                 struct snd_soc_dai *dai)
 300 {
 301         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 302         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 303         struct snd_pcm_runtime *runtime = substream->runtime;
 304         struct skl_pipe_params p_params = {0};
 305         struct skl_module_cfg *m_cfg;
 306         int ret, dma_id;
 307
 308         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 309         ret = skl_substream_alloc_pages(bus, substream,
 310                                           params_buffer_bytes(params));
 311         if (ret < 0)
 312                 return ret;
 313
 314         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 315                         runtime->rate, runtime->channels, runtime->format);
 316
 317         dma_id = hdac_stream(stream)->stream_tag - 1;
 318         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 319
 320         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 321         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 322         p_params.ch = params_channels(params);
 323         p_params.s_freq = params_rate(params);
 324         p_params.host_dma_id = dma_id;
 325         p_params.stream = substream->stream;
 326         p_params.format = params_format(params);
 327         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 328                 p_params.host_bps = dai->driver->playback.sig_bits;
 329         else
 330                 p_params.host_bps = dai->driver->capture.sig_bits;
 331
 332
 333         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 334         if (m_cfg)
 335                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 336
 337         return 0;
 338 }
 339
 340 static void skl_pcm_close(struct snd_pcm_substream *substream,
 341                 struct snd_soc_dai *dai)
 342 {
 343         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 344         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 345         struct skl_dma_params *dma_params = NULL;
 346         struct skl_dev *skl = bus_to_skl(bus);
 347         struct skl_module_cfg *mconfig;
 348
 349         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 350
 351         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 352
 353         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 354         /*
 355          * now we should set this to NULL as we are freeing by the
 356          * dma_params
 357          */
 358         snd_soc_dai_set_dma_data(dai, substream, NULL);
 359         skl_set_suspend_active(substream, dai, false);
 360
 361         /*
 362          * check if close is for "Reference Pin" and set back the
 363          * CGCTL.MISCBDCGE if disabled by driver
 364          */
 365         if (!strncmp(dai->name, "Reference Pin", 13) &&
 366                         skl->miscbdcg_disabled) {
 367                 skl->enable_miscbdcge(dai->dev, true);
 368                 skl->miscbdcg_disabled = false;
 369         }
 370
 371         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 372         if (mconfig)
 373                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 374
 375         kfree(dma_params);
 376 }
 377
 378 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 379                 struct snd_soc_dai *dai)
 380 {
 381         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 382         struct skl_dev *skl = get_skl_ctx(dai->dev);
 383         struct skl_module_cfg *mconfig;
 384         int ret;
 385
 386         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 387
 388         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 389
 390         if (mconfig) {
 391                 ret = skl_reset_pipe(skl, mconfig->pipe);
 392                 if (ret < 0)
 393                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 394                                                 __func__, ret);
 395         }
 396
 397         snd_hdac_stream_cleanup(hdac_stream(stream));
 398         hdac_stream(stream)->prepared = 0;
 399
 400         return 0;
 401 }
 402
 403 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 404                                 struct snd_pcm_hw_params *params,
 405                                 struct snd_soc_dai *dai)
 406 {
 407         struct skl_pipe_params p_params = {0};
 408
 409         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 410         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 411         p_params.ch = params_channels(params);
 412         p_params.s_freq = params_rate(params);
 413         p_params.stream = substream->stream;
 414
 415         return skl_tplg_be_update_params(dai, &p_params);
 416 }
 417
 418 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 419                 int cmd)
 420 {
 421         struct hdac_bus *bus = get_bus_ctx(substream);
 422         struct hdac_ext_stream *stream;
 423         int start;
 424         unsigned long cookie;
 425         struct hdac_stream *hstr;
 426
 427         stream = get_hdac_ext_stream(substream);
 428         hstr = hdac_stream(stream);
 429
 430         if (!hstr->prepared)
 431                 return -EPIPE;
 432
 433         switch (cmd) {
 434         case SNDRV_PCM_TRIGGER_START:
 435         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 436         case SNDRV_PCM_TRIGGER_RESUME:
 437                 start = 1;
 438                 break;
 439
 440         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 441         case SNDRV_PCM_TRIGGER_SUSPEND:
 442         case SNDRV_PCM_TRIGGER_STOP:
 443                 start = 0;
 444                 break;
 445
 446         default:
 447                 return -EINVAL;
 448         }
 449
 450         spin_lock_irqsave(&bus->reg_lock, cookie);
 451
 452         if (start) {
 453                 snd_hdac_stream_start(hdac_stream(stream));
 454                 snd_hdac_stream_timecounter_init(hstr, 0);
 455         } else {
 456                 snd_hdac_stream_stop(hdac_stream(stream));
 457         }
 458
 459         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 460
 461         return 0;
 462 }
 463
 464 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 465                 struct snd_soc_dai *dai)
 466 {
 467         struct skl_dev *skl = get_skl_ctx(dai->dev);
 468         struct skl_module_cfg *mconfig;
 469         struct hdac_bus *bus = get_bus_ctx(substream);
 470         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 471         struct hdac_stream *hstream = hdac_stream(stream);
 472         struct snd_soc_dapm_widget *w;
 473         int ret;
 474
 475         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 476         if (!mconfig)
 477                 return -EIO;
 478
 479         w = snd_soc_dai_get_widget(dai, substream->stream);
 480
 481         switch (cmd) {
 482         case SNDRV_PCM_TRIGGER_RESUME:
 483                 if (!w->ignore_suspend) {
 484                         /*
 485                          * enable DMA Resume enable bit for the stream, set the
 486                          * dpib & lpib position to resume before starting the
 487                          * DMA
 488                          */
 489                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 490                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 491                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 492                 }
 493                 fallthrough;
 494
 495         case SNDRV_PCM_TRIGGER_START:
 496         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 497                 /*
 498                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 499                  * there are no underrun/overrun in the case when the FE
 500                  * pipeline is started but there is a delay in starting the
 501                  * DMA channel on the host.
 502                  */
 503                 ret = skl_decoupled_trigger(substream, cmd);
 504                 if (ret < 0)
 505                         return ret;
 506                 return skl_run_pipe(skl, mconfig->pipe);
 507
 508         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 509         case SNDRV_PCM_TRIGGER_SUSPEND:
 510         case SNDRV_PCM_TRIGGER_STOP:
 511                 /*
 512                  * Stop FE Pipe first and stop DMA. This is to make sure that
 513                  * there are no underrun/overrun in the case if there is a delay
 514                  * between the two operations.
 515                  */
 516                 ret = skl_stop_pipe(skl, mconfig->pipe);
 517                 if (ret < 0)
 518                         return ret;
 519
 520                 ret = skl_decoupled_trigger(substream, cmd);
 521                 if (ret < 0)
 522                         return ret;
 523
 524                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 525                         /* save the dpib and lpib positions */
 526                         hstream->dpib = readl(bus->remap_addr +
 527                                         AZX_REG_VS_SDXDPIB_XBASE +
 528                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 529                                         hstream->index));
 530
 531                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 532
 533                         snd_hdac_ext_stream_decouple(bus, stream, false);
 534                 }
 535                 break;
 536
 537         default:
 538                 return -EINVAL;
 539         }
 540
 541         return 0;
 542 }
 543
 544
 545 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 546                                 struct snd_pcm_hw_params *params,
 547                                 struct snd_soc_dai *dai)
 548 {
 549         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 550         struct hdac_ext_stream *link_dev;
 551         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 552         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
 553         struct skl_pipe_params p_params = {0};
 554         struct hdac_ext_link *link;
 555         int stream_tag;
 556
 557         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 558                                         HDAC_EXT_STREAM_TYPE_LINK);
 559         if (!link_dev)
 560                 return -EBUSY;
 561
 562         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 563
 564         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 565         if (!link)
 566                 return -EINVAL;
 567
 568         stream_tag = hdac_stream(link_dev)->stream_tag;
 569
 570         /* set the hdac_stream in the codec dai */
 571         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 572
 573         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 574         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 575         p_params.ch = params_channels(params);
 576         p_params.s_freq = params_rate(params);
 577         p_params.stream = substream->stream;
 578         p_params.link_dma_id = stream_tag - 1;
 579         p_params.link_index = link->index;
 580         p_params.format = params_format(params);
 581
 582         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 583                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 584         else
 585                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 586
 587         return skl_tplg_be_update_params(dai, &p_params);
 588 }
 589
 590 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 591                 struct snd_soc_dai *dai)
 592 {
 593         struct skl_dev *skl = get_skl_ctx(dai->dev);
 594         struct skl_module_cfg *mconfig = NULL;
 595
 596         /* In case of XRUN recovery, reset the FW pipe to clean state */
 597         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 598         if (mconfig && !mconfig->pipe->passthru &&
 599                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 600                 skl_reset_pipe(skl, mconfig->pipe);
 601
 602         return 0;
 603 }
 604
 605 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 606         int cmd, struct snd_soc_dai *dai)
 607 {
 608         struct hdac_ext_stream *link_dev =
 609                                 snd_soc_dai_get_dma_data(dai, substream);
 610         struct hdac_bus *bus = get_bus_ctx(substream);
 611         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 612
 613         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 614         switch (cmd) {
 615         case SNDRV_PCM_TRIGGER_RESUME:
 616         case SNDRV_PCM_TRIGGER_START:
 617         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 618                 snd_hdac_ext_stream_start(link_dev);
 619                 break;
 620
 621         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 622         case SNDRV_PCM_TRIGGER_SUSPEND:
 623         case SNDRV_PCM_TRIGGER_STOP:
 624                 snd_hdac_ext_stream_clear(link_dev);
 625                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 626                         snd_hdac_ext_stream_decouple(bus, stream, false);
 627                 break;
 628
 629         default:
 630                 return -EINVAL;
 631         }
 632         return 0;
 633 }
 634
 635 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 636                 struct snd_soc_dai *dai)
 637 {
 638         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 639         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 640         struct hdac_ext_stream *link_dev =
 641                                 snd_soc_dai_get_dma_data(dai, substream);
 642         struct hdac_ext_link *link;
 643         unsigned char stream_tag;
 644
 645         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 646
 647         link_dev->link_prepared = 0;
 648
 649         link = snd_hdac_ext_bus_get_hlink_by_name(bus, snd_soc_rtd_to_codec(rtd, 0)->component->name);
 650         if (!link)
 651                 return -EINVAL;
 652
 653         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 654                 stream_tag = hdac_stream(link_dev)->stream_tag;
 655                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 656         }
 657
 658         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 659         return 0;
 660 }
 661
 662 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 663         .startup = skl_pcm_open,
 664         .shutdown = skl_pcm_close,
 665         .prepare = skl_pcm_prepare,
 666         .hw_params = skl_pcm_hw_params,
 667         .hw_free = skl_pcm_hw_free,
 668         .trigger = skl_pcm_trigger,
 669 };
 670
 671 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 672         .hw_params = skl_be_hw_params,
 673 };
 674
 675 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 676         .hw_params = skl_be_hw_params,
 677 };
 678
 679 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 680         .prepare = skl_link_pcm_prepare,
 681         .hw_params = skl_link_hw_params,
 682         .hw_free = skl_link_hw_free,
 683         .trigger = skl_link_pcm_trigger,
 684 };
 685
 686 static struct snd_soc_dai_driver skl_fe_dai[] = {
 687 {
 688         .name = "System Pin",
 689         .ops = &skl_pcm_dai_ops,
 690         .playback = {
 691                 .stream_name = "System Playback",
 692                 .channels_min = HDA_MONO,
 693                 .channels_max = HDA_STEREO,
 694                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 695                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 696                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 697                 .sig_bits = 32,
 698         },
 699         .capture = {
 700                 .stream_name = "System Capture",
 701                 .channels_min = HDA_MONO,
 702                 .channels_max = HDA_STEREO,
 703                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 704                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 705                 .sig_bits = 32,
 706         },
 707 },
 708 {
 709         .name = "System Pin2",
 710         .ops = &skl_pcm_dai_ops,
 711         .playback = {
 712                 .stream_name = "Headset Playback",
 713                 .channels_min = HDA_MONO,
 714                 .channels_max = HDA_STEREO,
 715                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 716                         SNDRV_PCM_RATE_8000,
 717                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 718                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 719         },
 720 },
 721 {
 722         .name = "Echoref Pin",
 723         .ops = &skl_pcm_dai_ops,
 724         .capture = {
 725                 .stream_name = "Echoreference Capture",
 726                 .channels_min = HDA_STEREO,
 727                 .channels_max = HDA_STEREO,
 728                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 729                         SNDRV_PCM_RATE_8000,
 730                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 731                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 732         },
 733 },
 734 {
 735         .name = "Reference Pin",
 736         .ops = &skl_pcm_dai_ops,
 737         .capture = {
 738                 .stream_name = "Reference Capture",
 739                 .channels_min = HDA_MONO,
 740                 .channels_max = HDA_QUAD,
 741                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 742                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 743                 .sig_bits = 32,
 744         },
 745 },
 746 {
 747         .name = "Deepbuffer Pin",
 748         .ops = &skl_pcm_dai_ops,
 749         .playback = {
 750                 .stream_name = "Deepbuffer Playback",
 751                 .channels_min = HDA_STEREO,
 752                 .channels_max = HDA_STEREO,
 753                 .rates = SNDRV_PCM_RATE_48000,
 754                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 755                 .sig_bits = 32,
 756         },
 757 },
 758 {
 759         .name = "LowLatency Pin",
 760         .ops = &skl_pcm_dai_ops,
 761         .playback = {
 762                 .stream_name = "Low Latency Playback",
 763                 .channels_min = HDA_STEREO,
 764                 .channels_max = HDA_STEREO,
 765                 .rates = SNDRV_PCM_RATE_48000,
 766                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 767                 .sig_bits = 32,
 768         },
 769 },
 770 {
 771         .name = "DMIC Pin",
 772         .ops = &skl_pcm_dai_ops,
 773         .capture = {
 774                 .stream_name = "DMIC Capture",
 775                 .channels_min = HDA_MONO,
 776                 .channels_max = HDA_QUAD,
 777                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 778                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 779                 .sig_bits = 32,
 780         },
 781 },
 782 {
 783         .name = "HDMI1 Pin",
 784         .ops = &skl_pcm_dai_ops,
 785         .playback = {
 786                 .stream_name = "HDMI1 Playback",
 787                 .channels_min = HDA_STEREO,
 788                 .channels_max = 8,
 789                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 790                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 791                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 792                         SNDRV_PCM_RATE_192000,
 793                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 794                         SNDRV_PCM_FMTBIT_S32_LE,
 795                 .sig_bits = 32,
 796         },
 797 },
 798 {
 799         .name = "HDMI2 Pin",
 800         .ops = &skl_pcm_dai_ops,
 801         .playback = {
 802                 .stream_name = "HDMI2 Playback",
 803                 .channels_min = HDA_STEREO,
 804                 .channels_max = 8,
 805                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 806                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 807                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 808                         SNDRV_PCM_RATE_192000,
 809                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 810                         SNDRV_PCM_FMTBIT_S32_LE,
 811                 .sig_bits = 32,
 812         },
 813 },
 814 {
 815         .name = "HDMI3 Pin",
 816         .ops = &skl_pcm_dai_ops,
 817         .playback = {
 818                 .stream_name = "HDMI3 Playback",
 819                 .channels_min = HDA_STEREO,
 820                 .channels_max = 8,
 821                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 822                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 823                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 824                         SNDRV_PCM_RATE_192000,
 825                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 826                         SNDRV_PCM_FMTBIT_S32_LE,
 827                 .sig_bits = 32,
 828         },
 829 },
 830 };
 831
 832 /* BE CPU  Dais */
 833 static struct snd_soc_dai_driver skl_platform_dai[] = {
 834 {
 835         .name = "SSP0 Pin",
 836         .ops = &skl_be_ssp_dai_ops,
 837         .playback = {
 838                 .stream_name = "ssp0 Tx",
 839                 .channels_min = HDA_STEREO,
 840                 .channels_max = HDA_STEREO,
 841                 .rates = SNDRV_PCM_RATE_48000,
 842                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 843         },
 844         .capture = {
 845                 .stream_name = "ssp0 Rx",
 846                 .channels_min = HDA_STEREO,
 847                 .channels_max = HDA_STEREO,
 848                 .rates = SNDRV_PCM_RATE_48000,
 849                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 850         },
 851 },
 852 {
 853         .name = "SSP1 Pin",
 854         .ops = &skl_be_ssp_dai_ops,
 855         .playback = {
 856                 .stream_name = "ssp1 Tx",
 857                 .channels_min = HDA_STEREO,
 858                 .channels_max = HDA_STEREO,
 859                 .rates = SNDRV_PCM_RATE_48000,
 860                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 861         },
 862         .capture = {
 863                 .stream_name = "ssp1 Rx",
 864                 .channels_min = HDA_STEREO,
 865                 .channels_max = HDA_STEREO,
 866                 .rates = SNDRV_PCM_RATE_48000,
 867                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 868         },
 869 },
 870 {
 871         .name = "SSP2 Pin",
 872         .ops = &skl_be_ssp_dai_ops,
 873         .playback = {
 874                 .stream_name = "ssp2 Tx",
 875                 .channels_min = HDA_STEREO,
 876                 .channels_max = HDA_STEREO,
 877                 .rates = SNDRV_PCM_RATE_48000,
 878                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 879         },
 880         .capture = {
 881                 .stream_name = "ssp2 Rx",
 882                 .channels_min = HDA_STEREO,
 883                 .channels_max = HDA_STEREO,
 884                 .rates = SNDRV_PCM_RATE_48000,
 885                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 886         },
 887 },
 888 {
 889         .name = "SSP3 Pin",
 890         .ops = &skl_be_ssp_dai_ops,
 891         .playback = {
 892                 .stream_name = "ssp3 Tx",
 893                 .channels_min = HDA_STEREO,
 894                 .channels_max = HDA_STEREO,
 895                 .rates = SNDRV_PCM_RATE_48000,
 896                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 897         },
 898         .capture = {
 899                 .stream_name = "ssp3 Rx",
 900                 .channels_min = HDA_STEREO,
 901                 .channels_max = HDA_STEREO,
 902                 .rates = SNDRV_PCM_RATE_48000,
 903                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 904         },
 905 },
 906 {
 907         .name = "SSP4 Pin",
 908         .ops = &skl_be_ssp_dai_ops,
 909         .playback = {
 910                 .stream_name = "ssp4 Tx",
 911                 .channels_min = HDA_STEREO,
 912                 .channels_max = HDA_STEREO,
 913                 .rates = SNDRV_PCM_RATE_48000,
 914                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 915         },
 916         .capture = {
 917                 .stream_name = "ssp4 Rx",
 918                 .channels_min = HDA_STEREO,
 919                 .channels_max = HDA_STEREO,
 920                 .rates = SNDRV_PCM_RATE_48000,
 921                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 922         },
 923 },
 924 {
 925         .name = "SSP5 Pin",
 926         .ops = &skl_be_ssp_dai_ops,
 927         .playback = {
 928                 .stream_name = "ssp5 Tx",
 929                 .channels_min = HDA_STEREO,
 930                 .channels_max = HDA_STEREO,
 931                 .rates = SNDRV_PCM_RATE_48000,
 932                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 933         },
 934         .capture = {
 935                 .stream_name = "ssp5 Rx",
 936                 .channels_min = HDA_STEREO,
 937                 .channels_max = HDA_STEREO,
 938                 .rates = SNDRV_PCM_RATE_48000,
 939                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 940         },
 941 },
 942 {
 943         .name = "iDisp1 Pin",
 944         .ops = &skl_link_dai_ops,
 945         .playback = {
 946                 .stream_name = "iDisp1 Tx",
 947                 .channels_min = HDA_STEREO,
 948                 .channels_max = 8,
 949                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 950                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 951                         SNDRV_PCM_FMTBIT_S24_LE,
 952         },
 953 },
 954 {
 955         .name = "iDisp2 Pin",
 956         .ops = &skl_link_dai_ops,
 957         .playback = {
 958                 .stream_name = "iDisp2 Tx",
 959                 .channels_min = HDA_STEREO,
 960                 .channels_max = 8,
 961                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 962                         SNDRV_PCM_RATE_48000,
 963                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 964                         SNDRV_PCM_FMTBIT_S24_LE,
 965         },
 966 },
 967 {
 968         .name = "iDisp3 Pin",
 969         .ops = &skl_link_dai_ops,
 970         .playback = {
 971                 .stream_name = "iDisp3 Tx",
 972                 .channels_min = HDA_STEREO,
 973                 .channels_max = 8,
 974                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 975                         SNDRV_PCM_RATE_48000,
 976                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 977                         SNDRV_PCM_FMTBIT_S24_LE,
 978         },
 979 },
 980 {
 981         .name = "DMIC01 Pin",
 982         .ops = &skl_dmic_dai_ops,
 983         .capture = {
 984                 .stream_name = "DMIC01 Rx",
 985                 .channels_min = HDA_MONO,
 986                 .channels_max = HDA_QUAD,
 987                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 988                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 989         },
 990 },
 991 {
 992         .name = "DMIC16k Pin",
 993         .ops = &skl_dmic_dai_ops,
 994         .capture = {
 995                 .stream_name = "DMIC16k Rx",
 996                 .channels_min = HDA_MONO,
 997                 .channels_max = HDA_QUAD,
 998                 .rates = SNDRV_PCM_RATE_16000,
 999                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1000         },
1001 },
1002 {
1003         .name = "Analog CPU DAI",
1004         .ops = &skl_link_dai_ops,
1005         .playback = {
1006                 .stream_name = "Analog CPU Playback",
1007                 .channels_min = HDA_MONO,
1008                 .channels_max = HDA_MAX,
1009                 .rates = SNDRV_PCM_RATE_8000_192000,
1010                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1011                         SNDRV_PCM_FMTBIT_S32_LE,
1012         },
1013         .capture = {
1014                 .stream_name = "Analog CPU Capture",
1015                 .channels_min = HDA_MONO,
1016                 .channels_max = HDA_MAX,
1017                 .rates = SNDRV_PCM_RATE_8000_192000,
1018                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1019                         SNDRV_PCM_FMTBIT_S32_LE,
1020         },
1021 },
1022 {
1023         .name = "Alt Analog CPU DAI",
1024         .ops = &skl_link_dai_ops,
1025         .playback = {
1026                 .stream_name = "Alt Analog CPU Playback",
1027                 .channels_min = HDA_MONO,
1028                 .channels_max = HDA_MAX,
1029                 .rates = SNDRV_PCM_RATE_8000_192000,
1030                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1031                         SNDRV_PCM_FMTBIT_S32_LE,
1032         },
1033         .capture = {
1034                 .stream_name = "Alt Analog CPU Capture",
1035                 .channels_min = HDA_MONO,
1036                 .channels_max = HDA_MAX,
1037                 .rates = SNDRV_PCM_RATE_8000_192000,
1038                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1039                         SNDRV_PCM_FMTBIT_S32_LE,
1040         },
1041 },
1042 {
1043         .name = "Digital CPU DAI",
1044         .ops = &skl_link_dai_ops,
1045         .playback = {
1046                 .stream_name = "Digital CPU Playback",
1047                 .channels_min = HDA_MONO,
1048                 .channels_max = HDA_MAX,
1049                 .rates = SNDRV_PCM_RATE_8000_192000,
1050                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1051                         SNDRV_PCM_FMTBIT_S32_LE,
1052         },
1053         .capture = {
1054                 .stream_name = "Digital CPU Capture",
1055                 .channels_min = HDA_MONO,
1056                 .channels_max = HDA_MAX,
1057                 .rates = SNDRV_PCM_RATE_8000_192000,
1058                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1059                         SNDRV_PCM_FMTBIT_S32_LE,
1060         },
1061 },
1062 };
1063
1064 int skl_dai_load(struct snd_soc_component *cmp, int index,
1065                         struct snd_soc_dai_driver *dai_drv,
1066                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1067 {
1068         dai_drv->ops = &skl_pcm_dai_ops;
1069
1070         return 0;
1071 }
1072
1073 static int skl_platform_soc_open(struct snd_soc_component *component,
1074                                  struct snd_pcm_substream *substream)
1075 {
1076         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1077         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1078
1079         dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1080                                         dai_link->cpus->dai_name);
1081
1082         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1083
1084         return 0;
1085 }
1086
1087 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1088                                         int cmd)
1089 {
1090         struct hdac_bus *bus = get_bus_ctx(substream);
1091         struct hdac_ext_stream *stream;
1092         struct snd_pcm_substream *s;
1093         bool start;
1094         int sbits = 0;
1095         unsigned long cookie;
1096         struct hdac_stream *hstr;
1097
1098         stream = get_hdac_ext_stream(substream);
1099         hstr = hdac_stream(stream);
1100
1101         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1102
1103         if (!hstr->prepared)
1104                 return -EPIPE;
1105
1106         switch (cmd) {
1107         case SNDRV_PCM_TRIGGER_START:
1108         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1109         case SNDRV_PCM_TRIGGER_RESUME:
1110                 start = true;
1111                 break;
1112
1113         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1114         case SNDRV_PCM_TRIGGER_SUSPEND:
1115         case SNDRV_PCM_TRIGGER_STOP:
1116                 start = false;
1117                 break;
1118
1119         default:
1120                 return -EINVAL;
1121         }
1122
1123         snd_pcm_group_for_each_entry(s, substream) {
1124                 if (s->pcm->card != substream->pcm->card)
1125                         continue;
1126                 stream = get_hdac_ext_stream(s);
1127                 sbits |= 1 << hdac_stream(stream)->index;
1128                 snd_pcm_trigger_done(s, substream);
1129         }
1130
1131         spin_lock_irqsave(&bus->reg_lock, cookie);
1132
1133         /* first, set SYNC bits of corresponding streams */
1134         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1135
1136         snd_pcm_group_for_each_entry(s, substream) {
1137                 if (s->pcm->card != substream->pcm->card)
1138                         continue;
1139                 stream = get_hdac_ext_stream(s);
1140                 if (start)
1141                         snd_hdac_stream_start(hdac_stream(stream));
1142                 else
1143                         snd_hdac_stream_stop(hdac_stream(stream));
1144         }
1145         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1146
1147         snd_hdac_stream_sync(hstr, start, sbits);
1148
1149         spin_lock_irqsave(&bus->reg_lock, cookie);
1150
1151         /* reset SYNC bits */
1152         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1153         if (start)
1154                 snd_hdac_stream_timecounter_init(hstr, sbits);
1155         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1156
1157         return 0;
1158 }
1159
1160 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1161                                     struct snd_pcm_substream *substream,
1162                                     int cmd)
1163 {
1164         struct hdac_bus *bus = get_bus_ctx(substream);
1165
1166         if (!bus->ppcap)
1167                 return skl_coupled_trigger(substream, cmd);
1168
1169         return 0;
1170 }
1171
1172 static snd_pcm_uframes_t skl_platform_soc_pointer(
1173         struct snd_soc_component *component,
1174         struct snd_pcm_substream *substream)
1175 {
1176         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1177         struct hdac_bus *bus = get_bus_ctx(substream);
1178         unsigned int pos;
1179
1180         /*
1181          * Use DPIB for Playback stream as the periodic DMA Position-in-
1182          * Buffer Writes may be scheduled at the same time or later than
1183          * the MSI and does not guarantee to reflect the Position of the
1184          * last buffer that was transferred. Whereas DPIB register in
1185          * HAD space reflects the actual data that is transferred.
1186          * Use the position buffer for capture, as DPIB write gets
1187          * completed earlier than the actual data written to the DDR.
1188          *
1189          * For capture stream following workaround is required to fix the
1190          * incorrect position reporting.
1191          *
1192          * 1. Wait for 20us before reading the DMA position in buffer once
1193          * the interrupt is generated for stream completion as update happens
1194          * on the HDA frame boundary i.e. 20.833uSec.
1195          * 2. Read DPIB register to flush the DMA position value. This dummy
1196          * read is required to flush DMA position value.
1197          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1198          * or greater than period boundary.
1199          */
1200
1201         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1202                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1203                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1204                                 hdac_stream(hstream)->index));
1205         } else {
1206                 udelay(20);
1207                 readl(bus->remap_addr +
1208                                 AZX_REG_VS_SDXDPIB_XBASE +
1209                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1210                                  hdac_stream(hstream)->index));
1211                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1212         }
1213
1214         if (pos >= hdac_stream(hstream)->bufsize)
1215                 pos = 0;
1216
1217         return bytes_to_frames(substream->runtime, pos);
1218 }
1219
1220 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1221                                 u64 nsec)
1222 {
1223         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1224         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
1225         u64 codec_frames, codec_nsecs;
1226
1227         if (!codec_dai->driver->ops->delay)
1228                 return nsec;
1229
1230         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1231         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1232                               substream->runtime->rate);
1233
1234         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1235                 return nsec + codec_nsecs;
1236
1237         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1238 }
1239
1240 static int skl_platform_soc_get_time_info(
1241                         struct snd_soc_component *component,
1242                         struct snd_pcm_substream *substream,
1243                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1244                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1245                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1246 {
1247         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1248         struct hdac_stream *hstr = hdac_stream(sstream);
1249         u64 nsec;
1250
1251         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1252                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1253
1254                 snd_pcm_gettime(substream->runtime, system_ts);
1255
1256                 nsec = timecounter_read(&hstr->tc);
1257                 if (audio_tstamp_config->report_delay)
1258                         nsec = skl_adjust_codec_delay(substream, nsec);
1259
1260                 *audio_ts = ns_to_timespec64(nsec);
1261
1262                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1263                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1264                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1265
1266         } else {
1267                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1268         }
1269
1270         return 0;
1271 }
1272
1273 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1274
1275 static int skl_platform_soc_new(struct snd_soc_component *component,
1276                                 struct snd_soc_pcm_runtime *rtd)
1277 {
1278         struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1279         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1280         struct snd_pcm *pcm = rtd->pcm;
1281         unsigned int size;
1282         struct skl_dev *skl = bus_to_skl(bus);
1283
1284         if (dai->driver->playback.channels_min ||
1285                 dai->driver->capture.channels_min) {
1286                 /* buffer pre-allocation */
1287                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1288                 if (size > MAX_PREALLOC_SIZE)
1289                         size = MAX_PREALLOC_SIZE;
1290                 snd_pcm_set_managed_buffer_all(pcm,
1291                                                SNDRV_DMA_TYPE_DEV_SG,
1292                                                &skl->pci->dev,
1293                                                size, MAX_PREALLOC_SIZE);
1294         }
1295
1296         return 0;
1297 }
1298
1299 static int skl_get_module_info(struct skl_dev *skl,
1300                 struct skl_module_cfg *mconfig)
1301 {
1302         struct skl_module_inst_id *pin_id;
1303         guid_t *uuid_mod, *uuid_tplg;
1304         struct skl_module *skl_module;
1305         struct uuid_module *module;
1306         int i, ret = -EIO;
1307
1308         uuid_mod = (guid_t *)mconfig->guid;
1309
1310         if (list_empty(&skl->uuid_list)) {
1311                 dev_err(skl->dev, "Module list is empty\n");
1312                 return -EIO;
1313         }
1314
1315         for (i = 0; i < skl->nr_modules; i++) {
1316                 skl_module = skl->modules[i];
1317                 uuid_tplg = &skl_module->uuid;
1318                 if (guid_equal(uuid_mod, uuid_tplg)) {
1319                         mconfig->module = skl_module;
1320                         ret = 0;
1321                         break;
1322                 }
1323         }
1324
1325         if (skl->nr_modules && ret)
1326                 return ret;
1327
1328         ret = -EIO;
1329         list_for_each_entry(module, &skl->uuid_list, list) {
1330                 if (guid_equal(uuid_mod, &module->uuid)) {
1331                         mconfig->id.module_id = module->id;
1332                         mconfig->module->loadable = module->is_loadable;
1333                         ret = 0;
1334                 }
1335
1336                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1337                         pin_id = &mconfig->m_in_pin[i].id;
1338                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1339                                 pin_id->module_id = module->id;
1340                 }
1341
1342                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1343                         pin_id = &mconfig->m_out_pin[i].id;
1344                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1345                                 pin_id->module_id = module->id;
1346                 }
1347         }
1348
1349         return ret;
1350 }
1351
1352 static int skl_populate_modules(struct skl_dev *skl)
1353 {
1354         struct skl_pipeline *p;
1355         struct skl_pipe_module *m;
1356         struct snd_soc_dapm_widget *w;
1357         struct skl_module_cfg *mconfig;
1358         int ret = 0;
1359
1360         list_for_each_entry(p, &skl->ppl_list, node) {
1361                 list_for_each_entry(m, &p->pipe->w_list, node) {
1362                         w = m->w;
1363                         mconfig = w->priv;
1364
1365                         ret = skl_get_module_info(skl, mconfig);
1366                         if (ret < 0) {
1367                                 dev_err(skl->dev,
1368                                         "query module info failed\n");
1369                                 return ret;
1370                         }
1371
1372                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1373                 }
1374         }
1375
1376         return ret;
1377 }
1378
1379 static int skl_platform_soc_probe(struct snd_soc_component *component)
1380 {
1381         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1382         struct skl_dev *skl = bus_to_skl(bus);
1383         const struct skl_dsp_ops *ops;
1384         int ret;
1385
1386         ret = pm_runtime_resume_and_get(component->dev);
1387         if (ret < 0 && ret != -EACCES)
1388                 return ret;
1389
1390         if (bus->ppcap) {
1391                 skl->component = component;
1392
1393                 /* init debugfs */
1394                 skl->debugfs = skl_debugfs_init(skl);
1395
1396                 ret = skl_tplg_init(component, bus);
1397                 if (ret < 0) {
1398                         dev_err(component->dev, "Failed to init topology!\n");
1399                         return ret;
1400                 }
1401
1402                 /* load the firmwares, since all is set */
1403                 ops = skl_get_dsp_ops(skl->pci->device);
1404                 if (!ops)
1405                         return -EIO;
1406
1407                 /*
1408                  * Disable dynamic clock and power gating during firmware
1409                  * and library download
1410                  */
1411                 skl->enable_miscbdcge(component->dev, false);
1412                 skl->clock_power_gating(component->dev, false);
1413
1414                 ret = ops->init_fw(component->dev, skl);
1415                 skl->enable_miscbdcge(component->dev, true);
1416                 skl->clock_power_gating(component->dev, true);
1417                 if (ret < 0) {
1418                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1419                         return ret;
1420                 }
1421                 skl_populate_modules(skl);
1422                 skl->update_d0i3c = skl_update_d0i3c;
1423
1424                 if (skl->cfg.astate_cfg != NULL) {
1425                         skl_dsp_set_astate_cfg(skl,
1426                                         skl->cfg.astate_cfg->count,
1427                                         skl->cfg.astate_cfg);
1428                 }
1429         }
1430         pm_runtime_mark_last_busy(component->dev);
1431         pm_runtime_put_autosuspend(component->dev);
1432
1433         return 0;
1434 }
1435
1436 static void skl_platform_soc_remove(struct snd_soc_component *component)
1437 {
1438         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1439         struct skl_dev *skl = bus_to_skl(bus);
1440
1441         skl_tplg_exit(component, bus);
1442
1443         skl_debugfs_exit(skl);
1444 }
1445
1446 static const struct snd_soc_component_driver skl_component  = {
1447         .name           = "pcm",
1448         .probe          = skl_platform_soc_probe,
1449         .remove         = skl_platform_soc_remove,
1450         .open           = skl_platform_soc_open,
1451         .trigger        = skl_platform_soc_trigger,
1452         .pointer        = skl_platform_soc_pointer,
1453         .get_time_info  = skl_platform_soc_get_time_info,
1454         .pcm_construct  = skl_platform_soc_new,
1455         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1456 };
1457
1458 int skl_platform_register(struct device *dev)
1459 {
1460         int ret;
1461         struct snd_soc_dai_driver *dais;
1462         int num_dais = ARRAY_SIZE(skl_platform_dai);
1463         struct hdac_bus *bus = dev_get_drvdata(dev);
1464         struct skl_dev *skl = bus_to_skl(bus);
1465
1466         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1467                             GFP_KERNEL);
1468         if (!skl->dais) {
1469                 ret = -ENOMEM;
1470                 goto err;
1471         }
1472
1473         if (!skl->use_tplg_pcm) {
1474                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1475                                 sizeof(skl_platform_dai), GFP_KERNEL);
1476                 if (!dais) {
1477                         ret = -ENOMEM;
1478                         goto err;
1479                 }
1480
1481                 skl->dais = dais;
1482                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1483                        sizeof(skl_fe_dai));
1484                 num_dais += ARRAY_SIZE(skl_fe_dai);
1485         }
1486
1487         ret = devm_snd_soc_register_component(dev, &skl_component,
1488                                          skl->dais, num_dais);
1489         if (ret)
1490                 dev_err(dev, "soc component registration failed %d\n", ret);
1491 err:
1492         return ret;
1493 }
1494
1495 int skl_platform_unregister(struct device *dev)
1496 {
1497         struct hdac_bus *bus = dev_get_drvdata(dev);
1498         struct skl_dev *skl = bus_to_skl(bus);
1499         struct skl_module_deferred_bind *modules, *tmp;
1500
1501         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1502                 list_del(&modules->node);
1503                 kfree(modules);
1504         }
1505
1506         kfree(skl->dais);
1507
1508         return 0;
1509 }