sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/hdaudio.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc.h>
  19 #include "skl.h"
  20 #include "skl-topology.h"
  21 #include "skl-sst-dsp.h"
  22 #include "skl-sst-ipc.h"
  23
  24 #define HDA_MONO 1
  25 #define HDA_STEREO 2
  26 #define HDA_QUAD 4
  27 #define HDA_MAX 8
  28
  29 static const struct snd_pcm_hardware azx_pcm_hw = {
  30         .info =                 (SNDRV_PCM_INFO_MMAP |
  31                                  SNDRV_PCM_INFO_INTERLEAVED |
  32                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  33                                  SNDRV_PCM_INFO_MMAP_VALID |
  34                                  SNDRV_PCM_INFO_PAUSE |
  35                                  SNDRV_PCM_INFO_RESUME |
  36                                  SNDRV_PCM_INFO_SYNC_START |
  37                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  38                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  39                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  40         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  41                                 SNDRV_PCM_FMTBIT_S32_LE |
  42                                 SNDRV_PCM_FMTBIT_S24_LE,
  43         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  44                                 SNDRV_PCM_RATE_8000,
  45         .rate_min =             8000,
  46         .rate_max =             48000,
  47         .channels_min =         1,
  48         .channels_max =         8,
  49         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  50         .period_bytes_min =     128,
  51         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  52         .periods_min =          2,
  53         .periods_max =          AZX_MAX_FRAG,
  54         .fifo_size =            0,
  55 };
  56
  57 static inline
  58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  59 {
  60         return substream->runtime->private_data;
  61 }
  62
  63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  64 {
  65         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  66         struct hdac_stream *hstream = hdac_stream(stream);
  67         struct hdac_bus *bus = hstream->bus;
  68         return bus;
  69 }
  70
  71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  72                                  struct snd_pcm_substream *substream,
  73                                  size_t size)
  74 {
  75         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  76
  77         hdac_stream(stream)->bufsize = 0;
  78         hdac_stream(stream)->period_bytes = 0;
  79         hdac_stream(stream)->format_val = 0;
  80
  81         return 0;
  82 }
  83
  84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  85                                  struct snd_pcm_runtime *runtime)
  86 {
  87         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  88
  89         /* avoid wrap-around with wall-clock */
  90         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  91                                      20, 178000000);
  92 }
  93
  94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  95 {
  96         if (bus->ppcap)
  97                 return HDAC_EXT_STREAM_TYPE_HOST;
  98         else
  99                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 100 }
 101
 102 /*
 103  * check if the stream opened is marked as ignore_suspend by machine, if so
 104  * then enable suspend_active refcount
 105  *
 106  * The count supend_active does not need lock as it is used in open/close
 107  * and suspend context
 108  */
 109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 110                                          struct snd_soc_dai *dai, bool enable)
 111 {
 112         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 113         struct snd_soc_dapm_widget *w;
 114         struct skl_dev *skl = bus_to_skl(bus);
 115
 116         w = snd_soc_dai_get_widget(dai, substream->stream);
 117
 118         if (w->ignore_suspend && enable)
 119                 skl->supend_active++;
 120         else if (w->ignore_suspend && !enable)
 121                 skl->supend_active--;
 122 }
 123
 124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dev);
 127         unsigned int format_val;
 128         struct hdac_stream *hstream;
 129         struct hdac_ext_stream *stream;
 130         int err;
 131
 132         hstream = snd_hdac_get_stream(bus, params->stream,
 133                                         params->host_dma_id + 1);
 134         if (!hstream)
 135                 return -EINVAL;
 136
 137         stream = stream_to_hdac_ext_stream(hstream);
 138         snd_hdac_ext_stream_decouple(bus, stream, true);
 139
 140         format_val = snd_hdac_calc_stream_format(params->s_freq,
 141                         params->ch, params->format, params->host_bps, 0);
 142
 143         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 144                 format_val, params->s_freq, params->ch, params->format);
 145
 146         snd_hdac_stream_reset(hdac_stream(stream));
 147         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 148         if (err < 0)
 149                 return err;
 150
 151         err = snd_hdac_ext_host_stream_setup(stream, false);
 152         if (err < 0)
 153                 return err;
 154
 155         hdac_stream(stream)->prepared = 1;
 156
 157         return 0;
 158 }
 159
 160 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 161 {
 162         struct hdac_bus *bus = dev_get_drvdata(dev);
 163         unsigned int format_val;
 164         struct hdac_stream *hstream;
 165         struct hdac_ext_stream *stream;
 166         struct hdac_ext_link *link;
 167         unsigned char stream_tag;
 168
 169         hstream = snd_hdac_get_stream(bus, params->stream,
 170                                         params->link_dma_id + 1);
 171         if (!hstream)
 172                 return -EINVAL;
 173
 174         stream = stream_to_hdac_ext_stream(hstream);
 175         snd_hdac_ext_stream_decouple(bus, stream, true);
 176         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 177                                         params->format, params->link_bps, 0);
 178
 179         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 180                 format_val, params->s_freq, params->ch, params->format);
 181
 182         snd_hdac_ext_stream_reset(stream);
 183
 184         snd_hdac_ext_stream_setup(stream, format_val);
 185
 186         stream_tag = hstream->stream_tag;
 187         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 188                 list_for_each_entry(link, &bus->hlink_list, list) {
 189                         if (link->index == params->link_index)
 190                                 snd_hdac_ext_bus_link_set_stream_id(link,
 191                                                                     stream_tag);
 192                 }
 193         }
 194
 195         stream->link_prepared = 1;
 196
 197         return 0;
 198 }
 199
 200 static int skl_pcm_open(struct snd_pcm_substream *substream,
 201                 struct snd_soc_dai *dai)
 202 {
 203         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 204         struct hdac_ext_stream *stream;
 205         struct snd_pcm_runtime *runtime = substream->runtime;
 206         struct skl_dma_params *dma_params;
 207         struct skl_dev *skl = get_skl_ctx(dai->dev);
 208         struct skl_module_cfg *mconfig;
 209
 210         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 211
 212         stream = snd_hdac_ext_stream_assign(bus, substream,
 213                                         skl_get_host_stream_type(bus));
 214         if (stream == NULL)
 215                 return -EBUSY;
 216
 217         skl_set_pcm_constrains(bus, runtime);
 218
 219         /*
 220          * disable WALLCLOCK timestamps for capture streams
 221          * until we figure out how to handle digital inputs
 222          */
 223         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 224                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 225                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 226         }
 227
 228         runtime->private_data = stream;
 229
 230         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 231         if (!dma_params)
 232                 return -ENOMEM;
 233
 234         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 235         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 236
 237         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 238                                  dma_params->stream_tag);
 239         skl_set_suspend_active(substream, dai, true);
 240         snd_pcm_set_sync(substream);
 241
 242         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 243         if (!mconfig)
 244                 return -EINVAL;
 245
 246         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 247
 248         return 0;
 249 }
 250
 251 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 252                 struct snd_soc_dai *dai)
 253 {
 254         struct skl_dev *skl = get_skl_ctx(dai->dev);
 255         struct skl_module_cfg *mconfig;
 256         int ret;
 257
 258         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 259
 260         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 261
 262         /*
 263          * In case of XRUN recovery or in the case when the application
 264          * calls prepare another time, reset the FW pipe to clean state
 265          */
 266         if (mconfig &&
 267                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 268                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 269                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 270
 271                 ret = skl_reset_pipe(skl, mconfig->pipe);
 272
 273                 if (ret < 0)
 274                         return ret;
 275
 276                 ret = skl_pcm_host_dma_prepare(dai->dev,
 277                                         mconfig->pipe->p_params);
 278                 if (ret < 0)
 279                         return ret;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 286                                 struct snd_pcm_hw_params *params,
 287                                 struct snd_soc_dai *dai)
 288 {
 289         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 290         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 291         struct snd_pcm_runtime *runtime = substream->runtime;
 292         struct skl_pipe_params p_params = {0};
 293         struct skl_module_cfg *m_cfg;
 294         int ret, dma_id;
 295
 296         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 297         ret = skl_substream_alloc_pages(bus, substream,
 298                                           params_buffer_bytes(params));
 299         if (ret < 0)
 300                 return ret;
 301
 302         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 303                         runtime->rate, runtime->channels, runtime->format);
 304
 305         dma_id = hdac_stream(stream)->stream_tag - 1;
 306         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 307
 308         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 309         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 310         p_params.ch = params_channels(params);
 311         p_params.s_freq = params_rate(params);
 312         p_params.host_dma_id = dma_id;
 313         p_params.stream = substream->stream;
 314         p_params.format = params_format(params);
 315         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 316                 p_params.host_bps = dai->driver->playback.sig_bits;
 317         else
 318                 p_params.host_bps = dai->driver->capture.sig_bits;
 319
 320
 321         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 322         if (m_cfg)
 323                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 324
 325         return 0;
 326 }
 327
 328 static void skl_pcm_close(struct snd_pcm_substream *substream,
 329                 struct snd_soc_dai *dai)
 330 {
 331         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 332         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 333         struct skl_dma_params *dma_params = NULL;
 334         struct skl_dev *skl = bus_to_skl(bus);
 335         struct skl_module_cfg *mconfig;
 336
 337         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 338
 339         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 340
 341         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 342         /*
 343          * now we should set this to NULL as we are freeing by the
 344          * dma_params
 345          */
 346         snd_soc_dai_set_dma_data(dai, substream, NULL);
 347         skl_set_suspend_active(substream, dai, false);
 348
 349         /*
 350          * check if close is for "Reference Pin" and set back the
 351          * CGCTL.MISCBDCGE if disabled by driver
 352          */
 353         if (!strncmp(dai->name, "Reference Pin", 13) &&
 354                         skl->miscbdcg_disabled) {
 355                 skl->enable_miscbdcge(dai->dev, true);
 356                 skl->miscbdcg_disabled = false;
 357         }
 358
 359         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 360         if (mconfig)
 361                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 362
 363         kfree(dma_params);
 364 }
 365
 366 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 367                 struct snd_soc_dai *dai)
 368 {
 369         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 370         struct skl_dev *skl = get_skl_ctx(dai->dev);
 371         struct skl_module_cfg *mconfig;
 372         int ret;
 373
 374         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 375
 376         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 377
 378         if (mconfig) {
 379                 ret = skl_reset_pipe(skl, mconfig->pipe);
 380                 if (ret < 0)
 381                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 382                                                 __func__, ret);
 383         }
 384
 385         snd_hdac_stream_cleanup(hdac_stream(stream));
 386         hdac_stream(stream)->prepared = 0;
 387
 388         return 0;
 389 }
 390
 391 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 392                                 struct snd_pcm_hw_params *params,
 393                                 struct snd_soc_dai *dai)
 394 {
 395         struct skl_pipe_params p_params = {0};
 396
 397         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 398         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 399         p_params.ch = params_channels(params);
 400         p_params.s_freq = params_rate(params);
 401         p_params.stream = substream->stream;
 402
 403         return skl_tplg_be_update_params(dai, &p_params);
 404 }
 405
 406 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 407                 int cmd)
 408 {
 409         struct hdac_bus *bus = get_bus_ctx(substream);
 410         struct hdac_ext_stream *stream;
 411         int start;
 412         unsigned long cookie;
 413         struct hdac_stream *hstr;
 414
 415         stream = get_hdac_ext_stream(substream);
 416         hstr = hdac_stream(stream);
 417
 418         if (!hstr->prepared)
 419                 return -EPIPE;
 420
 421         switch (cmd) {
 422         case SNDRV_PCM_TRIGGER_START:
 423         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 424         case SNDRV_PCM_TRIGGER_RESUME:
 425                 start = 1;
 426                 break;
 427
 428         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 429         case SNDRV_PCM_TRIGGER_SUSPEND:
 430         case SNDRV_PCM_TRIGGER_STOP:
 431                 start = 0;
 432                 break;
 433
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         spin_lock_irqsave(&bus->reg_lock, cookie);
 439
 440         if (start) {
 441                 snd_hdac_stream_start(hdac_stream(stream));
 442                 snd_hdac_stream_timecounter_init(hstr, 0);
 443         } else {
 444                 snd_hdac_stream_stop(hdac_stream(stream));
 445         }
 446
 447         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 448
 449         return 0;
 450 }
 451
 452 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 453                 struct snd_soc_dai *dai)
 454 {
 455         struct skl_dev *skl = get_skl_ctx(dai->dev);
 456         struct skl_module_cfg *mconfig;
 457         struct hdac_bus *bus = get_bus_ctx(substream);
 458         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 459         struct hdac_stream *hstream = hdac_stream(stream);
 460         struct snd_soc_dapm_widget *w;
 461         int ret;
 462
 463         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 464         if (!mconfig)
 465                 return -EIO;
 466
 467         w = snd_soc_dai_get_widget(dai, substream->stream);
 468
 469         switch (cmd) {
 470         case SNDRV_PCM_TRIGGER_RESUME:
 471                 if (!w->ignore_suspend) {
 472                         /*
 473                          * enable DMA Resume enable bit for the stream, set the
 474                          * dpib & lpib position to resume before starting the
 475                          * DMA
 476                          */
 477                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 478                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 479                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 480                 }
 481                 fallthrough;
 482
 483         case SNDRV_PCM_TRIGGER_START:
 484         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 485                 /*
 486                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 487                  * there are no underrun/overrun in the case when the FE
 488                  * pipeline is started but there is a delay in starting the
 489                  * DMA channel on the host.
 490                  */
 491                 ret = skl_decoupled_trigger(substream, cmd);
 492                 if (ret < 0)
 493                         return ret;
 494                 return skl_run_pipe(skl, mconfig->pipe);
 495
 496         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 497         case SNDRV_PCM_TRIGGER_SUSPEND:
 498         case SNDRV_PCM_TRIGGER_STOP:
 499                 /*
 500                  * Stop FE Pipe first and stop DMA. This is to make sure that
 501                  * there are no underrun/overrun in the case if there is a delay
 502                  * between the two operations.
 503                  */
 504                 ret = skl_stop_pipe(skl, mconfig->pipe);
 505                 if (ret < 0)
 506                         return ret;
 507
 508                 ret = skl_decoupled_trigger(substream, cmd);
 509                 if (ret < 0)
 510                         return ret;
 511
 512                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 513                         /* save the dpib and lpib positions */
 514                         hstream->dpib = readl(bus->remap_addr +
 515                                         AZX_REG_VS_SDXDPIB_XBASE +
 516                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 517                                         hstream->index));
 518
 519                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 520
 521                         snd_hdac_ext_stream_decouple(bus, stream, false);
 522                 }
 523                 break;
 524
 525         default:
 526                 return -EINVAL;
 527         }
 528
 529         return 0;
 530 }
 531
 532
 533 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 534                                 struct snd_pcm_hw_params *params,
 535                                 struct snd_soc_dai *dai)
 536 {
 537         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 538         struct hdac_ext_stream *link_dev;
 539         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 540         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
 541         struct skl_pipe_params p_params = {0};
 542         struct hdac_ext_link *link;
 543         int stream_tag;
 544
 545         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 546                                         HDAC_EXT_STREAM_TYPE_LINK);
 547         if (!link_dev)
 548                 return -EBUSY;
 549
 550         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 551
 552         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 553         if (!link)
 554                 return -EINVAL;
 555
 556         stream_tag = hdac_stream(link_dev)->stream_tag;
 557
 558         /* set the hdac_stream in the codec dai */
 559         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 560
 561         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 562         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 563         p_params.ch = params_channels(params);
 564         p_params.s_freq = params_rate(params);
 565         p_params.stream = substream->stream;
 566         p_params.link_dma_id = stream_tag - 1;
 567         p_params.link_index = link->index;
 568         p_params.format = params_format(params);
 569
 570         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 571                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 572         else
 573                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 574
 575         return skl_tplg_be_update_params(dai, &p_params);
 576 }
 577
 578 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 579                 struct snd_soc_dai *dai)
 580 {
 581         struct skl_dev *skl = get_skl_ctx(dai->dev);
 582         struct skl_module_cfg *mconfig = NULL;
 583
 584         /* In case of XRUN recovery, reset the FW pipe to clean state */
 585         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 586         if (mconfig && !mconfig->pipe->passthru &&
 587                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 588                 skl_reset_pipe(skl, mconfig->pipe);
 589
 590         return 0;
 591 }
 592
 593 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 594         int cmd, struct snd_soc_dai *dai)
 595 {
 596         struct hdac_ext_stream *link_dev =
 597                                 snd_soc_dai_get_dma_data(dai, substream);
 598         struct hdac_bus *bus = get_bus_ctx(substream);
 599         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 600
 601         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 602         switch (cmd) {
 603         case SNDRV_PCM_TRIGGER_RESUME:
 604         case SNDRV_PCM_TRIGGER_START:
 605         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 606                 snd_hdac_ext_stream_start(link_dev);
 607                 break;
 608
 609         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 610         case SNDRV_PCM_TRIGGER_SUSPEND:
 611         case SNDRV_PCM_TRIGGER_STOP:
 612                 snd_hdac_ext_stream_clear(link_dev);
 613                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 614                         snd_hdac_ext_stream_decouple(bus, stream, false);
 615                 break;
 616
 617         default:
 618                 return -EINVAL;
 619         }
 620         return 0;
 621 }
 622
 623 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 624                 struct snd_soc_dai *dai)
 625 {
 626         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 627         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 628         struct hdac_ext_stream *link_dev =
 629                                 snd_soc_dai_get_dma_data(dai, substream);
 630         struct hdac_ext_link *link;
 631         unsigned char stream_tag;
 632
 633         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 634
 635         link_dev->link_prepared = 0;
 636
 637         link = snd_hdac_ext_bus_get_hlink_by_name(bus, snd_soc_rtd_to_codec(rtd, 0)->component->name);
 638         if (!link)
 639                 return -EINVAL;
 640
 641         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 642                 stream_tag = hdac_stream(link_dev)->stream_tag;
 643                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 644         }
 645
 646         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 647         return 0;
 648 }
 649
 650 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 651         .startup = skl_pcm_open,
 652         .shutdown = skl_pcm_close,
 653         .prepare = skl_pcm_prepare,
 654         .hw_params = skl_pcm_hw_params,
 655         .hw_free = skl_pcm_hw_free,
 656         .trigger = skl_pcm_trigger,
 657 };
 658
 659 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 660         .hw_params = skl_be_hw_params,
 661 };
 662
 663 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 664         .hw_params = skl_be_hw_params,
 665 };
 666
 667 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 668         .prepare = skl_link_pcm_prepare,
 669         .hw_params = skl_link_hw_params,
 670         .hw_free = skl_link_hw_free,
 671         .trigger = skl_link_pcm_trigger,
 672 };
 673
 674 static struct snd_soc_dai_driver skl_fe_dai[] = {
 675 {
 676         .name = "System Pin",
 677         .ops = &skl_pcm_dai_ops,
 678         .playback = {
 679                 .stream_name = "System Playback",
 680                 .channels_min = HDA_MONO,
 681                 .channels_max = HDA_STEREO,
 682                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 683                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 684                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 685                 .sig_bits = 32,
 686         },
 687         .capture = {
 688                 .stream_name = "System Capture",
 689                 .channels_min = HDA_MONO,
 690                 .channels_max = HDA_STEREO,
 691                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 692                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 693                 .sig_bits = 32,
 694         },
 695 },
 696 {
 697         .name = "System Pin2",
 698         .ops = &skl_pcm_dai_ops,
 699         .playback = {
 700                 .stream_name = "Headset Playback",
 701                 .channels_min = HDA_MONO,
 702                 .channels_max = HDA_STEREO,
 703                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 704                         SNDRV_PCM_RATE_8000,
 705                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 706                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 707         },
 708 },
 709 {
 710         .name = "Echoref Pin",
 711         .ops = &skl_pcm_dai_ops,
 712         .capture = {
 713                 .stream_name = "Echoreference Capture",
 714                 .channels_min = HDA_STEREO,
 715                 .channels_max = HDA_STEREO,
 716                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 717                         SNDRV_PCM_RATE_8000,
 718                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 719                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 720         },
 721 },
 722 {
 723         .name = "Reference Pin",
 724         .ops = &skl_pcm_dai_ops,
 725         .capture = {
 726                 .stream_name = "Reference Capture",
 727                 .channels_min = HDA_MONO,
 728                 .channels_max = HDA_QUAD,
 729                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 730                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 731                 .sig_bits = 32,
 732         },
 733 },
 734 {
 735         .name = "Deepbuffer Pin",
 736         .ops = &skl_pcm_dai_ops,
 737         .playback = {
 738                 .stream_name = "Deepbuffer Playback",
 739                 .channels_min = HDA_STEREO,
 740                 .channels_max = HDA_STEREO,
 741                 .rates = SNDRV_PCM_RATE_48000,
 742                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 743                 .sig_bits = 32,
 744         },
 745 },
 746 {
 747         .name = "LowLatency Pin",
 748         .ops = &skl_pcm_dai_ops,
 749         .playback = {
 750                 .stream_name = "Low Latency Playback",
 751                 .channels_min = HDA_STEREO,
 752                 .channels_max = HDA_STEREO,
 753                 .rates = SNDRV_PCM_RATE_48000,
 754                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 755                 .sig_bits = 32,
 756         },
 757 },
 758 {
 759         .name = "DMIC Pin",
 760         .ops = &skl_pcm_dai_ops,
 761         .capture = {
 762                 .stream_name = "DMIC Capture",
 763                 .channels_min = HDA_MONO,
 764                 .channels_max = HDA_QUAD,
 765                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 766                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 767                 .sig_bits = 32,
 768         },
 769 },
 770 {
 771         .name = "HDMI1 Pin",
 772         .ops = &skl_pcm_dai_ops,
 773         .playback = {
 774                 .stream_name = "HDMI1 Playback",
 775                 .channels_min = HDA_STEREO,
 776                 .channels_max = 8,
 777                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 778                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 779                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 780                         SNDRV_PCM_RATE_192000,
 781                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 782                         SNDRV_PCM_FMTBIT_S32_LE,
 783                 .sig_bits = 32,
 784         },
 785 },
 786 {
 787         .name = "HDMI2 Pin",
 788         .ops = &skl_pcm_dai_ops,
 789         .playback = {
 790                 .stream_name = "HDMI2 Playback",
 791                 .channels_min = HDA_STEREO,
 792                 .channels_max = 8,
 793                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 794                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 795                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 796                         SNDRV_PCM_RATE_192000,
 797                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 798                         SNDRV_PCM_FMTBIT_S32_LE,
 799                 .sig_bits = 32,
 800         },
 801 },
 802 {
 803         .name = "HDMI3 Pin",
 804         .ops = &skl_pcm_dai_ops,
 805         .playback = {
 806                 .stream_name = "HDMI3 Playback",
 807                 .channels_min = HDA_STEREO,
 808                 .channels_max = 8,
 809                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 810                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 811                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 812                         SNDRV_PCM_RATE_192000,
 813                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 814                         SNDRV_PCM_FMTBIT_S32_LE,
 815                 .sig_bits = 32,
 816         },
 817 },
 818 };
 819
 820 /* BE CPU  Dais */
 821 static struct snd_soc_dai_driver skl_platform_dai[] = {
 822 {
 823         .name = "SSP0 Pin",
 824         .ops = &skl_be_ssp_dai_ops,
 825         .playback = {
 826                 .stream_name = "ssp0 Tx",
 827                 .channels_min = HDA_STEREO,
 828                 .channels_max = HDA_STEREO,
 829                 .rates = SNDRV_PCM_RATE_48000,
 830                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 831         },
 832         .capture = {
 833                 .stream_name = "ssp0 Rx",
 834                 .channels_min = HDA_STEREO,
 835                 .channels_max = HDA_STEREO,
 836                 .rates = SNDRV_PCM_RATE_48000,
 837                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 838         },
 839 },
 840 {
 841         .name = "SSP1 Pin",
 842         .ops = &skl_be_ssp_dai_ops,
 843         .playback = {
 844                 .stream_name = "ssp1 Tx",
 845                 .channels_min = HDA_STEREO,
 846                 .channels_max = HDA_STEREO,
 847                 .rates = SNDRV_PCM_RATE_48000,
 848                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 849         },
 850         .capture = {
 851                 .stream_name = "ssp1 Rx",
 852                 .channels_min = HDA_STEREO,
 853                 .channels_max = HDA_STEREO,
 854                 .rates = SNDRV_PCM_RATE_48000,
 855                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 856         },
 857 },
 858 {
 859         .name = "SSP2 Pin",
 860         .ops = &skl_be_ssp_dai_ops,
 861         .playback = {
 862                 .stream_name = "ssp2 Tx",
 863                 .channels_min = HDA_STEREO,
 864                 .channels_max = HDA_STEREO,
 865                 .rates = SNDRV_PCM_RATE_48000,
 866                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 867         },
 868         .capture = {
 869                 .stream_name = "ssp2 Rx",
 870                 .channels_min = HDA_STEREO,
 871                 .channels_max = HDA_STEREO,
 872                 .rates = SNDRV_PCM_RATE_48000,
 873                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 874         },
 875 },
 876 {
 877         .name = "SSP3 Pin",
 878         .ops = &skl_be_ssp_dai_ops,
 879         .playback = {
 880                 .stream_name = "ssp3 Tx",
 881                 .channels_min = HDA_STEREO,
 882                 .channels_max = HDA_STEREO,
 883                 .rates = SNDRV_PCM_RATE_48000,
 884                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 885         },
 886         .capture = {
 887                 .stream_name = "ssp3 Rx",
 888                 .channels_min = HDA_STEREO,
 889                 .channels_max = HDA_STEREO,
 890                 .rates = SNDRV_PCM_RATE_48000,
 891                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 892         },
 893 },
 894 {
 895         .name = "SSP4 Pin",
 896         .ops = &skl_be_ssp_dai_ops,
 897         .playback = {
 898                 .stream_name = "ssp4 Tx",
 899                 .channels_min = HDA_STEREO,
 900                 .channels_max = HDA_STEREO,
 901                 .rates = SNDRV_PCM_RATE_48000,
 902                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 903         },
 904         .capture = {
 905                 .stream_name = "ssp4 Rx",
 906                 .channels_min = HDA_STEREO,
 907                 .channels_max = HDA_STEREO,
 908                 .rates = SNDRV_PCM_RATE_48000,
 909                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 910         },
 911 },
 912 {
 913         .name = "SSP5 Pin",
 914         .ops = &skl_be_ssp_dai_ops,
 915         .playback = {
 916                 .stream_name = "ssp5 Tx",
 917                 .channels_min = HDA_STEREO,
 918                 .channels_max = HDA_STEREO,
 919                 .rates = SNDRV_PCM_RATE_48000,
 920                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 921         },
 922         .capture = {
 923                 .stream_name = "ssp5 Rx",
 924                 .channels_min = HDA_STEREO,
 925                 .channels_max = HDA_STEREO,
 926                 .rates = SNDRV_PCM_RATE_48000,
 927                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 928         },
 929 },
 930 {
 931         .name = "iDisp1 Pin",
 932         .ops = &skl_link_dai_ops,
 933         .playback = {
 934                 .stream_name = "iDisp1 Tx",
 935                 .channels_min = HDA_STEREO,
 936                 .channels_max = 8,
 937                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 938                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 939                         SNDRV_PCM_FMTBIT_S24_LE,
 940         },
 941 },
 942 {
 943         .name = "iDisp2 Pin",
 944         .ops = &skl_link_dai_ops,
 945         .playback = {
 946                 .stream_name = "iDisp2 Tx",
 947                 .channels_min = HDA_STEREO,
 948                 .channels_max = 8,
 949                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 950                         SNDRV_PCM_RATE_48000,
 951                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 952                         SNDRV_PCM_FMTBIT_S24_LE,
 953         },
 954 },
 955 {
 956         .name = "iDisp3 Pin",
 957         .ops = &skl_link_dai_ops,
 958         .playback = {
 959                 .stream_name = "iDisp3 Tx",
 960                 .channels_min = HDA_STEREO,
 961                 .channels_max = 8,
 962                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 963                         SNDRV_PCM_RATE_48000,
 964                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 965                         SNDRV_PCM_FMTBIT_S24_LE,
 966         },
 967 },
 968 {
 969         .name = "DMIC01 Pin",
 970         .ops = &skl_dmic_dai_ops,
 971         .capture = {
 972                 .stream_name = "DMIC01 Rx",
 973                 .channels_min = HDA_MONO,
 974                 .channels_max = HDA_QUAD,
 975                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 976                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 977         },
 978 },
 979 {
 980         .name = "DMIC16k Pin",
 981         .ops = &skl_dmic_dai_ops,
 982         .capture = {
 983                 .stream_name = "DMIC16k Rx",
 984                 .channels_min = HDA_MONO,
 985                 .channels_max = HDA_QUAD,
 986                 .rates = SNDRV_PCM_RATE_16000,
 987                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 988         },
 989 },
 990 {
 991         .name = "Analog CPU DAI",
 992         .ops = &skl_link_dai_ops,
 993         .playback = {
 994                 .stream_name = "Analog CPU Playback",
 995                 .channels_min = HDA_MONO,
 996                 .channels_max = HDA_MAX,
 997                 .rates = SNDRV_PCM_RATE_8000_192000,
 998                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 999                         SNDRV_PCM_FMTBIT_S32_LE,
1000         },
1001         .capture = {
1002                 .stream_name = "Analog CPU Capture",
1003                 .channels_min = HDA_MONO,
1004                 .channels_max = HDA_MAX,
1005                 .rates = SNDRV_PCM_RATE_8000_192000,
1006                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1007                         SNDRV_PCM_FMTBIT_S32_LE,
1008         },
1009 },
1010 {
1011         .name = "Alt Analog CPU DAI",
1012         .ops = &skl_link_dai_ops,
1013         .playback = {
1014                 .stream_name = "Alt Analog CPU Playback",
1015                 .channels_min = HDA_MONO,
1016                 .channels_max = HDA_MAX,
1017                 .rates = SNDRV_PCM_RATE_8000_192000,
1018                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1019                         SNDRV_PCM_FMTBIT_S32_LE,
1020         },
1021         .capture = {
1022                 .stream_name = "Alt Analog CPU Capture",
1023                 .channels_min = HDA_MONO,
1024                 .channels_max = HDA_MAX,
1025                 .rates = SNDRV_PCM_RATE_8000_192000,
1026                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1027                         SNDRV_PCM_FMTBIT_S32_LE,
1028         },
1029 },
1030 {
1031         .name = "Digital CPU DAI",
1032         .ops = &skl_link_dai_ops,
1033         .playback = {
1034                 .stream_name = "Digital CPU Playback",
1035                 .channels_min = HDA_MONO,
1036                 .channels_max = HDA_MAX,
1037                 .rates = SNDRV_PCM_RATE_8000_192000,
1038                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1039                         SNDRV_PCM_FMTBIT_S32_LE,
1040         },
1041         .capture = {
1042                 .stream_name = "Digital CPU Capture",
1043                 .channels_min = HDA_MONO,
1044                 .channels_max = HDA_MAX,
1045                 .rates = SNDRV_PCM_RATE_8000_192000,
1046                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1047                         SNDRV_PCM_FMTBIT_S32_LE,
1048         },
1049 },
1050 };
1051
1052 int skl_dai_load(struct snd_soc_component *cmp, int index,
1053                         struct snd_soc_dai_driver *dai_drv,
1054                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1055 {
1056         dai_drv->ops = &skl_pcm_dai_ops;
1057
1058         return 0;
1059 }
1060
1061 static int skl_platform_soc_open(struct snd_soc_component *component,
1062                                  struct snd_pcm_substream *substream)
1063 {
1064         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1065         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1066
1067         dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1068                                         dai_link->cpus->dai_name);
1069
1070         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1071
1072         return 0;
1073 }
1074
1075 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1076                                         int cmd)
1077 {
1078         struct hdac_bus *bus = get_bus_ctx(substream);
1079         struct hdac_ext_stream *stream;
1080         struct snd_pcm_substream *s;
1081         bool start;
1082         int sbits = 0;
1083         unsigned long cookie;
1084         struct hdac_stream *hstr;
1085
1086         stream = get_hdac_ext_stream(substream);
1087         hstr = hdac_stream(stream);
1088
1089         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1090
1091         if (!hstr->prepared)
1092                 return -EPIPE;
1093
1094         switch (cmd) {
1095         case SNDRV_PCM_TRIGGER_START:
1096         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1097         case SNDRV_PCM_TRIGGER_RESUME:
1098                 start = true;
1099                 break;
1100
1101         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1102         case SNDRV_PCM_TRIGGER_SUSPEND:
1103         case SNDRV_PCM_TRIGGER_STOP:
1104                 start = false;
1105                 break;
1106
1107         default:
1108                 return -EINVAL;
1109         }
1110
1111         snd_pcm_group_for_each_entry(s, substream) {
1112                 if (s->pcm->card != substream->pcm->card)
1113                         continue;
1114                 stream = get_hdac_ext_stream(s);
1115                 sbits |= 1 << hdac_stream(stream)->index;
1116                 snd_pcm_trigger_done(s, substream);
1117         }
1118
1119         spin_lock_irqsave(&bus->reg_lock, cookie);
1120
1121         /* first, set SYNC bits of corresponding streams */
1122         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1123
1124         snd_pcm_group_for_each_entry(s, substream) {
1125                 if (s->pcm->card != substream->pcm->card)
1126                         continue;
1127                 stream = get_hdac_ext_stream(s);
1128                 if (start)
1129                         snd_hdac_stream_start(hdac_stream(stream));
1130                 else
1131                         snd_hdac_stream_stop(hdac_stream(stream));
1132         }
1133         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1134
1135         snd_hdac_stream_sync(hstr, start, sbits);
1136
1137         spin_lock_irqsave(&bus->reg_lock, cookie);
1138
1139         /* reset SYNC bits */
1140         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1141         if (start)
1142                 snd_hdac_stream_timecounter_init(hstr, sbits);
1143         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1144
1145         return 0;
1146 }
1147
1148 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1149                                     struct snd_pcm_substream *substream,
1150                                     int cmd)
1151 {
1152         struct hdac_bus *bus = get_bus_ctx(substream);
1153
1154         if (!bus->ppcap)
1155                 return skl_coupled_trigger(substream, cmd);
1156
1157         return 0;
1158 }
1159
1160 static snd_pcm_uframes_t skl_platform_soc_pointer(
1161         struct snd_soc_component *component,
1162         struct snd_pcm_substream *substream)
1163 {
1164         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1165         struct hdac_bus *bus = get_bus_ctx(substream);
1166         unsigned int pos;
1167
1168         /*
1169          * Use DPIB for Playback stream as the periodic DMA Position-in-
1170          * Buffer Writes may be scheduled at the same time or later than
1171          * the MSI and does not guarantee to reflect the Position of the
1172          * last buffer that was transferred. Whereas DPIB register in
1173          * HAD space reflects the actual data that is transferred.
1174          * Use the position buffer for capture, as DPIB write gets
1175          * completed earlier than the actual data written to the DDR.
1176          *
1177          * For capture stream following workaround is required to fix the
1178          * incorrect position reporting.
1179          *
1180          * 1. Wait for 20us before reading the DMA position in buffer once
1181          * the interrupt is generated for stream completion as update happens
1182          * on the HDA frame boundary i.e. 20.833uSec.
1183          * 2. Read DPIB register to flush the DMA position value. This dummy
1184          * read is required to flush DMA position value.
1185          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1186          * or greater than period boundary.
1187          */
1188
1189         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1190                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1191                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1192                                 hdac_stream(hstream)->index));
1193         } else {
1194                 udelay(20);
1195                 readl(bus->remap_addr +
1196                                 AZX_REG_VS_SDXDPIB_XBASE +
1197                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1198                                  hdac_stream(hstream)->index));
1199                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1200         }
1201
1202         if (pos >= hdac_stream(hstream)->bufsize)
1203                 pos = 0;
1204
1205         return bytes_to_frames(substream->runtime, pos);
1206 }
1207
1208 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1209                                 u64 nsec)
1210 {
1211         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1212         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
1213         u64 codec_frames, codec_nsecs;
1214
1215         if (!codec_dai->driver->ops->delay)
1216                 return nsec;
1217
1218         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1219         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1220                               substream->runtime->rate);
1221
1222         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1223                 return nsec + codec_nsecs;
1224
1225         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1226 }
1227
1228 static int skl_platform_soc_get_time_info(
1229                         struct snd_soc_component *component,
1230                         struct snd_pcm_substream *substream,
1231                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1232                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1233                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1234 {
1235         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1236         struct hdac_stream *hstr = hdac_stream(sstream);
1237         u64 nsec;
1238
1239         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1240                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1241
1242                 snd_pcm_gettime(substream->runtime, system_ts);
1243
1244                 nsec = timecounter_read(&hstr->tc);
1245                 if (audio_tstamp_config->report_delay)
1246                         nsec = skl_adjust_codec_delay(substream, nsec);
1247
1248                 *audio_ts = ns_to_timespec64(nsec);
1249
1250                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1251                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1252                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1253
1254         } else {
1255                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1256         }
1257
1258         return 0;
1259 }
1260
1261 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1262
1263 static int skl_platform_soc_new(struct snd_soc_component *component,
1264                                 struct snd_soc_pcm_runtime *rtd)
1265 {
1266         struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1267         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1268         struct snd_pcm *pcm = rtd->pcm;
1269         unsigned int size;
1270         struct skl_dev *skl = bus_to_skl(bus);
1271
1272         if (dai->driver->playback.channels_min ||
1273                 dai->driver->capture.channels_min) {
1274                 /* buffer pre-allocation */
1275                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1276                 if (size > MAX_PREALLOC_SIZE)
1277                         size = MAX_PREALLOC_SIZE;
1278                 snd_pcm_set_managed_buffer_all(pcm,
1279                                                SNDRV_DMA_TYPE_DEV_SG,
1280                                                &skl->pci->dev,
1281                                                size, MAX_PREALLOC_SIZE);
1282         }
1283
1284         return 0;
1285 }
1286
1287 static int skl_get_module_info(struct skl_dev *skl,
1288                 struct skl_module_cfg *mconfig)
1289 {
1290         struct skl_module_inst_id *pin_id;
1291         guid_t *uuid_mod, *uuid_tplg;
1292         struct skl_module *skl_module;
1293         struct uuid_module *module;
1294         int i, ret = -EIO;
1295
1296         uuid_mod = (guid_t *)mconfig->guid;
1297
1298         if (list_empty(&skl->uuid_list)) {
1299                 dev_err(skl->dev, "Module list is empty\n");
1300                 return -EIO;
1301         }
1302
1303         for (i = 0; i < skl->nr_modules; i++) {
1304                 skl_module = skl->modules[i];
1305                 uuid_tplg = &skl_module->uuid;
1306                 if (guid_equal(uuid_mod, uuid_tplg)) {
1307                         mconfig->module = skl_module;
1308                         ret = 0;
1309                         break;
1310                 }
1311         }
1312
1313         if (skl->nr_modules && ret)
1314                 return ret;
1315
1316         ret = -EIO;
1317         list_for_each_entry(module, &skl->uuid_list, list) {
1318                 if (guid_equal(uuid_mod, &module->uuid)) {
1319                         mconfig->id.module_id = module->id;
1320                         mconfig->module->loadable = module->is_loadable;
1321                         ret = 0;
1322                 }
1323
1324                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1325                         pin_id = &mconfig->m_in_pin[i].id;
1326                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1327                                 pin_id->module_id = module->id;
1328                 }
1329
1330                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1331                         pin_id = &mconfig->m_out_pin[i].id;
1332                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1333                                 pin_id->module_id = module->id;
1334                 }
1335         }
1336
1337         return ret;
1338 }
1339
1340 static int skl_populate_modules(struct skl_dev *skl)
1341 {
1342         struct skl_pipeline *p;
1343         struct skl_pipe_module *m;
1344         struct snd_soc_dapm_widget *w;
1345         struct skl_module_cfg *mconfig;
1346         int ret = 0;
1347
1348         list_for_each_entry(p, &skl->ppl_list, node) {
1349                 list_for_each_entry(m, &p->pipe->w_list, node) {
1350                         w = m->w;
1351                         mconfig = w->priv;
1352
1353                         ret = skl_get_module_info(skl, mconfig);
1354                         if (ret < 0) {
1355                                 dev_err(skl->dev,
1356                                         "query module info failed\n");
1357                                 return ret;
1358                         }
1359
1360                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1361                 }
1362         }
1363
1364         return ret;
1365 }
1366
1367 static int skl_platform_soc_probe(struct snd_soc_component *component)
1368 {
1369         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1370         struct skl_dev *skl = bus_to_skl(bus);
1371         const struct skl_dsp_ops *ops;
1372         int ret;
1373
1374         ret = pm_runtime_resume_and_get(component->dev);
1375         if (ret < 0 && ret != -EACCES)
1376                 return ret;
1377
1378         if (bus->ppcap) {
1379                 skl->component = component;
1380
1381                 /* init debugfs */
1382                 skl->debugfs = skl_debugfs_init(skl);
1383
1384                 ret = skl_tplg_init(component, bus);
1385                 if (ret < 0) {
1386                         dev_err(component->dev, "Failed to init topology!\n");
1387                         return ret;
1388                 }
1389
1390                 /* load the firmwares, since all is set */
1391                 ops = skl_get_dsp_ops(skl->pci->device);
1392                 if (!ops)
1393                         return -EIO;
1394
1395                 /*
1396                  * Disable dynamic clock and power gating during firmware
1397                  * and library download
1398                  */
1399                 skl->enable_miscbdcge(component->dev, false);
1400                 skl->clock_power_gating(component->dev, false);
1401
1402                 ret = ops->init_fw(component->dev, skl);
1403                 skl->enable_miscbdcge(component->dev, true);
1404                 skl->clock_power_gating(component->dev, true);
1405                 if (ret < 0) {
1406                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1407                         return ret;
1408                 }
1409                 skl_populate_modules(skl);
1410                 skl->update_d0i3c = skl_update_d0i3c;
1411
1412                 if (skl->cfg.astate_cfg != NULL) {
1413                         skl_dsp_set_astate_cfg(skl,
1414                                         skl->cfg.astate_cfg->count,
1415                                         skl->cfg.astate_cfg);
1416                 }
1417         }
1418         pm_runtime_mark_last_busy(component->dev);
1419         pm_runtime_put_autosuspend(component->dev);
1420
1421         return 0;
1422 }
1423
1424 static void skl_platform_soc_remove(struct snd_soc_component *component)
1425 {
1426         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1427         struct skl_dev *skl = bus_to_skl(bus);
1428
1429         skl_tplg_exit(component, bus);
1430
1431         skl_debugfs_exit(skl);
1432 }
1433
1434 static const struct snd_soc_component_driver skl_component  = {
1435         .name           = "pcm",
1436         .probe          = skl_platform_soc_probe,
1437         .remove         = skl_platform_soc_remove,
1438         .open           = skl_platform_soc_open,
1439         .trigger        = skl_platform_soc_trigger,
1440         .pointer        = skl_platform_soc_pointer,
1441         .get_time_info  = skl_platform_soc_get_time_info,
1442         .pcm_construct  = skl_platform_soc_new,
1443         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1444 };
1445
1446 int skl_platform_register(struct device *dev)
1447 {
1448         int ret;
1449         struct snd_soc_dai_driver *dais;
1450         int num_dais = ARRAY_SIZE(skl_platform_dai);
1451         struct hdac_bus *bus = dev_get_drvdata(dev);
1452         struct skl_dev *skl = bus_to_skl(bus);
1453
1454         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1455                             GFP_KERNEL);
1456         if (!skl->dais) {
1457                 ret = -ENOMEM;
1458                 goto err;
1459         }
1460
1461         if (!skl->use_tplg_pcm) {
1462                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1463                                 sizeof(skl_platform_dai), GFP_KERNEL);
1464                 if (!dais) {
1465                         ret = -ENOMEM;
1466                         goto err;
1467                 }
1468
1469                 skl->dais = dais;
1470                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1471                        sizeof(skl_fe_dai));
1472                 num_dais += ARRAY_SIZE(skl_fe_dai);
1473         }
1474
1475         ret = devm_snd_soc_register_component(dev, &skl_component,
1476                                          skl->dais, num_dais);
1477         if (ret)
1478                 dev_err(dev, "soc component registration failed %d\n", ret);
1479 err:
1480         return ret;
1481 }
1482
1483 int skl_platform_unregister(struct device *dev)
1484 {
1485         struct hdac_bus *bus = dev_get_drvdata(dev);
1486         struct skl_dev *skl = bus_to_skl(bus);
1487         struct skl_module_deferred_bind *modules, *tmp;
1488
1489         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1490                 list_del(&modules->node);
1491                 kfree(modules);
1492         }
1493
1494         kfree(skl->dais);
1495
1496         return 0;
1497 }