sound/soc/intel/skylake/skl-pcm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  skl-pcm.c -ASoC HDA Platform driver file implementing PCM functionality
   4  *
   5  *  Copyright (C) 2014-2015 Intel Corp
   6  *  Author:  Jeeja KP <jeeja.kp@intel.com>
   7  *
   8  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
   9  *
  10  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  11  */
  12
  13 #include <linux/pci.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/delay.h>
  16 #include <sound/hdaudio.h>
  17 #include <sound/pcm_params.h>
  18 #include <sound/soc.h>
  19 #include "skl.h"
  20 #include "skl-topology.h"
  21 #include "skl-sst-dsp.h"
  22 #include "skl-sst-ipc.h"
  23
  24 #define HDA_MONO 1
  25 #define HDA_STEREO 2
  26 #define HDA_QUAD 4
  27 #define HDA_MAX 8
  28
  29 static const struct snd_pcm_hardware azx_pcm_hw = {
  30         .info =                 (SNDRV_PCM_INFO_MMAP |
  31                                  SNDRV_PCM_INFO_INTERLEAVED |
  32                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
  33                                  SNDRV_PCM_INFO_MMAP_VALID |
  34                                  SNDRV_PCM_INFO_PAUSE |
  35                                  SNDRV_PCM_INFO_RESUME |
  36                                  SNDRV_PCM_INFO_SYNC_START |
  37                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
  38                                  SNDRV_PCM_INFO_HAS_LINK_ATIME |
  39                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
  40         .formats =              SNDRV_PCM_FMTBIT_S16_LE |
  41                                 SNDRV_PCM_FMTBIT_S32_LE |
  42                                 SNDRV_PCM_FMTBIT_S24_LE,
  43         .rates =                SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
  44                                 SNDRV_PCM_RATE_8000,
  45         .rate_min =             8000,
  46         .rate_max =             48000,
  47         .channels_min =         1,
  48         .channels_max =         8,
  49         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
  50         .period_bytes_min =     128,
  51         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
  52         .periods_min =          2,
  53         .periods_max =          AZX_MAX_FRAG,
  54         .fifo_size =            0,
  55 };
  56
  57 static inline
  58 struct hdac_ext_stream *get_hdac_ext_stream(struct snd_pcm_substream *substream)
  59 {
  60         return substream->runtime->private_data;
  61 }
  62
  63 static struct hdac_bus *get_bus_ctx(struct snd_pcm_substream *substream)
  64 {
  65         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  66         struct hdac_stream *hstream = hdac_stream(stream);
  67         struct hdac_bus *bus = hstream->bus;
  68         return bus;
  69 }
  70
  71 static int skl_substream_alloc_pages(struct hdac_bus *bus,
  72                                  struct snd_pcm_substream *substream,
  73                                  size_t size)
  74 {
  75         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
  76
  77         hdac_stream(stream)->bufsize = 0;
  78         hdac_stream(stream)->period_bytes = 0;
  79         hdac_stream(stream)->format_val = 0;
  80
  81         return 0;
  82 }
  83
  84 static void skl_set_pcm_constrains(struct hdac_bus *bus,
  85                                  struct snd_pcm_runtime *runtime)
  86 {
  87         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
  88
  89         /* avoid wrap-around with wall-clock */
  90         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
  91                                      20, 178000000);
  92 }
  93
  94 static enum hdac_ext_stream_type skl_get_host_stream_type(struct hdac_bus *bus)
  95 {
  96         if (bus->ppcap)
  97                 return HDAC_EXT_STREAM_TYPE_HOST;
  98         else
  99                 return HDAC_EXT_STREAM_TYPE_COUPLED;
 100 }
 101
 102 /*
 103  * check if the stream opened is marked as ignore_suspend by machine, if so
 104  * then enable suspend_active refcount
 105  *
 106  * The count supend_active does not need lock as it is used in open/close
 107  * and suspend context
 108  */
 109 static void skl_set_suspend_active(struct snd_pcm_substream *substream,
 110                                          struct snd_soc_dai *dai, bool enable)
 111 {
 112         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 113         struct snd_soc_dapm_widget *w;
 114         struct skl_dev *skl = bus_to_skl(bus);
 115
 116         w = snd_soc_dai_get_widget(dai, substream->stream);
 117
 118         if (w->ignore_suspend && enable)
 119                 skl->supend_active++;
 120         else if (w->ignore_suspend && !enable)
 121                 skl->supend_active--;
 122 }
 123
 124 int skl_pcm_host_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 125 {
 126         struct hdac_bus *bus = dev_get_drvdata(dev);
 127         unsigned int format_val;
 128         struct hdac_stream *hstream;
 129         struct hdac_ext_stream *stream;
 130         int err;
 131
 132         hstream = snd_hdac_get_stream(bus, params->stream,
 133                                         params->host_dma_id + 1);
 134         if (!hstream)
 135                 return -EINVAL;
 136
 137         stream = stream_to_hdac_ext_stream(hstream);
 138         snd_hdac_ext_stream_decouple(bus, stream, true);
 139
 140         format_val = snd_hdac_calc_stream_format(params->s_freq,
 141                         params->ch, params->format, params->host_bps, 0);
 142
 143         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 144                 format_val, params->s_freq, params->ch, params->format);
 145
 146         snd_hdac_stream_reset(hdac_stream(stream));
 147         err = snd_hdac_stream_set_params(hdac_stream(stream), format_val);
 148         if (err < 0)
 149                 return err;
 150
 151         err = snd_hdac_ext_host_stream_setup(stream, false);
 152         if (err < 0)
 153                 return err;
 154
 155         hdac_stream(stream)->prepared = 1;
 156
 157         return 0;
 158 }
 159
 160 int skl_pcm_link_dma_prepare(struct device *dev, struct skl_pipe_params *params)
 161 {
 162         struct hdac_bus *bus = dev_get_drvdata(dev);
 163         unsigned int format_val;
 164         struct hdac_stream *hstream;
 165         struct hdac_ext_stream *stream;
 166         struct hdac_ext_link *link;
 167         unsigned char stream_tag;
 168
 169         hstream = snd_hdac_get_stream(bus, params->stream,
 170                                         params->link_dma_id + 1);
 171         if (!hstream)
 172                 return -EINVAL;
 173
 174         stream = stream_to_hdac_ext_stream(hstream);
 175         snd_hdac_ext_stream_decouple(bus, stream, true);
 176         format_val = snd_hdac_calc_stream_format(params->s_freq, params->ch,
 177                                         params->format, params->link_bps, 0);
 178
 179         dev_dbg(dev, "format_val=%d, rate=%d, ch=%d, format=%d\n",
 180                 format_val, params->s_freq, params->ch, params->format);
 181
 182         snd_hdac_ext_stream_reset(stream);
 183
 184         snd_hdac_ext_stream_setup(stream, format_val);
 185
 186         stream_tag = hstream->stream_tag;
 187         if (stream->hstream.direction == SNDRV_PCM_STREAM_PLAYBACK) {
 188                 list_for_each_entry(link, &bus->hlink_list, list) {
 189                         if (link->index == params->link_index)
 190                                 snd_hdac_ext_bus_link_set_stream_id(link,
 191                                                                     stream_tag);
 192                 }
 193         }
 194
 195         stream->link_prepared = 1;
 196
 197         return 0;
 198 }
 199
 200 static int skl_pcm_open(struct snd_pcm_substream *substream,
 201                 struct snd_soc_dai *dai)
 202 {
 203         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 204         struct hdac_ext_stream *stream;
 205         struct snd_pcm_runtime *runtime = substream->runtime;
 206         struct skl_dma_params *dma_params;
 207         struct skl_dev *skl = get_skl_ctx(dai->dev);
 208         struct skl_module_cfg *mconfig;
 209
 210         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 211
 212         stream = snd_hdac_ext_stream_assign(bus, substream,
 213                                         skl_get_host_stream_type(bus));
 214         if (stream == NULL)
 215                 return -EBUSY;
 216
 217         skl_set_pcm_constrains(bus, runtime);
 218
 219         /*
 220          * disable WALLCLOCK timestamps for capture streams
 221          * until we figure out how to handle digital inputs
 222          */
 223         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
 224                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
 225                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
 226         }
 227
 228         runtime->private_data = stream;
 229
 230         dma_params = kzalloc(sizeof(*dma_params), GFP_KERNEL);
 231         if (!dma_params)
 232                 return -ENOMEM;
 233
 234         dma_params->stream_tag = hdac_stream(stream)->stream_tag;
 235         snd_soc_dai_set_dma_data(dai, substream, dma_params);
 236
 237         dev_dbg(dai->dev, "stream tag set in dma params=%d\n",
 238                                  dma_params->stream_tag);
 239         skl_set_suspend_active(substream, dai, true);
 240         snd_pcm_set_sync(substream);
 241
 242         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 243         if (!mconfig)
 244                 return -EINVAL;
 245
 246         skl_tplg_d0i3_get(skl, mconfig->d0i3_caps);
 247
 248         return 0;
 249 }
 250
 251 static int skl_pcm_prepare(struct snd_pcm_substream *substream,
 252                 struct snd_soc_dai *dai)
 253 {
 254         struct skl_dev *skl = get_skl_ctx(dai->dev);
 255         struct skl_module_cfg *mconfig;
 256         int ret;
 257
 258         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 259
 260         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 261
 262         /*
 263          * In case of XRUN recovery or in the case when the application
 264          * calls prepare another time, reset the FW pipe to clean state
 265          */
 266         if (mconfig &&
 267                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN ||
 268                  mconfig->pipe->state == SKL_PIPE_CREATED ||
 269                  mconfig->pipe->state == SKL_PIPE_PAUSED)) {
 270
 271                 ret = skl_reset_pipe(skl, mconfig->pipe);
 272
 273                 if (ret < 0)
 274                         return ret;
 275
 276                 ret = skl_pcm_host_dma_prepare(dai->dev,
 277                                         mconfig->pipe->p_params);
 278                 if (ret < 0)
 279                         return ret;
 280         }
 281
 282         return 0;
 283 }
 284
 285 static int skl_pcm_hw_params(struct snd_pcm_substream *substream,
 286                                 struct snd_pcm_hw_params *params,
 287                                 struct snd_soc_dai *dai)
 288 {
 289         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 290         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 291         struct snd_pcm_runtime *runtime = substream->runtime;
 292         struct skl_pipe_params p_params = {0};
 293         struct skl_module_cfg *m_cfg;
 294         int ret, dma_id;
 295
 296         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 297         ret = skl_substream_alloc_pages(bus, substream,
 298                                           params_buffer_bytes(params));
 299         if (ret < 0)
 300                 return ret;
 301
 302         dev_dbg(dai->dev, "format_val, rate=%d, ch=%d, format=%d\n",
 303                         runtime->rate, runtime->channels, runtime->format);
 304
 305         dma_id = hdac_stream(stream)->stream_tag - 1;
 306         dev_dbg(dai->dev, "dma_id=%d\n", dma_id);
 307
 308         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 309         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 310         p_params.ch = params_channels(params);
 311         p_params.s_freq = params_rate(params);
 312         p_params.host_dma_id = dma_id;
 313         p_params.stream = substream->stream;
 314         p_params.format = params_format(params);
 315         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 316                 p_params.host_bps = dai->driver->playback.sig_bits;
 317         else
 318                 p_params.host_bps = dai->driver->capture.sig_bits;
 319
 320
 321         m_cfg = skl_tplg_fe_get_cpr_module(dai, p_params.stream);
 322         if (m_cfg)
 323                 skl_tplg_update_pipe_params(dai->dev, m_cfg, &p_params);
 324
 325         return 0;
 326 }
 327
 328 static void skl_pcm_close(struct snd_pcm_substream *substream,
 329                 struct snd_soc_dai *dai)
 330 {
 331         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 332         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 333         struct skl_dma_params *dma_params = NULL;
 334         struct skl_dev *skl = bus_to_skl(bus);
 335         struct skl_module_cfg *mconfig;
 336
 337         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 338
 339         snd_hdac_ext_stream_release(stream, skl_get_host_stream_type(bus));
 340
 341         dma_params = snd_soc_dai_get_dma_data(dai, substream);
 342         /*
 343          * now we should set this to NULL as we are freeing by the
 344          * dma_params
 345          */
 346         snd_soc_dai_set_dma_data(dai, substream, NULL);
 347         skl_set_suspend_active(substream, dai, false);
 348
 349         /*
 350          * check if close is for "Reference Pin" and set back the
 351          * CGCTL.MISCBDCGE if disabled by driver
 352          */
 353         if (!strncmp(dai->name, "Reference Pin", 13) &&
 354                         skl->miscbdcg_disabled) {
 355                 skl->enable_miscbdcge(dai->dev, true);
 356                 skl->miscbdcg_disabled = false;
 357         }
 358
 359         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 360         if (mconfig)
 361                 skl_tplg_d0i3_put(skl, mconfig->d0i3_caps);
 362
 363         kfree(dma_params);
 364 }
 365
 366 static int skl_pcm_hw_free(struct snd_pcm_substream *substream,
 367                 struct snd_soc_dai *dai)
 368 {
 369         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 370         struct skl_dev *skl = get_skl_ctx(dai->dev);
 371         struct skl_module_cfg *mconfig;
 372         int ret;
 373
 374         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 375
 376         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 377
 378         if (mconfig) {
 379                 ret = skl_reset_pipe(skl, mconfig->pipe);
 380                 if (ret < 0)
 381                         dev_err(dai->dev, "%s:Reset failed ret =%d",
 382                                                 __func__, ret);
 383         }
 384
 385         snd_hdac_stream_cleanup(hdac_stream(stream));
 386         hdac_stream(stream)->prepared = 0;
 387
 388         return 0;
 389 }
 390
 391 static int skl_be_hw_params(struct snd_pcm_substream *substream,
 392                                 struct snd_pcm_hw_params *params,
 393                                 struct snd_soc_dai *dai)
 394 {
 395         struct skl_pipe_params p_params = {0};
 396
 397         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 398         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 399         p_params.ch = params_channels(params);
 400         p_params.s_freq = params_rate(params);
 401         p_params.stream = substream->stream;
 402
 403         return skl_tplg_be_update_params(dai, &p_params);
 404 }
 405
 406 static int skl_decoupled_trigger(struct snd_pcm_substream *substream,
 407                 int cmd)
 408 {
 409         struct hdac_bus *bus = get_bus_ctx(substream);
 410         struct hdac_ext_stream *stream;
 411         int start;
 412         unsigned long cookie;
 413         struct hdac_stream *hstr;
 414
 415         stream = get_hdac_ext_stream(substream);
 416         hstr = hdac_stream(stream);
 417
 418         if (!hstr->prepared)
 419                 return -EPIPE;
 420
 421         switch (cmd) {
 422         case SNDRV_PCM_TRIGGER_START:
 423         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 424         case SNDRV_PCM_TRIGGER_RESUME:
 425                 start = 1;
 426                 break;
 427
 428         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 429         case SNDRV_PCM_TRIGGER_SUSPEND:
 430         case SNDRV_PCM_TRIGGER_STOP:
 431                 start = 0;
 432                 break;
 433
 434         default:
 435                 return -EINVAL;
 436         }
 437
 438         spin_lock_irqsave(&bus->reg_lock, cookie);
 439
 440         if (start) {
 441                 snd_hdac_stream_start(hdac_stream(stream));
 442                 snd_hdac_stream_timecounter_init(hstr, 0);
 443         } else {
 444                 snd_hdac_stream_stop(hdac_stream(stream));
 445         }
 446
 447         spin_unlock_irqrestore(&bus->reg_lock, cookie);
 448
 449         return 0;
 450 }
 451
 452 static int skl_pcm_trigger(struct snd_pcm_substream *substream, int cmd,
 453                 struct snd_soc_dai *dai)
 454 {
 455         struct skl_dev *skl = get_skl_ctx(dai->dev);
 456         struct skl_module_cfg *mconfig;
 457         struct hdac_bus *bus = get_bus_ctx(substream);
 458         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 459         struct hdac_stream *hstream = hdac_stream(stream);
 460         struct snd_soc_dapm_widget *w;
 461         int ret;
 462
 463         mconfig = skl_tplg_fe_get_cpr_module(dai, substream->stream);
 464         if (!mconfig)
 465                 return -EIO;
 466
 467         w = snd_soc_dai_get_widget(dai, substream->stream);
 468
 469         switch (cmd) {
 470         case SNDRV_PCM_TRIGGER_RESUME:
 471                 if (!w->ignore_suspend) {
 472                         /*
 473                          * enable DMA Resume enable bit for the stream, set the
 474                          * dpib & lpib position to resume before starting the
 475                          * DMA
 476                          */
 477                         snd_hdac_stream_drsm_enable(bus, true, hstream->index);
 478                         snd_hdac_stream_set_dpibr(bus, hstream, hstream->lpib);
 479                         snd_hdac_stream_set_lpib(hstream, hstream->lpib);
 480                 }
 481                 fallthrough;
 482
 483         case SNDRV_PCM_TRIGGER_START:
 484         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 485                 /*
 486                  * Start HOST DMA and Start FE Pipe.This is to make sure that
 487                  * there are no underrun/overrun in the case when the FE
 488                  * pipeline is started but there is a delay in starting the
 489                  * DMA channel on the host.
 490                  */
 491                 ret = skl_decoupled_trigger(substream, cmd);
 492                 if (ret < 0)
 493                         return ret;
 494                 return skl_run_pipe(skl, mconfig->pipe);
 495
 496         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 497         case SNDRV_PCM_TRIGGER_SUSPEND:
 498         case SNDRV_PCM_TRIGGER_STOP:
 499                 /*
 500                  * Stop FE Pipe first and stop DMA. This is to make sure that
 501                  * there are no underrun/overrun in the case if there is a delay
 502                  * between the two operations.
 503                  */
 504                 ret = skl_stop_pipe(skl, mconfig->pipe);
 505                 if (ret < 0)
 506                         return ret;
 507
 508                 ret = skl_decoupled_trigger(substream, cmd);
 509                 if ((cmd == SNDRV_PCM_TRIGGER_SUSPEND) && !w->ignore_suspend) {
 510                         /* save the dpib and lpib positions */
 511                         hstream->dpib = readl(bus->remap_addr +
 512                                         AZX_REG_VS_SDXDPIB_XBASE +
 513                                         (AZX_REG_VS_SDXDPIB_XINTERVAL *
 514                                         hstream->index));
 515
 516                         hstream->lpib = snd_hdac_stream_get_pos_lpib(hstream);
 517
 518                         snd_hdac_ext_stream_decouple(bus, stream, false);
 519                 }
 520                 break;
 521
 522         default:
 523                 return -EINVAL;
 524         }
 525
 526         return 0;
 527 }
 528
 529
 530 static int skl_link_hw_params(struct snd_pcm_substream *substream,
 531                                 struct snd_pcm_hw_params *params,
 532                                 struct snd_soc_dai *dai)
 533 {
 534         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 535         struct hdac_ext_stream *link_dev;
 536         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 537         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
 538         struct skl_pipe_params p_params = {0};
 539         struct hdac_ext_link *link;
 540         int stream_tag;
 541
 542         link_dev = snd_hdac_ext_stream_assign(bus, substream,
 543                                         HDAC_EXT_STREAM_TYPE_LINK);
 544         if (!link_dev)
 545                 return -EBUSY;
 546
 547         snd_soc_dai_set_dma_data(dai, substream, (void *)link_dev);
 548
 549         link = snd_hdac_ext_bus_get_hlink_by_name(bus, codec_dai->component->name);
 550         if (!link)
 551                 return -EINVAL;
 552
 553         stream_tag = hdac_stream(link_dev)->stream_tag;
 554
 555         /* set the hdac_stream in the codec dai */
 556         snd_soc_dai_set_stream(codec_dai, hdac_stream(link_dev), substream->stream);
 557
 558         p_params.s_fmt = snd_pcm_format_width(params_format(params));
 559         p_params.s_cont = snd_pcm_format_physical_width(params_format(params));
 560         p_params.ch = params_channels(params);
 561         p_params.s_freq = params_rate(params);
 562         p_params.stream = substream->stream;
 563         p_params.link_dma_id = stream_tag - 1;
 564         p_params.link_index = link->index;
 565         p_params.format = params_format(params);
 566
 567         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 568                 p_params.link_bps = codec_dai->driver->playback.sig_bits;
 569         else
 570                 p_params.link_bps = codec_dai->driver->capture.sig_bits;
 571
 572         return skl_tplg_be_update_params(dai, &p_params);
 573 }
 574
 575 static int skl_link_pcm_prepare(struct snd_pcm_substream *substream,
 576                 struct snd_soc_dai *dai)
 577 {
 578         struct skl_dev *skl = get_skl_ctx(dai->dev);
 579         struct skl_module_cfg *mconfig = NULL;
 580
 581         /* In case of XRUN recovery, reset the FW pipe to clean state */
 582         mconfig = skl_tplg_be_get_cpr_module(dai, substream->stream);
 583         if (mconfig && !mconfig->pipe->passthru &&
 584                 (substream->runtime->state == SNDRV_PCM_STATE_XRUN))
 585                 skl_reset_pipe(skl, mconfig->pipe);
 586
 587         return 0;
 588 }
 589
 590 static int skl_link_pcm_trigger(struct snd_pcm_substream *substream,
 591         int cmd, struct snd_soc_dai *dai)
 592 {
 593         struct hdac_ext_stream *link_dev =
 594                                 snd_soc_dai_get_dma_data(dai, substream);
 595         struct hdac_bus *bus = get_bus_ctx(substream);
 596         struct hdac_ext_stream *stream = get_hdac_ext_stream(substream);
 597
 598         dev_dbg(dai->dev, "In %s cmd=%d\n", __func__, cmd);
 599         switch (cmd) {
 600         case SNDRV_PCM_TRIGGER_RESUME:
 601         case SNDRV_PCM_TRIGGER_START:
 602         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 603                 snd_hdac_ext_stream_start(link_dev);
 604                 break;
 605
 606         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 607         case SNDRV_PCM_TRIGGER_SUSPEND:
 608         case SNDRV_PCM_TRIGGER_STOP:
 609                 snd_hdac_ext_stream_clear(link_dev);
 610                 if (cmd == SNDRV_PCM_TRIGGER_SUSPEND)
 611                         snd_hdac_ext_stream_decouple(bus, stream, false);
 612                 break;
 613
 614         default:
 615                 return -EINVAL;
 616         }
 617         return 0;
 618 }
 619
 620 static int skl_link_hw_free(struct snd_pcm_substream *substream,
 621                 struct snd_soc_dai *dai)
 622 {
 623         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
 624         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
 625         struct hdac_ext_stream *link_dev =
 626                                 snd_soc_dai_get_dma_data(dai, substream);
 627         struct hdac_ext_link *link;
 628         unsigned char stream_tag;
 629
 630         dev_dbg(dai->dev, "%s: %s\n", __func__, dai->name);
 631
 632         link_dev->link_prepared = 0;
 633
 634         link = snd_hdac_ext_bus_get_hlink_by_name(bus, snd_soc_rtd_to_codec(rtd, 0)->component->name);
 635         if (!link)
 636                 return -EINVAL;
 637
 638         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 639                 stream_tag = hdac_stream(link_dev)->stream_tag;
 640                 snd_hdac_ext_bus_link_clear_stream_id(link, stream_tag);
 641         }
 642
 643         snd_hdac_ext_stream_release(link_dev, HDAC_EXT_STREAM_TYPE_LINK);
 644         return 0;
 645 }
 646
 647 static const struct snd_soc_dai_ops skl_pcm_dai_ops = {
 648         .startup = skl_pcm_open,
 649         .shutdown = skl_pcm_close,
 650         .prepare = skl_pcm_prepare,
 651         .hw_params = skl_pcm_hw_params,
 652         .hw_free = skl_pcm_hw_free,
 653         .trigger = skl_pcm_trigger,
 654 };
 655
 656 static const struct snd_soc_dai_ops skl_dmic_dai_ops = {
 657         .hw_params = skl_be_hw_params,
 658 };
 659
 660 static const struct snd_soc_dai_ops skl_be_ssp_dai_ops = {
 661         .hw_params = skl_be_hw_params,
 662 };
 663
 664 static const struct snd_soc_dai_ops skl_link_dai_ops = {
 665         .prepare = skl_link_pcm_prepare,
 666         .hw_params = skl_link_hw_params,
 667         .hw_free = skl_link_hw_free,
 668         .trigger = skl_link_pcm_trigger,
 669 };
 670
 671 static struct snd_soc_dai_driver skl_fe_dai[] = {
 672 {
 673         .name = "System Pin",
 674         .ops = &skl_pcm_dai_ops,
 675         .playback = {
 676                 .stream_name = "System Playback",
 677                 .channels_min = HDA_MONO,
 678                 .channels_max = HDA_STEREO,
 679                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_8000,
 680                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 681                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 682                 .sig_bits = 32,
 683         },
 684         .capture = {
 685                 .stream_name = "System Capture",
 686                 .channels_min = HDA_MONO,
 687                 .channels_max = HDA_STEREO,
 688                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 689                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 690                 .sig_bits = 32,
 691         },
 692 },
 693 {
 694         .name = "System Pin2",
 695         .ops = &skl_pcm_dai_ops,
 696         .playback = {
 697                 .stream_name = "Headset Playback",
 698                 .channels_min = HDA_MONO,
 699                 .channels_max = HDA_STEREO,
 700                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 701                         SNDRV_PCM_RATE_8000,
 702                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 703                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 704         },
 705 },
 706 {
 707         .name = "Echoref Pin",
 708         .ops = &skl_pcm_dai_ops,
 709         .capture = {
 710                 .stream_name = "Echoreference Capture",
 711                 .channels_min = HDA_STEREO,
 712                 .channels_max = HDA_STEREO,
 713                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000 |
 714                         SNDRV_PCM_RATE_8000,
 715                 .formats = SNDRV_PCM_FMTBIT_S16_LE |
 716                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE,
 717         },
 718 },
 719 {
 720         .name = "Reference Pin",
 721         .ops = &skl_pcm_dai_ops,
 722         .capture = {
 723                 .stream_name = "Reference Capture",
 724                 .channels_min = HDA_MONO,
 725                 .channels_max = HDA_QUAD,
 726                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 727                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 728                 .sig_bits = 32,
 729         },
 730 },
 731 {
 732         .name = "Deepbuffer Pin",
 733         .ops = &skl_pcm_dai_ops,
 734         .playback = {
 735                 .stream_name = "Deepbuffer Playback",
 736                 .channels_min = HDA_STEREO,
 737                 .channels_max = HDA_STEREO,
 738                 .rates = SNDRV_PCM_RATE_48000,
 739                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 740                 .sig_bits = 32,
 741         },
 742 },
 743 {
 744         .name = "LowLatency Pin",
 745         .ops = &skl_pcm_dai_ops,
 746         .playback = {
 747                 .stream_name = "Low Latency Playback",
 748                 .channels_min = HDA_STEREO,
 749                 .channels_max = HDA_STEREO,
 750                 .rates = SNDRV_PCM_RATE_48000,
 751                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 752                 .sig_bits = 32,
 753         },
 754 },
 755 {
 756         .name = "DMIC Pin",
 757         .ops = &skl_pcm_dai_ops,
 758         .capture = {
 759                 .stream_name = "DMIC Capture",
 760                 .channels_min = HDA_MONO,
 761                 .channels_max = HDA_QUAD,
 762                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 763                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 764                 .sig_bits = 32,
 765         },
 766 },
 767 {
 768         .name = "HDMI1 Pin",
 769         .ops = &skl_pcm_dai_ops,
 770         .playback = {
 771                 .stream_name = "HDMI1 Playback",
 772                 .channels_min = HDA_STEREO,
 773                 .channels_max = 8,
 774                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 775                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 776                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 777                         SNDRV_PCM_RATE_192000,
 778                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 779                         SNDRV_PCM_FMTBIT_S32_LE,
 780                 .sig_bits = 32,
 781         },
 782 },
 783 {
 784         .name = "HDMI2 Pin",
 785         .ops = &skl_pcm_dai_ops,
 786         .playback = {
 787                 .stream_name = "HDMI2 Playback",
 788                 .channels_min = HDA_STEREO,
 789                 .channels_max = 8,
 790                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 791                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 792                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 793                         SNDRV_PCM_RATE_192000,
 794                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 795                         SNDRV_PCM_FMTBIT_S32_LE,
 796                 .sig_bits = 32,
 797         },
 798 },
 799 {
 800         .name = "HDMI3 Pin",
 801         .ops = &skl_pcm_dai_ops,
 802         .playback = {
 803                 .stream_name = "HDMI3 Playback",
 804                 .channels_min = HDA_STEREO,
 805                 .channels_max = 8,
 806                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
 807                         SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
 808                         SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
 809                         SNDRV_PCM_RATE_192000,
 810                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 811                         SNDRV_PCM_FMTBIT_S32_LE,
 812                 .sig_bits = 32,
 813         },
 814 },
 815 };
 816
 817 /* BE CPU  Dais */
 818 static struct snd_soc_dai_driver skl_platform_dai[] = {
 819 {
 820         .name = "SSP0 Pin",
 821         .ops = &skl_be_ssp_dai_ops,
 822         .playback = {
 823                 .stream_name = "ssp0 Tx",
 824                 .channels_min = HDA_STEREO,
 825                 .channels_max = HDA_STEREO,
 826                 .rates = SNDRV_PCM_RATE_48000,
 827                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 828         },
 829         .capture = {
 830                 .stream_name = "ssp0 Rx",
 831                 .channels_min = HDA_STEREO,
 832                 .channels_max = HDA_STEREO,
 833                 .rates = SNDRV_PCM_RATE_48000,
 834                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 835         },
 836 },
 837 {
 838         .name = "SSP1 Pin",
 839         .ops = &skl_be_ssp_dai_ops,
 840         .playback = {
 841                 .stream_name = "ssp1 Tx",
 842                 .channels_min = HDA_STEREO,
 843                 .channels_max = HDA_STEREO,
 844                 .rates = SNDRV_PCM_RATE_48000,
 845                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 846         },
 847         .capture = {
 848                 .stream_name = "ssp1 Rx",
 849                 .channels_min = HDA_STEREO,
 850                 .channels_max = HDA_STEREO,
 851                 .rates = SNDRV_PCM_RATE_48000,
 852                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 853         },
 854 },
 855 {
 856         .name = "SSP2 Pin",
 857         .ops = &skl_be_ssp_dai_ops,
 858         .playback = {
 859                 .stream_name = "ssp2 Tx",
 860                 .channels_min = HDA_STEREO,
 861                 .channels_max = HDA_STEREO,
 862                 .rates = SNDRV_PCM_RATE_48000,
 863                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 864         },
 865         .capture = {
 866                 .stream_name = "ssp2 Rx",
 867                 .channels_min = HDA_STEREO,
 868                 .channels_max = HDA_STEREO,
 869                 .rates = SNDRV_PCM_RATE_48000,
 870                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 871         },
 872 },
 873 {
 874         .name = "SSP3 Pin",
 875         .ops = &skl_be_ssp_dai_ops,
 876         .playback = {
 877                 .stream_name = "ssp3 Tx",
 878                 .channels_min = HDA_STEREO,
 879                 .channels_max = HDA_STEREO,
 880                 .rates = SNDRV_PCM_RATE_48000,
 881                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 882         },
 883         .capture = {
 884                 .stream_name = "ssp3 Rx",
 885                 .channels_min = HDA_STEREO,
 886                 .channels_max = HDA_STEREO,
 887                 .rates = SNDRV_PCM_RATE_48000,
 888                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 889         },
 890 },
 891 {
 892         .name = "SSP4 Pin",
 893         .ops = &skl_be_ssp_dai_ops,
 894         .playback = {
 895                 .stream_name = "ssp4 Tx",
 896                 .channels_min = HDA_STEREO,
 897                 .channels_max = HDA_STEREO,
 898                 .rates = SNDRV_PCM_RATE_48000,
 899                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 900         },
 901         .capture = {
 902                 .stream_name = "ssp4 Rx",
 903                 .channels_min = HDA_STEREO,
 904                 .channels_max = HDA_STEREO,
 905                 .rates = SNDRV_PCM_RATE_48000,
 906                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 907         },
 908 },
 909 {
 910         .name = "SSP5 Pin",
 911         .ops = &skl_be_ssp_dai_ops,
 912         .playback = {
 913                 .stream_name = "ssp5 Tx",
 914                 .channels_min = HDA_STEREO,
 915                 .channels_max = HDA_STEREO,
 916                 .rates = SNDRV_PCM_RATE_48000,
 917                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 918         },
 919         .capture = {
 920                 .stream_name = "ssp5 Rx",
 921                 .channels_min = HDA_STEREO,
 922                 .channels_max = HDA_STEREO,
 923                 .rates = SNDRV_PCM_RATE_48000,
 924                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 925         },
 926 },
 927 {
 928         .name = "iDisp1 Pin",
 929         .ops = &skl_link_dai_ops,
 930         .playback = {
 931                 .stream_name = "iDisp1 Tx",
 932                 .channels_min = HDA_STEREO,
 933                 .channels_max = 8,
 934                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_48000,
 935                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 936                         SNDRV_PCM_FMTBIT_S24_LE,
 937         },
 938 },
 939 {
 940         .name = "iDisp2 Pin",
 941         .ops = &skl_link_dai_ops,
 942         .playback = {
 943                 .stream_name = "iDisp2 Tx",
 944                 .channels_min = HDA_STEREO,
 945                 .channels_max = 8,
 946                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 947                         SNDRV_PCM_RATE_48000,
 948                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 949                         SNDRV_PCM_FMTBIT_S24_LE,
 950         },
 951 },
 952 {
 953         .name = "iDisp3 Pin",
 954         .ops = &skl_link_dai_ops,
 955         .playback = {
 956                 .stream_name = "iDisp3 Tx",
 957                 .channels_min = HDA_STEREO,
 958                 .channels_max = 8,
 959                 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|
 960                         SNDRV_PCM_RATE_48000,
 961                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE |
 962                         SNDRV_PCM_FMTBIT_S24_LE,
 963         },
 964 },
 965 {
 966         .name = "DMIC01 Pin",
 967         .ops = &skl_dmic_dai_ops,
 968         .capture = {
 969                 .stream_name = "DMIC01 Rx",
 970                 .channels_min = HDA_MONO,
 971                 .channels_max = HDA_QUAD,
 972                 .rates = SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_16000,
 973                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
 974         },
 975 },
 976 {
 977         .name = "DMIC16k Pin",
 978         .ops = &skl_dmic_dai_ops,
 979         .capture = {
 980                 .stream_name = "DMIC16k Rx",
 981                 .channels_min = HDA_MONO,
 982                 .channels_max = HDA_QUAD,
 983                 .rates = SNDRV_PCM_RATE_16000,
 984                 .formats = SNDRV_PCM_FMTBIT_S16_LE,
 985         },
 986 },
 987 {
 988         .name = "Analog CPU DAI",
 989         .ops = &skl_link_dai_ops,
 990         .playback = {
 991                 .stream_name = "Analog CPU Playback",
 992                 .channels_min = HDA_MONO,
 993                 .channels_max = HDA_MAX,
 994                 .rates = SNDRV_PCM_RATE_8000_192000,
 995                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
 996                         SNDRV_PCM_FMTBIT_S32_LE,
 997         },
 998         .capture = {
 999                 .stream_name = "Analog CPU Capture",
1000                 .channels_min = HDA_MONO,
1001                 .channels_max = HDA_MAX,
1002                 .rates = SNDRV_PCM_RATE_8000_192000,
1003                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1004                         SNDRV_PCM_FMTBIT_S32_LE,
1005         },
1006 },
1007 {
1008         .name = "Alt Analog CPU DAI",
1009         .ops = &skl_link_dai_ops,
1010         .playback = {
1011                 .stream_name = "Alt Analog CPU Playback",
1012                 .channels_min = HDA_MONO,
1013                 .channels_max = HDA_MAX,
1014                 .rates = SNDRV_PCM_RATE_8000_192000,
1015                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1016                         SNDRV_PCM_FMTBIT_S32_LE,
1017         },
1018         .capture = {
1019                 .stream_name = "Alt Analog CPU Capture",
1020                 .channels_min = HDA_MONO,
1021                 .channels_max = HDA_MAX,
1022                 .rates = SNDRV_PCM_RATE_8000_192000,
1023                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1024                         SNDRV_PCM_FMTBIT_S32_LE,
1025         },
1026 },
1027 {
1028         .name = "Digital CPU DAI",
1029         .ops = &skl_link_dai_ops,
1030         .playback = {
1031                 .stream_name = "Digital CPU Playback",
1032                 .channels_min = HDA_MONO,
1033                 .channels_max = HDA_MAX,
1034                 .rates = SNDRV_PCM_RATE_8000_192000,
1035                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1036                         SNDRV_PCM_FMTBIT_S32_LE,
1037         },
1038         .capture = {
1039                 .stream_name = "Digital CPU Capture",
1040                 .channels_min = HDA_MONO,
1041                 .channels_max = HDA_MAX,
1042                 .rates = SNDRV_PCM_RATE_8000_192000,
1043                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE |
1044                         SNDRV_PCM_FMTBIT_S32_LE,
1045         },
1046 },
1047 };
1048
1049 int skl_dai_load(struct snd_soc_component *cmp, int index,
1050                         struct snd_soc_dai_driver *dai_drv,
1051                         struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai)
1052 {
1053         dai_drv->ops = &skl_pcm_dai_ops;
1054
1055         return 0;
1056 }
1057
1058 static int skl_platform_soc_open(struct snd_soc_component *component,
1059                                  struct snd_pcm_substream *substream)
1060 {
1061         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1062         struct snd_soc_dai_link *dai_link = rtd->dai_link;
1063
1064         dev_dbg(snd_soc_rtd_to_cpu(rtd, 0)->dev, "In %s:%s\n", __func__,
1065                                         dai_link->cpus->dai_name);
1066
1067         snd_soc_set_runtime_hwparams(substream, &azx_pcm_hw);
1068
1069         return 0;
1070 }
1071
1072 static int skl_coupled_trigger(struct snd_pcm_substream *substream,
1073                                         int cmd)
1074 {
1075         struct hdac_bus *bus = get_bus_ctx(substream);
1076         struct hdac_ext_stream *stream;
1077         struct snd_pcm_substream *s;
1078         bool start;
1079         int sbits = 0;
1080         unsigned long cookie;
1081         struct hdac_stream *hstr;
1082
1083         stream = get_hdac_ext_stream(substream);
1084         hstr = hdac_stream(stream);
1085
1086         dev_dbg(bus->dev, "In %s cmd=%d\n", __func__, cmd);
1087
1088         if (!hstr->prepared)
1089                 return -EPIPE;
1090
1091         switch (cmd) {
1092         case SNDRV_PCM_TRIGGER_START:
1093         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1094         case SNDRV_PCM_TRIGGER_RESUME:
1095                 start = true;
1096                 break;
1097
1098         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1099         case SNDRV_PCM_TRIGGER_SUSPEND:
1100         case SNDRV_PCM_TRIGGER_STOP:
1101                 start = false;
1102                 break;
1103
1104         default:
1105                 return -EINVAL;
1106         }
1107
1108         snd_pcm_group_for_each_entry(s, substream) {
1109                 if (s->pcm->card != substream->pcm->card)
1110                         continue;
1111                 stream = get_hdac_ext_stream(s);
1112                 sbits |= 1 << hdac_stream(stream)->index;
1113                 snd_pcm_trigger_done(s, substream);
1114         }
1115
1116         spin_lock_irqsave(&bus->reg_lock, cookie);
1117
1118         /* first, set SYNC bits of corresponding streams */
1119         snd_hdac_stream_sync_trigger(hstr, true, sbits, AZX_REG_SSYNC);
1120
1121         snd_pcm_group_for_each_entry(s, substream) {
1122                 if (s->pcm->card != substream->pcm->card)
1123                         continue;
1124                 stream = get_hdac_ext_stream(s);
1125                 if (start)
1126                         snd_hdac_stream_start(hdac_stream(stream));
1127                 else
1128                         snd_hdac_stream_stop(hdac_stream(stream));
1129         }
1130         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1131
1132         snd_hdac_stream_sync(hstr, start, sbits);
1133
1134         spin_lock_irqsave(&bus->reg_lock, cookie);
1135
1136         /* reset SYNC bits */
1137         snd_hdac_stream_sync_trigger(hstr, false, sbits, AZX_REG_SSYNC);
1138         if (start)
1139                 snd_hdac_stream_timecounter_init(hstr, sbits);
1140         spin_unlock_irqrestore(&bus->reg_lock, cookie);
1141
1142         return 0;
1143 }
1144
1145 static int skl_platform_soc_trigger(struct snd_soc_component *component,
1146                                     struct snd_pcm_substream *substream,
1147                                     int cmd)
1148 {
1149         struct hdac_bus *bus = get_bus_ctx(substream);
1150
1151         if (!bus->ppcap)
1152                 return skl_coupled_trigger(substream, cmd);
1153
1154         return 0;
1155 }
1156
1157 static snd_pcm_uframes_t skl_platform_soc_pointer(
1158         struct snd_soc_component *component,
1159         struct snd_pcm_substream *substream)
1160 {
1161         struct hdac_ext_stream *hstream = get_hdac_ext_stream(substream);
1162         struct hdac_bus *bus = get_bus_ctx(substream);
1163         unsigned int pos;
1164
1165         /*
1166          * Use DPIB for Playback stream as the periodic DMA Position-in-
1167          * Buffer Writes may be scheduled at the same time or later than
1168          * the MSI and does not guarantee to reflect the Position of the
1169          * last buffer that was transferred. Whereas DPIB register in
1170          * HAD space reflects the actual data that is transferred.
1171          * Use the position buffer for capture, as DPIB write gets
1172          * completed earlier than the actual data written to the DDR.
1173          *
1174          * For capture stream following workaround is required to fix the
1175          * incorrect position reporting.
1176          *
1177          * 1. Wait for 20us before reading the DMA position in buffer once
1178          * the interrupt is generated for stream completion as update happens
1179          * on the HDA frame boundary i.e. 20.833uSec.
1180          * 2. Read DPIB register to flush the DMA position value. This dummy
1181          * read is required to flush DMA position value.
1182          * 3. Read the DMA Position-in-Buffer. This value now will be equal to
1183          * or greater than period boundary.
1184          */
1185
1186         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1187                 pos = readl(bus->remap_addr + AZX_REG_VS_SDXDPIB_XBASE +
1188                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1189                                 hdac_stream(hstream)->index));
1190         } else {
1191                 udelay(20);
1192                 readl(bus->remap_addr +
1193                                 AZX_REG_VS_SDXDPIB_XBASE +
1194                                 (AZX_REG_VS_SDXDPIB_XINTERVAL *
1195                                  hdac_stream(hstream)->index));
1196                 pos = snd_hdac_stream_get_pos_posbuf(hdac_stream(hstream));
1197         }
1198
1199         if (pos >= hdac_stream(hstream)->bufsize)
1200                 pos = 0;
1201
1202         return bytes_to_frames(substream->runtime, pos);
1203 }
1204
1205 static u64 skl_adjust_codec_delay(struct snd_pcm_substream *substream,
1206                                 u64 nsec)
1207 {
1208         struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1209         struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
1210         u64 codec_frames, codec_nsecs;
1211
1212         if (!codec_dai->driver->ops->delay)
1213                 return nsec;
1214
1215         codec_frames = codec_dai->driver->ops->delay(substream, codec_dai);
1216         codec_nsecs = div_u64(codec_frames * 1000000000LL,
1217                               substream->runtime->rate);
1218
1219         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1220                 return nsec + codec_nsecs;
1221
1222         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
1223 }
1224
1225 static int skl_platform_soc_get_time_info(
1226                         struct snd_soc_component *component,
1227                         struct snd_pcm_substream *substream,
1228                         struct timespec64 *system_ts, struct timespec64 *audio_ts,
1229                         struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
1230                         struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
1231 {
1232         struct hdac_ext_stream *sstream = get_hdac_ext_stream(substream);
1233         struct hdac_stream *hstr = hdac_stream(sstream);
1234         u64 nsec;
1235
1236         if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
1237                 (audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
1238
1239                 snd_pcm_gettime(substream->runtime, system_ts);
1240
1241                 nsec = timecounter_read(&hstr->tc);
1242                 if (audio_tstamp_config->report_delay)
1243                         nsec = skl_adjust_codec_delay(substream, nsec);
1244
1245                 *audio_ts = ns_to_timespec64(nsec);
1246
1247                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
1248                 audio_tstamp_report->accuracy_report = 1; /* rest of struct is valid */
1249                 audio_tstamp_report->accuracy = 42; /* 24MHzWallClk == 42ns resolution */
1250
1251         } else {
1252                 audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
1253         }
1254
1255         return 0;
1256 }
1257
1258 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
1259
1260 static int skl_platform_soc_new(struct snd_soc_component *component,
1261                                 struct snd_soc_pcm_runtime *rtd)
1262 {
1263         struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0);
1264         struct hdac_bus *bus = dev_get_drvdata(dai->dev);
1265         struct snd_pcm *pcm = rtd->pcm;
1266         unsigned int size;
1267         struct skl_dev *skl = bus_to_skl(bus);
1268
1269         if (dai->driver->playback.channels_min ||
1270                 dai->driver->capture.channels_min) {
1271                 /* buffer pre-allocation */
1272                 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
1273                 if (size > MAX_PREALLOC_SIZE)
1274                         size = MAX_PREALLOC_SIZE;
1275                 snd_pcm_set_managed_buffer_all(pcm,
1276                                                SNDRV_DMA_TYPE_DEV_SG,
1277                                                &skl->pci->dev,
1278                                                size, MAX_PREALLOC_SIZE);
1279         }
1280
1281         return 0;
1282 }
1283
1284 static int skl_get_module_info(struct skl_dev *skl,
1285                 struct skl_module_cfg *mconfig)
1286 {
1287         struct skl_module_inst_id *pin_id;
1288         guid_t *uuid_mod, *uuid_tplg;
1289         struct skl_module *skl_module;
1290         struct uuid_module *module;
1291         int i, ret = -EIO;
1292
1293         uuid_mod = (guid_t *)mconfig->guid;
1294
1295         if (list_empty(&skl->uuid_list)) {
1296                 dev_err(skl->dev, "Module list is empty\n");
1297                 return -EIO;
1298         }
1299
1300         for (i = 0; i < skl->nr_modules; i++) {
1301                 skl_module = skl->modules[i];
1302                 uuid_tplg = &skl_module->uuid;
1303                 if (guid_equal(uuid_mod, uuid_tplg)) {
1304                         mconfig->module = skl_module;
1305                         ret = 0;
1306                         break;
1307                 }
1308         }
1309
1310         if (skl->nr_modules && ret)
1311                 return ret;
1312
1313         ret = -EIO;
1314         list_for_each_entry(module, &skl->uuid_list, list) {
1315                 if (guid_equal(uuid_mod, &module->uuid)) {
1316                         mconfig->id.module_id = module->id;
1317                         mconfig->module->loadable = module->is_loadable;
1318                         ret = 0;
1319                 }
1320
1321                 for (i = 0; i < MAX_IN_QUEUE; i++) {
1322                         pin_id = &mconfig->m_in_pin[i].id;
1323                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1324                                 pin_id->module_id = module->id;
1325                 }
1326
1327                 for (i = 0; i < MAX_OUT_QUEUE; i++) {
1328                         pin_id = &mconfig->m_out_pin[i].id;
1329                         if (guid_equal(&pin_id->mod_uuid, &module->uuid))
1330                                 pin_id->module_id = module->id;
1331                 }
1332         }
1333
1334         return ret;
1335 }
1336
1337 static int skl_populate_modules(struct skl_dev *skl)
1338 {
1339         struct skl_pipeline *p;
1340         struct skl_pipe_module *m;
1341         struct snd_soc_dapm_widget *w;
1342         struct skl_module_cfg *mconfig;
1343         int ret = 0;
1344
1345         list_for_each_entry(p, &skl->ppl_list, node) {
1346                 list_for_each_entry(m, &p->pipe->w_list, node) {
1347                         w = m->w;
1348                         mconfig = w->priv;
1349
1350                         ret = skl_get_module_info(skl, mconfig);
1351                         if (ret < 0) {
1352                                 dev_err(skl->dev,
1353                                         "query module info failed\n");
1354                                 return ret;
1355                         }
1356
1357                         skl_tplg_add_moduleid_in_bind_params(skl, w);
1358                 }
1359         }
1360
1361         return ret;
1362 }
1363
1364 static int skl_platform_soc_probe(struct snd_soc_component *component)
1365 {
1366         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1367         struct skl_dev *skl = bus_to_skl(bus);
1368         const struct skl_dsp_ops *ops;
1369         int ret;
1370
1371         ret = pm_runtime_resume_and_get(component->dev);
1372         if (ret < 0 && ret != -EACCES)
1373                 return ret;
1374
1375         if (bus->ppcap) {
1376                 skl->component = component;
1377
1378                 /* init debugfs */
1379                 skl->debugfs = skl_debugfs_init(skl);
1380
1381                 ret = skl_tplg_init(component, bus);
1382                 if (ret < 0) {
1383                         dev_err(component->dev, "Failed to init topology!\n");
1384                         return ret;
1385                 }
1386
1387                 /* load the firmwares, since all is set */
1388                 ops = skl_get_dsp_ops(skl->pci->device);
1389                 if (!ops)
1390                         return -EIO;
1391
1392                 /*
1393                  * Disable dynamic clock and power gating during firmware
1394                  * and library download
1395                  */
1396                 skl->enable_miscbdcge(component->dev, false);
1397                 skl->clock_power_gating(component->dev, false);
1398
1399                 ret = ops->init_fw(component->dev, skl);
1400                 skl->enable_miscbdcge(component->dev, true);
1401                 skl->clock_power_gating(component->dev, true);
1402                 if (ret < 0) {
1403                         dev_err(component->dev, "Failed to boot first fw: %d\n", ret);
1404                         return ret;
1405                 }
1406                 skl_populate_modules(skl);
1407                 skl->update_d0i3c = skl_update_d0i3c;
1408
1409                 if (skl->cfg.astate_cfg != NULL) {
1410                         skl_dsp_set_astate_cfg(skl,
1411                                         skl->cfg.astate_cfg->count,
1412                                         skl->cfg.astate_cfg);
1413                 }
1414         }
1415         pm_runtime_mark_last_busy(component->dev);
1416         pm_runtime_put_autosuspend(component->dev);
1417
1418         return 0;
1419 }
1420
1421 static void skl_platform_soc_remove(struct snd_soc_component *component)
1422 {
1423         struct hdac_bus *bus = dev_get_drvdata(component->dev);
1424         struct skl_dev *skl = bus_to_skl(bus);
1425
1426         skl_tplg_exit(component, bus);
1427
1428         skl_debugfs_exit(skl);
1429 }
1430
1431 static const struct snd_soc_component_driver skl_component  = {
1432         .name           = "pcm",
1433         .probe          = skl_platform_soc_probe,
1434         .remove         = skl_platform_soc_remove,
1435         .open           = skl_platform_soc_open,
1436         .trigger        = skl_platform_soc_trigger,
1437         .pointer        = skl_platform_soc_pointer,
1438         .get_time_info  = skl_platform_soc_get_time_info,
1439         .pcm_construct  = skl_platform_soc_new,
1440         .module_get_upon_open = 1, /* increment refcount when a pcm is opened */
1441 };
1442
1443 int skl_platform_register(struct device *dev)
1444 {
1445         int ret;
1446         struct snd_soc_dai_driver *dais;
1447         int num_dais = ARRAY_SIZE(skl_platform_dai);
1448         struct hdac_bus *bus = dev_get_drvdata(dev);
1449         struct skl_dev *skl = bus_to_skl(bus);
1450
1451         skl->dais = kmemdup(skl_platform_dai, sizeof(skl_platform_dai),
1452                             GFP_KERNEL);
1453         if (!skl->dais) {
1454                 ret = -ENOMEM;
1455                 goto err;
1456         }
1457
1458         if (!skl->use_tplg_pcm) {
1459                 dais = krealloc(skl->dais, sizeof(skl_fe_dai) +
1460                                 sizeof(skl_platform_dai), GFP_KERNEL);
1461                 if (!dais) {
1462                         ret = -ENOMEM;
1463                         goto err;
1464                 }
1465
1466                 skl->dais = dais;
1467                 memcpy(&skl->dais[ARRAY_SIZE(skl_platform_dai)], skl_fe_dai,
1468                        sizeof(skl_fe_dai));
1469                 num_dais += ARRAY_SIZE(skl_fe_dai);
1470         }
1471
1472         ret = devm_snd_soc_register_component(dev, &skl_component,
1473                                          skl->dais, num_dais);
1474         if (ret)
1475                 dev_err(dev, "soc component registration failed %d\n", ret);
1476 err:
1477         return ret;
1478 }
1479
1480 int skl_platform_unregister(struct device *dev)
1481 {
1482         struct hdac_bus *bus = dev_get_drvdata(dev);
1483         struct skl_dev *skl = bus_to_skl(bus);
1484         struct skl_module_deferred_bind *modules, *tmp;
1485
1486         list_for_each_entry_safe(modules, tmp, &skl->bind_list, node) {
1487                 list_del(&modules->node);
1488                 kfree(modules);
1489         }
1490
1491         kfree(skl->dais);
1492
1493         return 0;
1494 }