2 * bxt-sst.c - DSP library functions for BXT platform
4 * Copyright (C) 2015-16 Intel Corp
5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
6 * Jeeja KP <jeeja.kp@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/device.h>
23 #include "../common/sst-dsp.h"
24 #include "../common/sst-dsp-priv.h"
25 #include "skl-sst-ipc.h"
27 #define BXT_BASEFW_TIMEOUT 3000
28 #define BXT_INIT_TIMEOUT 500
29 #define BXT_IPC_PURGE_FW 0x01004000
31 #define BXT_ROM_INIT 0x5
32 #define BXT_ADSP_SRAM0_BASE 0x80000
34 /* Firmware status window */
35 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
36 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
38 #define BXT_ADSP_SRAM1_BASE 0xA0000
40 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
42 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
45 static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
46 const void *fwdata, u32 fwsize)
48 int stream_tag, ret, i;
51 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
53 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
58 ctx->dsp_ops.stream_tag = stream_tag;
59 memcpy(ctx->dmab.area, fwdata, fwsize);
61 /* Purge FW request */
62 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
63 BXT_IPC_PURGE_FW | (stream_tag - 1));
65 ret = skl_dsp_enable_core(ctx);
67 dev_err(ctx->dev, "Boot dsp core failed ret: %d\n", ret);
69 goto base_fw_load_failed;
72 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
73 reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
75 if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
76 sst_dsp_shim_update_bits_forced(ctx,
78 SKL_ADSP_REG_HIPCIE_DONE,
79 SKL_ADSP_REG_HIPCIE_DONE);
85 dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
86 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
87 SKL_ADSP_REG_HIPCIE_DONE,
88 SKL_ADSP_REG_HIPCIE_DONE);
91 /* enable Interrupt */
92 skl_ipc_int_enable(ctx);
93 skl_ipc_op_int_enable(ctx);
95 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
97 (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
100 dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
106 dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
108 goto base_fw_load_failed;
114 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
115 skl_dsp_disable_core(ctx);
119 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
123 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
124 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
125 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
127 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
128 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
133 static int bxt_load_base_firmware(struct sst_dsp *ctx)
135 const struct firmware *fw = NULL;
136 struct skl_sst *skl = ctx->thread_context;
139 ret = request_firmware(&fw, ctx->fw_name, ctx->dev);
141 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
142 goto sst_load_base_firmware_failed;
145 ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
146 /* Retry Enabling core and ROM load. Retry seemed to help */
148 ret = sst_bxt_prepare_fw(ctx, fw->data, fw->size);
150 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
151 goto sst_load_base_firmware_failed;
155 ret = sst_transfer_fw_host_dma(ctx);
157 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
158 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
159 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
160 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
162 skl_dsp_disable_core(ctx);
164 dev_dbg(ctx->dev, "Firmware download successful\n");
165 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
166 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
168 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
169 skl_dsp_disable_core(ctx);
172 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
177 sst_load_base_firmware_failed:
178 release_firmware(fw);
182 static int bxt_set_dsp_D0(struct sst_dsp *ctx)
184 struct skl_sst *skl = ctx->thread_context;
187 skl->boot_complete = false;
189 ret = skl_dsp_enable_core(ctx);
191 dev_err(ctx->dev, "enable dsp core failed ret: %d\n", ret);
195 /* enable interrupt */
196 skl_ipc_int_enable(ctx);
197 skl_ipc_op_int_enable(ctx);
199 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
200 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
202 dev_err(ctx->dev, "ipc: error DSP boot timeout\n");
203 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
204 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
205 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
209 skl_dsp_set_state_locked(ctx, SKL_DSP_RUNNING);
213 static int bxt_set_dsp_D3(struct sst_dsp *ctx)
215 struct skl_ipc_dxstate_info dx;
216 struct skl_sst *skl = ctx->thread_context;
219 if (!is_skl_dsp_running(ctx))
222 dx.core_mask = SKL_DSP_CORE0_MASK;
223 dx.dx_mask = SKL_IPC_D3_MASK;
225 ret = skl_ipc_set_dx(&skl->ipc, SKL_INSTANCE_ID,
226 SKL_BASE_FW_MODULE_ID, &dx);
228 dev_err(ctx->dev, "Failed to set DSP to D3 state: %d\n", ret);
232 ret = skl_dsp_disable_core(ctx);
234 dev_err(ctx->dev, "disbale dsp core failed: %d\n", ret);
238 skl_dsp_set_state_locked(ctx, SKL_DSP_RESET);
242 static struct skl_dsp_fw_ops bxt_fw_ops = {
243 .set_state_D0 = bxt_set_dsp_D0,
244 .set_state_D3 = bxt_set_dsp_D3,
245 .load_fw = bxt_load_base_firmware,
246 .get_fw_errcode = bxt_get_errorcode,
249 static struct sst_ops skl_ops = {
250 .irq_handler = skl_dsp_sst_interrupt,
251 .write = sst_shim32_write,
252 .read = sst_shim32_read,
253 .ram_read = sst_memcpy_fromio_32,
254 .ram_write = sst_memcpy_toio_32,
255 .free = skl_dsp_free,
258 static struct sst_dsp_device skl_dev = {
259 .thread = skl_dsp_irq_thread_handler,
263 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
264 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
265 struct skl_sst **dsp)
271 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
276 skl_dev.thread_context = skl;
278 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
280 dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
285 sst->fw_name = fw_name;
286 sst->dsp_ops = dsp_ops;
287 sst->fw_ops = bxt_fw_ops;
288 sst->addr.lpe = mmio_base;
289 sst->addr.shim = mmio_base;
291 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
292 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
294 ret = skl_ipc_init(dev, skl);
298 skl->boot_complete = false;
299 init_waitqueue_head(&skl->boot_wait);
301 ret = sst->fw_ops.load_fw(sst);
303 dev_err(dev, "Load base fw failed: %x", ret);
312 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
315 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
317 skl_ipc_free(&ctx->ipc);
318 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
320 if (ctx->dsp->addr.lpe)
321 iounmap(ctx->dsp->addr.lpe);
323 ctx->dsp->ops->free(ctx->dsp);
325 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
327 MODULE_LICENSE("GPL v2");
328 MODULE_DESCRIPTION("Intel Broxton IPC driver");