2 * bxt-sst.c - DSP library functions for BXT platform
4 * Copyright (C) 2015-16 Intel Corp
5 * Author:Rafal Redzimski <rafal.f.redzimski@intel.com>
6 * Jeeja KP <jeeja.kp@intel.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/delay.h>
20 #include <linux/firmware.h>
21 #include <linux/device.h>
23 #include "../common/sst-dsp.h"
24 #include "../common/sst-dsp-priv.h"
25 #include "skl-sst-ipc.h"
27 #define BXT_BASEFW_TIMEOUT 3000
28 #define BXT_INIT_TIMEOUT 500
29 #define BXT_IPC_PURGE_FW 0x01004000
31 #define BXT_ROM_INIT 0x5
32 #define BXT_ADSP_SRAM0_BASE 0x80000
34 /* Firmware status window */
35 #define BXT_ADSP_FW_STATUS BXT_ADSP_SRAM0_BASE
36 #define BXT_ADSP_ERROR_CODE (BXT_ADSP_FW_STATUS + 0x4)
38 #define BXT_ADSP_SRAM1_BASE 0xA0000
40 #define BXT_INSTANCE_ID 0
41 #define BXT_BASE_FW_MODULE_ID 0
43 static unsigned int bxt_get_errorcode(struct sst_dsp *ctx)
45 return sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE);
49 * First boot sequence has some extra steps. Core 0 waits for power
50 * status on core 1, so power up core 1 also momentarily, keep it in
51 * reset/stall and then turn it off
53 static int sst_bxt_prepare_fw(struct sst_dsp *ctx,
54 const void *fwdata, u32 fwsize)
56 int stream_tag, ret, i;
59 stream_tag = ctx->dsp_ops.prepare(ctx->dev, 0x40, fwsize, &ctx->dmab);
60 if (stream_tag <= 0) {
61 dev_err(ctx->dev, "Failed to prepare DMA FW loading err: %x\n",
66 ctx->dsp_ops.stream_tag = stream_tag;
67 memcpy(ctx->dmab.area, fwdata, fwsize);
69 /* Step 1: Power up core 0 and core1 */
70 ret = skl_dsp_core_power_up(ctx, SKL_DSP_CORE0_MASK |
71 SKL_DSP_CORE_MASK(1));
73 dev_err(ctx->dev, "dsp core0/1 power up failed\n");
74 goto base_fw_load_failed;
77 /* Step 2: Purge FW request */
78 sst_dsp_shim_write(ctx, SKL_ADSP_REG_HIPCI, SKL_ADSP_REG_HIPCI_BUSY |
79 (BXT_IPC_PURGE_FW | ((stream_tag - 1) << 9)));
81 /* Step 3: Unset core0 reset state & unstall/run core0 */
82 ret = skl_dsp_start_core(ctx, SKL_DSP_CORE0_MASK);
84 dev_err(ctx->dev, "Start dsp core failed ret: %d\n", ret);
86 goto base_fw_load_failed;
89 /* Step 4: Wait for DONE Bit */
90 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
91 reg = sst_dsp_shim_read(ctx, SKL_ADSP_REG_HIPCIE);
93 if (reg & SKL_ADSP_REG_HIPCIE_DONE) {
94 sst_dsp_shim_update_bits_forced(ctx,
96 SKL_ADSP_REG_HIPCIE_DONE,
97 SKL_ADSP_REG_HIPCIE_DONE);
103 dev_info(ctx->dev, "Waiting for HIPCIE done, reg: 0x%x\n", reg);
104 sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_HIPCIE,
105 SKL_ADSP_REG_HIPCIE_DONE,
106 SKL_ADSP_REG_HIPCIE_DONE);
109 /* Step 5: power down core1 */
110 ret = skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
112 dev_err(ctx->dev, "dsp core1 power down failed\n");
113 goto base_fw_load_failed;
116 /* Step 6: Enable Interrupt */
117 skl_ipc_int_enable(ctx);
118 skl_ipc_op_int_enable(ctx);
120 /* Step 7: Wait for ROM init */
121 for (i = BXT_INIT_TIMEOUT; i > 0; --i) {
123 (sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS) &
126 dev_info(ctx->dev, "ROM loaded, continue FW loading\n");
132 dev_err(ctx->dev, "Timeout for ROM init, HIPCIE: 0x%x\n", reg);
134 goto base_fw_load_failed;
140 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, stream_tag);
141 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
142 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
146 static int sst_transfer_fw_host_dma(struct sst_dsp *ctx)
150 ctx->dsp_ops.trigger(ctx->dev, true, ctx->dsp_ops.stream_tag);
151 ret = sst_dsp_register_poll(ctx, BXT_ADSP_FW_STATUS, SKL_FW_STS_MASK,
152 BXT_ROM_INIT, BXT_BASEFW_TIMEOUT, "Firmware boot");
154 ctx->dsp_ops.trigger(ctx->dev, false, ctx->dsp_ops.stream_tag);
155 ctx->dsp_ops.cleanup(ctx->dev, &ctx->dmab, ctx->dsp_ops.stream_tag);
160 #define BXT_ADSP_FW_BIN_HDR_OFFSET 0x2000
162 static int bxt_load_base_firmware(struct sst_dsp *ctx)
164 struct firmware stripped_fw;
165 struct skl_sst *skl = ctx->thread_context;
168 ret = request_firmware(&ctx->fw, ctx->fw_name, ctx->dev);
170 dev_err(ctx->dev, "Request firmware failed %d\n", ret);
171 goto sst_load_base_firmware_failed;
174 /* check for extended manifest */
176 goto sst_load_base_firmware_failed;
178 ret = snd_skl_parse_uuids(ctx, BXT_ADSP_FW_BIN_HDR_OFFSET);
180 goto sst_load_base_firmware_failed;
182 stripped_fw.data = ctx->fw->data;
183 stripped_fw.size = ctx->fw->size;
184 skl_dsp_strip_extended_manifest(&stripped_fw);
186 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
187 /* Retry Enabling core and ROM load. Retry seemed to help */
189 ret = sst_bxt_prepare_fw(ctx, stripped_fw.data, stripped_fw.size);
191 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
192 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
193 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
195 dev_err(ctx->dev, "Core En/ROM load fail:%d\n", ret);
196 goto sst_load_base_firmware_failed;
200 ret = sst_transfer_fw_host_dma(ctx);
202 dev_err(ctx->dev, "Transfer firmware failed %d\n", ret);
203 dev_info(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
204 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
205 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
207 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
209 dev_dbg(ctx->dev, "Firmware download successful\n");
210 ret = wait_event_timeout(skl->boot_wait, skl->boot_complete,
211 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
213 dev_err(ctx->dev, "DSP boot fail, FW Ready timeout\n");
214 skl_dsp_disable_core(ctx, SKL_DSP_CORE0_MASK);
218 skl->fw_loaded = true;
222 sst_load_base_firmware_failed:
223 release_firmware(ctx->fw);
227 static int bxt_set_dsp_D0(struct sst_dsp *ctx, unsigned int core_id)
229 struct skl_sst *skl = ctx->thread_context;
231 struct skl_ipc_dxstate_info dx;
232 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
234 if (skl->fw_loaded == false) {
235 skl->boot_complete = false;
236 ret = bxt_load_base_firmware(ctx);
238 dev_err(ctx->dev, "reload fw failed: %d\n", ret);
242 /* If core 0 is being turned on, turn on core 1 as well */
243 if (core_id == SKL_DSP_CORE0_ID)
244 ret = skl_dsp_core_power_up(ctx, core_mask |
245 SKL_DSP_CORE_MASK(1));
247 ret = skl_dsp_core_power_up(ctx, core_mask);
252 if (core_id == SKL_DSP_CORE0_ID) {
255 * Enable interrupt after SPA is set and before
258 skl_ipc_int_enable(ctx);
259 skl_ipc_op_int_enable(ctx);
260 skl->boot_complete = false;
263 ret = skl_dsp_start_core(ctx, core_mask);
267 if (core_id == SKL_DSP_CORE0_ID) {
268 ret = wait_event_timeout(skl->boot_wait,
270 msecs_to_jiffies(SKL_IPC_BOOT_MSECS));
272 /* If core 1 was turned on for booting core 0, turn it off */
273 skl_dsp_core_power_down(ctx, SKL_DSP_CORE_MASK(1));
275 dev_err(ctx->dev, "%s: DSP boot timeout\n", __func__);
276 dev_err(ctx->dev, "Error code=0x%x: FW status=0x%x\n",
277 sst_dsp_shim_read(ctx, BXT_ADSP_ERROR_CODE),
278 sst_dsp_shim_read(ctx, BXT_ADSP_FW_STATUS));
279 dev_err(ctx->dev, "Failed to set core0 to D0 state\n");
285 /* Tell FW if additional core in now On */
287 if (core_id != SKL_DSP_CORE0_ID) {
288 dx.core_mask = core_mask;
289 dx.dx_mask = core_mask;
291 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
292 BXT_BASE_FW_MODULE_ID, &dx);
294 dev_err(ctx->dev, "IPC set_dx for core %d fail: %d\n",
300 skl->cores.state[core_id] = SKL_DSP_RUNNING;
303 if (core_id == SKL_DSP_CORE0_ID)
304 core_mask |= SKL_DSP_CORE_MASK(1);
305 skl_dsp_disable_core(ctx, core_mask);
310 static int bxt_set_dsp_D3(struct sst_dsp *ctx, unsigned int core_id)
313 struct skl_ipc_dxstate_info dx;
314 struct skl_sst *skl = ctx->thread_context;
315 unsigned int core_mask = SKL_DSP_CORE_MASK(core_id);
317 dx.core_mask = core_mask;
318 dx.dx_mask = SKL_IPC_D3_MASK;
320 dev_dbg(ctx->dev, "core mask=%x dx_mask=%x\n",
321 dx.core_mask, dx.dx_mask);
323 ret = skl_ipc_set_dx(&skl->ipc, BXT_INSTANCE_ID,
324 BXT_BASE_FW_MODULE_ID, &dx);
327 "Failed to set DSP to D3:core id = %d;Continue reset\n",
330 ret = skl_dsp_disable_core(ctx, core_mask);
332 dev_err(ctx->dev, "Failed to disable core %d", ret);
335 skl->cores.state[core_id] = SKL_DSP_RESET;
339 static struct skl_dsp_fw_ops bxt_fw_ops = {
340 .set_state_D0 = bxt_set_dsp_D0,
341 .set_state_D3 = bxt_set_dsp_D3,
342 .load_fw = bxt_load_base_firmware,
343 .get_fw_errcode = bxt_get_errorcode,
346 static struct sst_ops skl_ops = {
347 .irq_handler = skl_dsp_sst_interrupt,
348 .write = sst_shim32_write,
349 .read = sst_shim32_read,
350 .ram_read = sst_memcpy_fromio_32,
351 .ram_write = sst_memcpy_toio_32,
352 .free = skl_dsp_free,
355 static struct sst_dsp_device skl_dev = {
356 .thread = skl_dsp_irq_thread_handler,
360 int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
361 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
362 struct skl_sst **dsp)
368 skl = devm_kzalloc(dev, sizeof(*skl), GFP_KERNEL);
373 skl_dev.thread_context = skl;
374 INIT_LIST_HEAD(&skl->uuid_list);
376 skl->dsp = skl_dsp_ctx_init(dev, &skl_dev, irq);
378 dev_err(skl->dev, "skl_dsp_ctx_init failed\n");
383 sst->fw_name = fw_name;
384 sst->dsp_ops = dsp_ops;
385 sst->fw_ops = bxt_fw_ops;
386 sst->addr.lpe = mmio_base;
387 sst->addr.shim = mmio_base;
389 sst_dsp_mailbox_init(sst, (BXT_ADSP_SRAM0_BASE + SKL_ADSP_W0_STAT_SZ),
390 SKL_ADSP_W0_UP_SZ, BXT_ADSP_SRAM1_BASE, SKL_ADSP_W1_SZ);
392 INIT_LIST_HEAD(&sst->module_list);
393 ret = skl_ipc_init(dev, skl);
397 skl->cores.count = 2;
398 skl->boot_complete = false;
399 init_waitqueue_head(&skl->boot_wait);
401 ret = sst->fw_ops.load_fw(sst);
403 dev_err(dev, "Load base fw failed: %x", ret);
407 skl_dsp_init_core_state(sst);
414 EXPORT_SYMBOL_GPL(bxt_sst_dsp_init);
417 void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx)
419 skl_freeup_uuid_list(ctx);
420 skl_ipc_free(&ctx->ipc);
421 ctx->dsp->cl_dev.ops.cl_cleanup_controller(ctx->dsp);
423 if (ctx->dsp->addr.lpe)
424 iounmap(ctx->dsp->addr.lpe);
426 ctx->dsp->ops->free(ctx->dsp);
428 EXPORT_SYMBOL_GPL(bxt_sst_dsp_cleanup);
430 MODULE_LICENSE("GPL v2");
431 MODULE_DESCRIPTION("Intel Broxton IPC driver");