2 * Freescale SSI ALSA SoC Digital Audio Interface (DAI) driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2010 Freescale Semiconductor, Inc.
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
13 * Some notes why imx-pcm-fiq is used instead of DMA on some boards:
15 * The i.MX SSI core has some nasty limitations in AC97 mode. While most
16 * sane processor vendors have a FIFO per AC97 slot, the i.MX has only
17 * one FIFO which combines all valid receive slots. We cannot even select
18 * which slots we want to receive. The WM9712 with which this driver
19 * was developed with always sends GPIO status data in slot 12 which
20 * we receive in our (PCM-) data stream. The only chance we have is to
21 * manually skip this data in the FIQ handler. With sampling rates different
22 * from 48000Hz not every frame has valid receive data, so the ratio
23 * between pcm data and GPIO status data changes. Our FIQ handler is not
24 * able to handle this, hence this driver only works with 48000Hz sampling
26 * Reading and writing AC97 registers is another challenge. The core
27 * provides us status bits when the read register is updated with *another*
28 * value. When we read the same register two times (and the register still
29 * contains the same value) these status bits are not set. We work
30 * around this by not polling these bits but only wait a fixed delay.
33 #include <linux/init.h>
35 #include <linux/module.h>
36 #include <linux/interrupt.h>
37 #include <linux/clk.h>
38 #include <linux/device.h>
39 #include <linux/delay.h>
40 #include <linux/slab.h>
41 #include <linux/of_address.h>
42 #include <linux/of_irq.h>
43 #include <linux/of_platform.h>
45 #include <sound/core.h>
46 #include <sound/pcm.h>
47 #include <sound/pcm_params.h>
48 #include <sound/initval.h>
49 #include <sound/soc.h>
50 #include <sound/dmaengine_pcm.h>
56 #define read_ssi(addr) in_be32(addr)
57 #define write_ssi(val, addr) out_be32(addr, val)
58 #define write_ssi_mask(addr, clear, set) clrsetbits_be32(addr, clear, set)
60 #define read_ssi(addr) readl(addr)
61 #define write_ssi(val, addr) writel(val, addr)
63 * FIXME: Proper locking should be added at write_ssi_mask caller level
64 * to ensure this register read/modify/write sequence is race free.
66 static inline void write_ssi_mask(u32 __iomem *addr, u32 clear, u32 set)
68 u32 val = readl(addr);
69 val = (val & ~clear) | set;
75 * FSLSSI_I2S_RATES: sample rates supported by the I2S
77 * This driver currently only supports the SSI running in I2S slave mode,
78 * which means the codec determines the sample rate. Therefore, we tell
79 * ALSA that we support all rates and let the codec driver decide what rates
80 * are really supported.
82 #define FSLSSI_I2S_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
83 SNDRV_PCM_RATE_CONTINUOUS)
86 * FSLSSI_I2S_FORMATS: audio formats supported by the SSI
88 * This driver currently only supports the SSI running in I2S slave mode.
90 * The SSI has a limitation in that the samples must be in the same byte
91 * order as the host CPU. This is because when multiple bytes are written
92 * to the STX register, the bytes and bits must be written in the same
93 * order. The STX is a shift register, so all the bits need to be aligned
94 * (bit-endianness must match byte-endianness). Processors typically write
95 * the bits within a byte in the same order that the bytes of a word are
96 * written in. So if the host CPU is big-endian, then only big-endian
97 * samples will be written to STX properly.
100 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_BE | \
101 SNDRV_PCM_FMTBIT_S18_3BE | SNDRV_PCM_FMTBIT_S20_3BE | \
102 SNDRV_PCM_FMTBIT_S24_3BE | SNDRV_PCM_FMTBIT_S24_BE)
104 #define FSLSSI_I2S_FORMATS (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | \
105 SNDRV_PCM_FMTBIT_S18_3LE | SNDRV_PCM_FMTBIT_S20_3LE | \
106 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S24_LE)
109 /* SIER bitflag of interrupts to enable */
110 #define SIER_FLAGS (CCSR_SSI_SIER_TFRC_EN | CCSR_SSI_SIER_TDMAE | \
111 CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TUE0_EN | \
112 CCSR_SSI_SIER_TUE1_EN | CCSR_SSI_SIER_RFRC_EN | \
113 CCSR_SSI_SIER_RDMAE | CCSR_SSI_SIER_RIE | \
114 CCSR_SSI_SIER_ROE0_EN | CCSR_SSI_SIER_ROE1_EN)
117 * fsl_ssi_private: per-SSI private data
119 * @ssi: pointer to the SSI's registers
120 * @ssi_phys: physical address of the SSI registers
121 * @irq: IRQ of this SSI
122 * @first_stream: pointer to the stream that was opened first
123 * @second_stream: pointer to second stream
124 * @playback: the number of playback streams opened
125 * @capture: the number of capture streams opened
126 * @cpu_dai: the CPU DAI for this device
127 * @dev_attr: the sysfs device attribute structure
128 * @stats: SSI statistics
129 * @name: name for this device
131 struct fsl_ssi_private {
132 struct ccsr_ssi __iomem *ssi;
135 struct snd_pcm_substream *first_stream;
136 struct snd_pcm_substream *second_stream;
137 unsigned int fifo_depth;
138 struct snd_soc_dai_driver cpu_dai_drv;
139 struct device_attribute dev_attr;
140 struct platform_device *pdev;
147 struct snd_dmaengine_dai_dma_data dma_params_tx;
148 struct snd_dmaengine_dai_dma_data dma_params_rx;
149 struct imx_dma_data filter_data_tx;
150 struct imx_dma_data filter_data_rx;
151 struct imx_pcm_fiq_params fiq_params;
181 * fsl_ssi_isr: SSI interrupt handler
183 * Although it's possible to use the interrupt handler to send and receive
184 * data to/from the SSI, we use the DMA instead. Programming is more
185 * complicated, but the performance is much better.
187 * This interrupt handler is used only to gather statistics.
189 * @irq: IRQ of the SSI device
190 * @dev_id: pointer to the ssi_private structure for this SSI device
192 static irqreturn_t fsl_ssi_isr(int irq, void *dev_id)
194 struct fsl_ssi_private *ssi_private = dev_id;
195 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
196 irqreturn_t ret = IRQ_NONE;
200 /* We got an interrupt, so read the status register to see what we
201 were interrupted for. We mask it with the Interrupt Enable register
202 so that we only check for events that we're interested in.
204 sisr = read_ssi(&ssi->sisr) & SIER_FLAGS;
206 if (sisr & CCSR_SSI_SISR_RFRC) {
207 ssi_private->stats.rfrc++;
208 sisr2 |= CCSR_SSI_SISR_RFRC;
212 if (sisr & CCSR_SSI_SISR_TFRC) {
213 ssi_private->stats.tfrc++;
214 sisr2 |= CCSR_SSI_SISR_TFRC;
218 if (sisr & CCSR_SSI_SISR_CMDAU) {
219 ssi_private->stats.cmdau++;
223 if (sisr & CCSR_SSI_SISR_CMDDU) {
224 ssi_private->stats.cmddu++;
228 if (sisr & CCSR_SSI_SISR_RXT) {
229 ssi_private->stats.rxt++;
233 if (sisr & CCSR_SSI_SISR_RDR1) {
234 ssi_private->stats.rdr1++;
238 if (sisr & CCSR_SSI_SISR_RDR0) {
239 ssi_private->stats.rdr0++;
243 if (sisr & CCSR_SSI_SISR_TDE1) {
244 ssi_private->stats.tde1++;
248 if (sisr & CCSR_SSI_SISR_TDE0) {
249 ssi_private->stats.tde0++;
253 if (sisr & CCSR_SSI_SISR_ROE1) {
254 ssi_private->stats.roe1++;
255 sisr2 |= CCSR_SSI_SISR_ROE1;
259 if (sisr & CCSR_SSI_SISR_ROE0) {
260 ssi_private->stats.roe0++;
261 sisr2 |= CCSR_SSI_SISR_ROE0;
265 if (sisr & CCSR_SSI_SISR_TUE1) {
266 ssi_private->stats.tue1++;
267 sisr2 |= CCSR_SSI_SISR_TUE1;
271 if (sisr & CCSR_SSI_SISR_TUE0) {
272 ssi_private->stats.tue0++;
273 sisr2 |= CCSR_SSI_SISR_TUE0;
277 if (sisr & CCSR_SSI_SISR_TFS) {
278 ssi_private->stats.tfs++;
282 if (sisr & CCSR_SSI_SISR_RFS) {
283 ssi_private->stats.rfs++;
287 if (sisr & CCSR_SSI_SISR_TLS) {
288 ssi_private->stats.tls++;
292 if (sisr & CCSR_SSI_SISR_RLS) {
293 ssi_private->stats.rls++;
297 if (sisr & CCSR_SSI_SISR_RFF1) {
298 ssi_private->stats.rff1++;
302 if (sisr & CCSR_SSI_SISR_RFF0) {
303 ssi_private->stats.rff0++;
307 if (sisr & CCSR_SSI_SISR_TFE1) {
308 ssi_private->stats.tfe1++;
312 if (sisr & CCSR_SSI_SISR_TFE0) {
313 ssi_private->stats.tfe0++;
317 /* Clear the bits that we set */
319 write_ssi(sisr2, &ssi->sisr);
324 static int fsl_ssi_setup(struct fsl_ssi_private *ssi_private)
326 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
329 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
331 if (ssi_private->imx_ac97)
332 i2s_mode = CCSR_SSI_SCR_I2S_MODE_NORMAL | CCSR_SSI_SCR_NET;
334 i2s_mode = CCSR_SSI_SCR_I2S_MODE_SLAVE;
337 * Section 16.5 of the MPC8610 reference manual says that the SSI needs
338 * to be disabled before updating the registers we set here.
340 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
343 * Program the SSI into I2S Slave Non-Network Synchronous mode. Also
344 * enable the transmit and receive FIFO.
346 * FIXME: Little-endian samples require a different shift dir
348 write_ssi_mask(&ssi->scr,
349 CCSR_SSI_SCR_I2S_MODE_MASK | CCSR_SSI_SCR_SYN,
350 CCSR_SSI_SCR_TFR_CLK_DIS |
352 (synchronous ? CCSR_SSI_SCR_SYN : 0));
354 write_ssi(CCSR_SSI_STCR_TXBIT0 | CCSR_SSI_STCR_TFEN0 |
355 CCSR_SSI_STCR_TFSI | CCSR_SSI_STCR_TEFS |
356 CCSR_SSI_STCR_TSCKP, &ssi->stcr);
358 write_ssi(CCSR_SSI_SRCR_RXBIT0 | CCSR_SSI_SRCR_RFEN0 |
359 CCSR_SSI_SRCR_RFSI | CCSR_SSI_SRCR_REFS |
360 CCSR_SSI_SRCR_RSCKP, &ssi->srcr);
362 * The DC and PM bits are only used if the SSI is the clock master.
366 * Set the watermark for transmit FIFI 0 and receive FIFO 0. We don't
367 * use FIFO 1. We program the transmit water to signal a DMA transfer
368 * if there are only two (or fewer) elements left in the FIFO. Two
369 * elements equals one frame (left channel, right channel). This value,
370 * however, depends on the depth of the transmit buffer.
372 * We set the watermark on the same level as the DMA burstsize. For
373 * fiq it is probably better to use the biggest possible watermark
376 if (ssi_private->use_dma)
377 wm = ssi_private->fifo_depth - 2;
379 wm = ssi_private->fifo_depth;
381 write_ssi(CCSR_SSI_SFCSR_TFWM0(wm) | CCSR_SSI_SFCSR_RFWM0(wm) |
382 CCSR_SSI_SFCSR_TFWM1(wm) | CCSR_SSI_SFCSR_RFWM1(wm),
386 * For non-ac97 setups, we keep the SSI disabled because if we enable
387 * it, then the DMA controller will start. It's not supposed to start
388 * until the SCR.TE (or SCR.RE) bit is set, but it does anyway. The DMA
389 * controller will transfer one "BWC" of data (i.e. the amount of data
390 * that the MR.BWC bits are set to). The reason this is bad is because
391 * at this point, the PCM driver has not finished initializing the DMA
397 * For ac97 interrupts are enabled with the startup of the substream
398 * because it is also running without an active substream. Normally SSI
399 * is only enabled when there is a substream.
401 if (!ssi_private->imx_ac97) {
402 /* Enable the interrupts and DMA requests */
403 if (ssi_private->use_dma)
404 write_ssi(SIER_FLAGS, &ssi->sier);
406 write_ssi(CCSR_SSI_SIER_TIE | CCSR_SSI_SIER_TFE0_EN |
408 CCSR_SSI_SIER_RFF0_EN, &ssi->sier);
411 * Setup the clock control register
413 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
415 write_ssi(CCSR_SSI_SxCCR_WL(17) | CCSR_SSI_SxCCR_DC(13),
419 * Enable AC97 mode and startup the SSI
421 write_ssi(CCSR_SSI_SACNT_AC97EN | CCSR_SSI_SACNT_FV,
423 write_ssi(0xff, &ssi->saccdis);
424 write_ssi(0x300, &ssi->saccen);
427 * Enable SSI, Transmit and Receive
429 write_ssi_mask(&ssi->scr, 0, CCSR_SSI_SCR_SSIEN |
430 CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE);
432 write_ssi(CCSR_SSI_SOR_WAIT(3), &ssi->sor);
440 * fsl_ssi_startup: create a new substream
442 * This is the first function called when a stream is opened.
444 * If this is the first stream open, then grab the IRQ and program most of
447 static int fsl_ssi_startup(struct snd_pcm_substream *substream,
448 struct snd_soc_dai *dai)
450 struct snd_soc_pcm_runtime *rtd = substream->private_data;
451 struct fsl_ssi_private *ssi_private =
452 snd_soc_dai_get_drvdata(rtd->cpu_dai);
453 int synchronous = ssi_private->cpu_dai_drv.symmetric_rates;
456 * If this is the first stream opened, then request the IRQ
457 * and initialize the SSI registers.
459 if (!ssi_private->first_stream) {
460 ssi_private->first_stream = substream;
463 * fsl_ssi_setup was already called by ac97_init earlier if
464 * the driver is in ac97 mode.
466 if (!ssi_private->imx_ac97)
467 fsl_ssi_setup(ssi_private);
470 struct snd_pcm_runtime *first_runtime =
471 ssi_private->first_stream->runtime;
473 * This is the second stream open, and we're in
474 * synchronous mode, so we need to impose sample
475 * sample size constraints. This is because STCCR is
476 * used for playback and capture in synchronous mode,
477 * so there's no way to specify different word
480 * Note that this can cause a race condition if the
481 * second stream is opened before the first stream is
482 * fully initialized. We provide some protection by
483 * checking to make sure the first stream is
484 * initialized, but it's not perfect. ALSA sometimes
485 * re-initializes the driver with a different sample
486 * rate or size. If the second stream is opened
487 * before the first stream has received its final
488 * parameters, then the second stream may be
489 * constrained to the wrong sample rate or size.
491 if (!first_runtime->sample_bits) {
492 dev_err(substream->pcm->card->dev,
493 "set sample size in %s stream first\n",
495 SNDRV_PCM_STREAM_PLAYBACK
496 ? "capture" : "playback");
500 snd_pcm_hw_constraint_minmax(substream->runtime,
501 SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
502 first_runtime->sample_bits,
503 first_runtime->sample_bits);
506 ssi_private->second_stream = substream;
513 * fsl_ssi_hw_params - program the sample size
515 * Most of the SSI registers have been programmed in the startup function,
516 * but the word length must be programmed here. Unfortunately, programming
517 * the SxCCR.WL bits requires the SSI to be temporarily disabled. This can
518 * cause a problem with supporting simultaneous playback and capture. If
519 * the SSI is already playing a stream, then that stream may be temporarily
520 * stopped when you start capture.
522 * Note: The SxCCR.DC and SxCCR.PM bits are only used if the SSI is the
525 static int fsl_ssi_hw_params(struct snd_pcm_substream *substream,
526 struct snd_pcm_hw_params *hw_params, struct snd_soc_dai *cpu_dai)
528 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(cpu_dai);
529 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
530 unsigned int sample_size =
531 snd_pcm_format_width(params_format(hw_params));
532 u32 wl = CCSR_SSI_SxCCR_WL(sample_size);
533 int enabled = read_ssi(&ssi->scr) & CCSR_SSI_SCR_SSIEN;
536 * If we're in synchronous mode, and the SSI is already enabled,
537 * then STCCR is already set properly.
539 if (enabled && ssi_private->cpu_dai_drv.symmetric_rates)
543 * FIXME: The documentation says that SxCCR[WL] should not be
544 * modified while the SSI is enabled. The only time this can
545 * happen is if we're trying to do simultaneous playback and
546 * capture in asynchronous mode. Unfortunately, I have been enable
547 * to get that to work at all on the P1022DS. Therefore, we don't
548 * bother to disable/enable the SSI when setting SxCCR[WL], because
549 * the SSI will stop anyway. Maybe one day, this will get fixed.
552 /* In synchronous mode, the SSI uses STCCR for capture */
553 if ((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ||
554 ssi_private->cpu_dai_drv.symmetric_rates)
555 write_ssi_mask(&ssi->stccr, CCSR_SSI_SxCCR_WL_MASK, wl);
557 write_ssi_mask(&ssi->srccr, CCSR_SSI_SxCCR_WL_MASK, wl);
563 * fsl_ssi_trigger: start and stop the DMA transfer.
565 * This function is called by ALSA to start, stop, pause, and resume the DMA
568 * The DMA channel is in external master start and pause mode, which
569 * means the SSI completely controls the flow of data.
571 static int fsl_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
572 struct snd_soc_dai *dai)
574 struct snd_soc_pcm_runtime *rtd = substream->private_data;
575 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
576 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
579 case SNDRV_PCM_TRIGGER_START:
580 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
581 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
582 write_ssi_mask(&ssi->scr, 0,
583 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_TE);
585 write_ssi_mask(&ssi->scr, 0,
586 CCSR_SSI_SCR_SSIEN | CCSR_SSI_SCR_RE);
589 case SNDRV_PCM_TRIGGER_STOP:
590 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
591 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
592 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_TE, 0);
594 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_RE, 0);
596 if (!ssi_private->imx_ac97 && (read_ssi(&ssi->scr) &
597 (CCSR_SSI_SCR_TE | CCSR_SSI_SCR_RE)) == 0)
598 write_ssi_mask(&ssi->scr, CCSR_SSI_SCR_SSIEN, 0);
609 * fsl_ssi_shutdown: shutdown the SSI
611 * Shutdown the SSI if there are no other substreams open.
613 static void fsl_ssi_shutdown(struct snd_pcm_substream *substream,
614 struct snd_soc_dai *dai)
616 struct snd_soc_pcm_runtime *rtd = substream->private_data;
617 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(rtd->cpu_dai);
619 if (ssi_private->first_stream == substream)
620 ssi_private->first_stream = ssi_private->second_stream;
622 ssi_private->second_stream = NULL;
625 static int fsl_ssi_dai_probe(struct snd_soc_dai *dai)
627 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(dai);
629 if (ssi_private->ssi_on_imx && ssi_private->use_dma) {
630 dai->playback_dma_data = &ssi_private->dma_params_tx;
631 dai->capture_dma_data = &ssi_private->dma_params_rx;
637 static const struct snd_soc_dai_ops fsl_ssi_dai_ops = {
638 .startup = fsl_ssi_startup,
639 .hw_params = fsl_ssi_hw_params,
640 .shutdown = fsl_ssi_shutdown,
641 .trigger = fsl_ssi_trigger,
644 /* Template for the CPU dai driver structure */
645 static struct snd_soc_dai_driver fsl_ssi_dai_template = {
646 .probe = fsl_ssi_dai_probe,
648 /* The SSI does not support monaural audio. */
651 .rates = FSLSSI_I2S_RATES,
652 .formats = FSLSSI_I2S_FORMATS,
657 .rates = FSLSSI_I2S_RATES,
658 .formats = FSLSSI_I2S_FORMATS,
660 .ops = &fsl_ssi_dai_ops,
663 static const struct snd_soc_component_driver fsl_ssi_component = {
668 * fsl_ssi_ac97_trigger: start and stop the AC97 receive/transmit.
670 * This function is called by ALSA to start, stop, pause, and resume the
673 static int fsl_ssi_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
674 struct snd_soc_dai *dai)
676 struct snd_soc_pcm_runtime *rtd = substream->private_data;
677 struct fsl_ssi_private *ssi_private = snd_soc_dai_get_drvdata(
679 struct ccsr_ssi __iomem *ssi = ssi_private->ssi;
682 case SNDRV_PCM_TRIGGER_START:
683 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
684 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
685 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_TIE |
686 CCSR_SSI_SIER_TFE0_EN);
688 write_ssi_mask(&ssi->sier, 0, CCSR_SSI_SIER_RIE |
689 CCSR_SSI_SIER_RFF0_EN);
692 case SNDRV_PCM_TRIGGER_STOP:
693 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
694 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
695 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_TIE |
696 CCSR_SSI_SIER_TFE0_EN, 0);
698 write_ssi_mask(&ssi->sier, CCSR_SSI_SIER_RIE |
699 CCSR_SSI_SIER_RFF0_EN, 0);
706 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
707 write_ssi(CCSR_SSI_SOR_TX_CLR, &ssi->sor);
709 write_ssi(CCSR_SSI_SOR_RX_CLR, &ssi->sor);
714 static const struct snd_soc_dai_ops fsl_ssi_ac97_dai_ops = {
715 .startup = fsl_ssi_startup,
716 .shutdown = fsl_ssi_shutdown,
717 .trigger = fsl_ssi_ac97_trigger,
720 static struct snd_soc_dai_driver fsl_ssi_ac97_dai = {
723 .stream_name = "AC97 Playback",
726 .rates = SNDRV_PCM_RATE_8000_48000,
727 .formats = SNDRV_PCM_FMTBIT_S16_LE,
730 .stream_name = "AC97 Capture",
733 .rates = SNDRV_PCM_RATE_48000,
734 .formats = SNDRV_PCM_FMTBIT_S16_LE,
736 .ops = &fsl_ssi_ac97_dai_ops,
740 static struct fsl_ssi_private *fsl_ac97_data;
742 static void fsl_ssi_ac97_init(void)
744 fsl_ssi_setup(fsl_ac97_data);
747 void fsl_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
750 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
759 write_ssi(lreg, &ssi->sacadd);
762 write_ssi(lval , &ssi->sacdat);
764 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
769 unsigned short fsl_ssi_ac97_read(struct snd_ac97 *ac97,
772 struct ccsr_ssi *ssi = fsl_ac97_data->ssi;
774 unsigned short val = -1;
777 lreg = (reg & 0x7f) << 12;
778 write_ssi(lreg, &ssi->sacadd);
779 write_ssi_mask(&ssi->sacnt, CCSR_SSI_SACNT_RDWR_MASK,
784 val = (read_ssi(&ssi->sacdat) >> 4) & 0xffff;
789 static struct snd_ac97_bus_ops fsl_ssi_ac97_ops = {
790 .read = fsl_ssi_ac97_read,
791 .write = fsl_ssi_ac97_write,
794 /* Show the statistics of a flag only if its interrupt is enabled. The
795 * compiler will optimze this code to a no-op if the interrupt is not
798 #define SIER_SHOW(flag, name) \
800 if (SIER_FLAGS & CCSR_SSI_SIER_##flag) \
801 length += sprintf(buf + length, #name "=%u\n", \
802 ssi_private->stats.name); \
807 * fsl_sysfs_ssi_show: display SSI statistics
809 * Display the statistics for the current SSI device. To avoid confusion,
810 * we only show those counts that are enabled.
812 static ssize_t fsl_sysfs_ssi_show(struct device *dev,
813 struct device_attribute *attr, char *buf)
815 struct fsl_ssi_private *ssi_private =
816 container_of(attr, struct fsl_ssi_private, dev_attr);
819 SIER_SHOW(RFRC_EN, rfrc);
820 SIER_SHOW(TFRC_EN, tfrc);
821 SIER_SHOW(CMDAU_EN, cmdau);
822 SIER_SHOW(CMDDU_EN, cmddu);
823 SIER_SHOW(RXT_EN, rxt);
824 SIER_SHOW(RDR1_EN, rdr1);
825 SIER_SHOW(RDR0_EN, rdr0);
826 SIER_SHOW(TDE1_EN, tde1);
827 SIER_SHOW(TDE0_EN, tde0);
828 SIER_SHOW(ROE1_EN, roe1);
829 SIER_SHOW(ROE0_EN, roe0);
830 SIER_SHOW(TUE1_EN, tue1);
831 SIER_SHOW(TUE0_EN, tue0);
832 SIER_SHOW(TFS_EN, tfs);
833 SIER_SHOW(RFS_EN, rfs);
834 SIER_SHOW(TLS_EN, tls);
835 SIER_SHOW(RLS_EN, rls);
836 SIER_SHOW(RFF1_EN, rff1);
837 SIER_SHOW(RFF0_EN, rff0);
838 SIER_SHOW(TFE1_EN, tfe1);
839 SIER_SHOW(TFE0_EN, tfe0);
845 * Make every character in a string lower-case
847 static void make_lowercase(char *s)
853 if ((c >= 'A') && (c <= 'Z'))
854 *p = c + ('a' - 'A');
859 static int fsl_ssi_probe(struct platform_device *pdev)
861 struct fsl_ssi_private *ssi_private;
863 struct device_attribute *dev_attr = NULL;
864 struct device_node *np = pdev->dev.of_node;
865 const char *p, *sprop;
866 const uint32_t *iprop;
872 /* SSIs that are not connected on the board should have a
873 * status = "disabled"
874 * property in their device tree nodes.
876 if (!of_device_is_available(np))
879 /* We only support the SSI in "I2S Slave" mode */
880 sprop = of_get_property(np, "fsl,mode", NULL);
882 dev_err(&pdev->dev, "fsl,mode property is necessary\n");
885 if (!strcmp(sprop, "ac97-slave")) {
887 } else if (strcmp(sprop, "i2s-slave")) {
888 dev_notice(&pdev->dev, "mode %s is unsupported\n", sprop);
892 /* The DAI name is the last part of the full name of the node. */
893 p = strrchr(np->full_name, '/') + 1;
894 ssi_private = devm_kzalloc(&pdev->dev, sizeof(*ssi_private) + strlen(p),
897 dev_err(&pdev->dev, "could not allocate DAI object\n");
901 strcpy(ssi_private->name, p);
903 ssi_private->use_dma = !of_property_read_bool(np,
904 "fsl,fiq-stream-filter");
907 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_ac97_dai,
908 sizeof(fsl_ssi_ac97_dai));
910 fsl_ac97_data = ssi_private;
911 ssi_private->imx_ac97 = true;
913 snd_soc_set_ac97_ops_of_reset(&fsl_ssi_ac97_ops, pdev);
915 /* Initialize this copy of the CPU DAI driver structure */
916 memcpy(&ssi_private->cpu_dai_drv, &fsl_ssi_dai_template,
917 sizeof(fsl_ssi_dai_template));
919 ssi_private->cpu_dai_drv.name = ssi_private->name;
921 /* Get the addresses and IRQ */
922 ret = of_address_to_resource(np, 0, &res);
924 dev_err(&pdev->dev, "could not determine device resources\n");
927 ssi_private->ssi = of_iomap(np, 0);
928 if (!ssi_private->ssi) {
929 dev_err(&pdev->dev, "could not map device resources\n");
932 ssi_private->ssi_phys = res.start;
934 ssi_private->irq = irq_of_parse_and_map(np, 0);
935 if (ssi_private->irq == NO_IRQ) {
936 dev_err(&pdev->dev, "no irq for node %s\n", np->full_name);
940 if (ssi_private->use_dma) {
941 /* The 'name' should not have any slashes in it. */
942 ret = devm_request_irq(&pdev->dev, ssi_private->irq,
943 fsl_ssi_isr, 0, ssi_private->name,
946 dev_err(&pdev->dev, "could not claim irq %u\n",
952 /* Are the RX and the TX clocks locked? */
953 if (!of_find_property(np, "fsl,ssi-asynchronous", NULL))
954 ssi_private->cpu_dai_drv.symmetric_rates = 1;
956 /* Determine the FIFO depth. */
957 iprop = of_get_property(np, "fsl,fifo-depth", NULL);
959 ssi_private->fifo_depth = be32_to_cpup(iprop);
961 /* Older 8610 DTs didn't have the fifo-depth property */
962 ssi_private->fifo_depth = 8;
964 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx21-ssi")) {
966 ssi_private->ssi_on_imx = true;
968 ssi_private->clk = devm_clk_get(&pdev->dev, NULL);
969 if (IS_ERR(ssi_private->clk)) {
970 ret = PTR_ERR(ssi_private->clk);
971 dev_err(&pdev->dev, "could not get clock: %d\n", ret);
974 ret = clk_prepare_enable(ssi_private->clk);
976 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n",
982 * We have burstsize be "fifo_depth - 2" to match the SSI
983 * watermark setting in fsl_ssi_startup().
985 ssi_private->dma_params_tx.maxburst =
986 ssi_private->fifo_depth - 2;
987 ssi_private->dma_params_rx.maxburst =
988 ssi_private->fifo_depth - 2;
989 ssi_private->dma_params_tx.addr =
990 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, stx0);
991 ssi_private->dma_params_rx.addr =
992 ssi_private->ssi_phys + offsetof(struct ccsr_ssi, srx0);
993 ssi_private->dma_params_tx.filter_data =
994 &ssi_private->filter_data_tx;
995 ssi_private->dma_params_rx.filter_data =
996 &ssi_private->filter_data_rx;
997 if (!of_property_read_bool(pdev->dev.of_node, "dmas") &&
998 ssi_private->use_dma) {
1000 * FIXME: This is a temporary solution until all
1001 * necessary dma drivers support the generic dma
1004 ret = of_property_read_u32_array(pdev->dev.of_node,
1005 "fsl,ssi-dma-events", dma_events, 2);
1006 if (ret && ssi_private->use_dma) {
1007 dev_err(&pdev->dev, "could not get dma events but fsl-ssi is configured to use DMA\n");
1012 shared = of_device_is_compatible(of_get_parent(np),
1015 imx_pcm_dma_params_init_data(&ssi_private->filter_data_tx,
1016 dma_events[0], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1017 imx_pcm_dma_params_init_data(&ssi_private->filter_data_rx,
1018 dma_events[1], shared ? IMX_DMATYPE_SSI_SP : IMX_DMATYPE_SSI);
1021 /* Initialize the the device_attribute structure */
1022 dev_attr = &ssi_private->dev_attr;
1023 sysfs_attr_init(&dev_attr->attr);
1024 dev_attr->attr.name = "statistics";
1025 dev_attr->attr.mode = S_IRUGO;
1026 dev_attr->show = fsl_sysfs_ssi_show;
1028 ret = device_create_file(&pdev->dev, dev_attr);
1030 dev_err(&pdev->dev, "could not create sysfs %s file\n",
1031 ssi_private->dev_attr.attr.name);
1035 /* Register with ASoC */
1036 dev_set_drvdata(&pdev->dev, ssi_private);
1038 ret = snd_soc_register_component(&pdev->dev, &fsl_ssi_component,
1039 &ssi_private->cpu_dai_drv, 1);
1041 dev_err(&pdev->dev, "failed to register DAI: %d\n", ret);
1045 if (ssi_private->ssi_on_imx) {
1046 if (!ssi_private->use_dma) {
1049 * Some boards use an incompatible codec. To get it
1050 * working, we are using imx-fiq-pcm-audio, that
1051 * can handle those codecs. DMA is not possible in this
1055 ssi_private->fiq_params.irq = ssi_private->irq;
1056 ssi_private->fiq_params.base = ssi_private->ssi;
1057 ssi_private->fiq_params.dma_params_rx =
1058 &ssi_private->dma_params_rx;
1059 ssi_private->fiq_params.dma_params_tx =
1060 &ssi_private->dma_params_tx;
1062 ret = imx_pcm_fiq_init(pdev, &ssi_private->fiq_params);
1066 ret = imx_pcm_dma_init(pdev);
1073 * If codec-handle property is missing from SSI node, we assume
1074 * that the machine driver uses new binding which does not require
1075 * SSI driver to trigger machine driver's probe.
1077 if (!of_get_property(np, "codec-handle", NULL)) {
1078 ssi_private->new_binding = true;
1082 /* Trigger the machine driver's probe function. The platform driver
1083 * name of the machine driver is taken from /compatible property of the
1084 * device tree. We also pass the address of the CPU DAI driver
1087 sprop = of_get_property(of_find_node_by_path("/"), "compatible", NULL);
1088 /* Sometimes the compatible name has a "fsl," prefix, so we strip it. */
1089 p = strrchr(sprop, ',');
1092 snprintf(name, sizeof(name), "snd-soc-%s", sprop);
1093 make_lowercase(name);
1096 platform_device_register_data(&pdev->dev, name, 0, NULL, 0);
1097 if (IS_ERR(ssi_private->pdev)) {
1098 ret = PTR_ERR(ssi_private->pdev);
1099 dev_err(&pdev->dev, "failed to register platform: %d\n", ret);
1104 if (ssi_private->imx_ac97)
1105 fsl_ssi_ac97_init();
1110 if (ssi_private->ssi_on_imx)
1111 imx_pcm_dma_exit(pdev);
1112 snd_soc_unregister_component(&pdev->dev);
1115 dev_set_drvdata(&pdev->dev, NULL);
1116 device_remove_file(&pdev->dev, dev_attr);
1119 if (ssi_private->ssi_on_imx)
1120 clk_disable_unprepare(ssi_private->clk);
1123 irq_dispose_mapping(ssi_private->irq);
1128 static int fsl_ssi_remove(struct platform_device *pdev)
1130 struct fsl_ssi_private *ssi_private = dev_get_drvdata(&pdev->dev);
1132 if (!ssi_private->new_binding)
1133 platform_device_unregister(ssi_private->pdev);
1134 if (ssi_private->ssi_on_imx)
1135 imx_pcm_dma_exit(pdev);
1136 snd_soc_unregister_component(&pdev->dev);
1137 dev_set_drvdata(&pdev->dev, NULL);
1138 device_remove_file(&pdev->dev, &ssi_private->dev_attr);
1139 if (ssi_private->ssi_on_imx)
1140 clk_disable_unprepare(ssi_private->clk);
1141 irq_dispose_mapping(ssi_private->irq);
1146 static const struct of_device_id fsl_ssi_ids[] = {
1147 { .compatible = "fsl,mpc8610-ssi", },
1148 { .compatible = "fsl,imx21-ssi", },
1151 MODULE_DEVICE_TABLE(of, fsl_ssi_ids);
1153 static struct platform_driver fsl_ssi_driver = {
1155 .name = "fsl-ssi-dai",
1156 .owner = THIS_MODULE,
1157 .of_match_table = fsl_ssi_ids,
1159 .probe = fsl_ssi_probe,
1160 .remove = fsl_ssi_remove,
1163 module_platform_driver(fsl_ssi_driver);
1165 MODULE_ALIAS("platform:fsl-ssi-dai");
1166 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
1167 MODULE_DESCRIPTION("Freescale Synchronous Serial Interface (SSI) ASoC Driver");
1168 MODULE_LICENSE("GPL v2");