1 // SPDX-License-Identifier: GPL-2.0+
3 // Freescale ALSA SoC Digital Audio Interface (SAI) driver.
5 // Copyright 2012-2015 Freescale Semiconductor, Inc.
8 #include <linux/delay.h>
9 #include <linux/dmaengine.h>
10 #include <linux/module.h>
11 #include <linux/of_address.h>
12 #include <linux/of_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/regmap.h>
15 #include <linux/slab.h>
16 #include <linux/time.h>
17 #include <sound/core.h>
18 #include <sound/dmaengine_pcm.h>
19 #include <sound/pcm_params.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
26 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
29 static const unsigned int fsl_sai_rates[] = {
30 8000, 11025, 12000, 16000, 22050,
31 24000, 32000, 44100, 48000, 64000,
32 88200, 96000, 176400, 192000
35 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
36 .count = ARRAY_SIZE(fsl_sai_rates),
37 .list = fsl_sai_rates,
40 static irqreturn_t fsl_sai_isr(int irq, void *devid)
42 struct fsl_sai *sai = (struct fsl_sai *)devid;
43 unsigned int ofs = sai->soc_data->reg_offset;
44 struct device *dev = &sai->pdev->dev;
45 u32 flags, xcsr, mask;
49 * Both IRQ status bits and IRQ mask bits are in the xCSR but
50 * different shifts. And we here create a mask only for those
51 * IRQs that we activated.
53 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
56 regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
64 if (flags & FSL_SAI_CSR_WSF)
65 dev_dbg(dev, "isr: Start of Tx word detected\n");
67 if (flags & FSL_SAI_CSR_SEF)
68 dev_dbg(dev, "isr: Tx Frame sync error detected\n");
70 if (flags & FSL_SAI_CSR_FEF) {
71 dev_dbg(dev, "isr: Transmit underrun detected\n");
72 /* FIFO reset for safety */
73 xcsr |= FSL_SAI_CSR_FR;
76 if (flags & FSL_SAI_CSR_FWF)
77 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
79 if (flags & FSL_SAI_CSR_FRF)
80 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
82 flags &= FSL_SAI_CSR_xF_W_MASK;
83 xcsr &= ~FSL_SAI_CSR_xF_MASK;
86 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
90 regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
98 if (flags & FSL_SAI_CSR_WSF)
99 dev_dbg(dev, "isr: Start of Rx word detected\n");
101 if (flags & FSL_SAI_CSR_SEF)
102 dev_dbg(dev, "isr: Rx Frame sync error detected\n");
104 if (flags & FSL_SAI_CSR_FEF) {
105 dev_dbg(dev, "isr: Receive overflow detected\n");
106 /* FIFO reset for safety */
107 xcsr |= FSL_SAI_CSR_FR;
110 if (flags & FSL_SAI_CSR_FWF)
111 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
113 if (flags & FSL_SAI_CSR_FRF)
114 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
116 flags &= FSL_SAI_CSR_xF_W_MASK;
117 xcsr &= ~FSL_SAI_CSR_xF_MASK;
120 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
129 static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
130 u32 rx_mask, int slots, int slot_width)
132 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
135 sai->slot_width = slot_width;
140 static int fsl_sai_set_dai_bclk_ratio(struct snd_soc_dai *dai,
143 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
145 sai->bclk_ratio = ratio;
150 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
151 int clk_id, unsigned int freq, int fsl_dir)
153 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
154 unsigned int ofs = sai->soc_data->reg_offset;
155 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
159 case FSL_SAI_CLK_BUS:
160 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
162 case FSL_SAI_CLK_MAST1:
163 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
165 case FSL_SAI_CLK_MAST2:
166 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
168 case FSL_SAI_CLK_MAST3:
169 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
175 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
176 FSL_SAI_CR2_MSEL_MASK, val_cr2);
181 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
182 int clk_id, unsigned int freq, int dir)
186 if (dir == SND_SOC_CLOCK_IN)
189 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
190 FSL_FMT_TRANSMITTER);
192 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
196 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
199 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
204 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
205 unsigned int fmt, int fsl_dir)
207 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
208 unsigned int ofs = sai->soc_data->reg_offset;
209 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
210 u32 val_cr2 = 0, val_cr4 = 0;
212 if (!sai->is_lsb_first)
213 val_cr4 |= FSL_SAI_CR4_MF;
216 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
217 case SND_SOC_DAIFMT_I2S:
219 * Frame low, 1clk before data, one word length for frame sync,
220 * frame sync starts one serial clock cycle earlier,
221 * that is, together with the last bit of the previous
224 val_cr2 |= FSL_SAI_CR2_BCP;
225 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
227 case SND_SOC_DAIFMT_LEFT_J:
229 * Frame high, one word length for frame sync,
230 * frame sync asserts with the first bit of the frame.
232 val_cr2 |= FSL_SAI_CR2_BCP;
234 case SND_SOC_DAIFMT_DSP_A:
236 * Frame high, 1clk before data, one bit for frame sync,
237 * frame sync starts one serial clock cycle earlier,
238 * that is, together with the last bit of the previous
241 val_cr2 |= FSL_SAI_CR2_BCP;
242 val_cr4 |= FSL_SAI_CR4_FSE;
243 sai->is_dsp_mode = true;
245 case SND_SOC_DAIFMT_DSP_B:
247 * Frame high, one bit for frame sync,
248 * frame sync asserts with the first bit of the frame.
250 val_cr2 |= FSL_SAI_CR2_BCP;
251 sai->is_dsp_mode = true;
253 case SND_SOC_DAIFMT_RIGHT_J:
259 /* DAI clock inversion */
260 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
261 case SND_SOC_DAIFMT_IB_IF:
262 /* Invert both clocks */
263 val_cr2 ^= FSL_SAI_CR2_BCP;
264 val_cr4 ^= FSL_SAI_CR4_FSP;
266 case SND_SOC_DAIFMT_IB_NF:
267 /* Invert bit clock */
268 val_cr2 ^= FSL_SAI_CR2_BCP;
270 case SND_SOC_DAIFMT_NB_IF:
271 /* Invert frame clock */
272 val_cr4 ^= FSL_SAI_CR4_FSP;
274 case SND_SOC_DAIFMT_NB_NF:
275 /* Nothing to do for both normal cases */
281 /* DAI clock master masks */
282 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
283 case SND_SOC_DAIFMT_CBS_CFS:
284 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
285 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
286 sai->is_slave_mode = false;
288 case SND_SOC_DAIFMT_CBM_CFM:
289 sai->is_slave_mode = true;
291 case SND_SOC_DAIFMT_CBS_CFM:
292 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
293 sai->is_slave_mode = false;
295 case SND_SOC_DAIFMT_CBM_CFS:
296 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
297 sai->is_slave_mode = true;
303 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
304 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
305 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
306 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
307 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
312 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
316 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
318 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
322 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
324 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
329 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
331 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
332 unsigned int ofs = sai->soc_data->reg_offset;
333 unsigned long clk_rate;
334 u32 savediv = 0, ratio, savesub = freq;
338 /* Don't apply to slave mode */
339 if (sai->is_slave_mode)
342 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
343 clk_rate = clk_get_rate(sai->mclk_clk[id]);
347 ratio = clk_rate / freq;
349 ret = clk_rate - ratio * freq;
352 * Drop the source that can not be
353 * divided into the required rate.
355 if (ret != 0 && clk_rate / ret < 1000)
359 "ratio %d for freq %dHz based on clock %ldHz\n",
360 ratio, freq, clk_rate);
362 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
369 sai->mclk_id[tx] = id;
378 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
379 tx ? 'T' : 'R', freq);
384 * 1) For Asynchronous mode, we must set RCR2 register for capture, and
385 * set TCR2 register for playback.
386 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback
388 * 3) For Rx sync with Tx clock, we must set TCR2 register for playback
390 * 4) For Tx and Rx are both Synchronous with another SAI, we just
393 if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
394 (!tx && !sai->synchronous[RX])) {
395 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
396 FSL_SAI_CR2_MSEL_MASK,
397 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
398 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
399 FSL_SAI_CR2_DIV_MASK, savediv - 1);
400 } else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
401 (tx && !sai->synchronous[TX])) {
402 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
403 FSL_SAI_CR2_MSEL_MASK,
404 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
405 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
406 FSL_SAI_CR2_DIV_MASK, savediv - 1);
409 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
410 sai->mclk_id[tx], savediv, savesub);
415 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
416 struct snd_pcm_hw_params *params,
417 struct snd_soc_dai *cpu_dai)
419 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
420 unsigned int ofs = sai->soc_data->reg_offset;
421 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
422 unsigned int channels = params_channels(params);
423 u32 word_width = params_width(params);
424 u32 val_cr4 = 0, val_cr5 = 0;
425 u32 slots = (channels == 1) ? 2 : channels;
426 u32 slot_width = word_width;
433 slot_width = sai->slot_width;
435 if (!sai->is_slave_mode) {
437 ret = fsl_sai_set_bclk(cpu_dai, tx,
439 params_rate(params));
441 ret = fsl_sai_set_bclk(cpu_dai, tx,
443 params_rate(params));
447 /* Do not enable the clock if it is already enabled */
448 if (!(sai->mclk_streams & BIT(substream->stream))) {
449 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
453 sai->mclk_streams |= BIT(substream->stream);
457 if (!sai->is_dsp_mode)
458 val_cr4 |= FSL_SAI_CR4_SYWD(slot_width);
460 val_cr5 |= FSL_SAI_CR5_WNW(slot_width);
461 val_cr5 |= FSL_SAI_CR5_W0W(slot_width);
463 if (sai->is_lsb_first)
464 val_cr5 |= FSL_SAI_CR5_FBT(0);
466 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
468 val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
471 * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
472 * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
473 * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
477 if (!sai->is_slave_mode) {
478 if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
479 regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
480 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
482 regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
483 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
484 FSL_SAI_CR5_FBT_MASK, val_cr5);
485 regmap_write(sai->regmap, FSL_SAI_TMR,
486 ~0UL - ((1 << channels) - 1));
487 } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
488 regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
489 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
491 regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
492 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
493 FSL_SAI_CR5_FBT_MASK, val_cr5);
494 regmap_write(sai->regmap, FSL_SAI_RMR,
495 ~0UL - ((1 << channels) - 1));
499 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
500 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
502 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
503 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
504 FSL_SAI_CR5_FBT_MASK, val_cr5);
505 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
510 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
511 struct snd_soc_dai *cpu_dai)
513 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
514 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
516 if (!sai->is_slave_mode &&
517 sai->mclk_streams & BIT(substream->stream)) {
518 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
519 sai->mclk_streams &= ~BIT(substream->stream);
526 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
527 struct snd_soc_dai *cpu_dai)
529 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
530 unsigned int ofs = sai->soc_data->reg_offset;
532 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
533 u32 xcsr, count = 100;
536 * Asynchronous mode: Clear SYNC for both Tx and Rx.
537 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
538 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
540 regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
541 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
542 regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
543 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
546 * It is recommended that the transmitter is the last enabled
547 * and the first disabled.
550 case SNDRV_PCM_TRIGGER_START:
551 case SNDRV_PCM_TRIGGER_RESUME:
552 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
553 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
554 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
556 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
557 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
558 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
559 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
561 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
562 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
564 case SNDRV_PCM_TRIGGER_STOP:
565 case SNDRV_PCM_TRIGGER_SUSPEND:
566 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
567 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
568 FSL_SAI_CSR_FRDE, 0);
569 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
570 FSL_SAI_CSR_xIE_MASK, 0);
572 /* Check if the opposite FRDE is also disabled */
573 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
574 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
575 /* Disable both directions and reset their FIFOs */
576 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
577 FSL_SAI_CSR_TERE, 0);
578 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
579 FSL_SAI_CSR_TERE, 0);
581 /* TERE will remain set till the end of current frame */
584 regmap_read(sai->regmap,
585 FSL_SAI_xCSR(tx, ofs), &xcsr);
586 } while (--count && xcsr & FSL_SAI_CSR_TERE);
588 regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
589 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
590 regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
591 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
594 * For sai master mode, after several open/close sai,
595 * there will be no frame clock, and can't recover
596 * anymore. Add software reset to fix this issue.
597 * This is a hardware bug, and will be fix in the
600 if (!sai->is_slave_mode) {
601 /* Software Reset for both Tx and Rx */
602 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
604 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
606 /* Clear SR bit to finish the reset */
607 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
608 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
619 static int fsl_sai_startup(struct snd_pcm_substream *substream,
620 struct snd_soc_dai *cpu_dai)
622 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
623 unsigned int ofs = sai->soc_data->reg_offset;
624 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
627 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
628 FSL_SAI_CR3_TRCE_MASK,
631 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
632 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
637 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
638 struct snd_soc_dai *cpu_dai)
640 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
641 unsigned int ofs = sai->soc_data->reg_offset;
642 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
644 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
645 FSL_SAI_CR3_TRCE_MASK, 0);
648 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
649 .set_bclk_ratio = fsl_sai_set_dai_bclk_ratio,
650 .set_sysclk = fsl_sai_set_dai_sysclk,
651 .set_fmt = fsl_sai_set_dai_fmt,
652 .set_tdm_slot = fsl_sai_set_dai_tdm_slot,
653 .hw_params = fsl_sai_hw_params,
654 .hw_free = fsl_sai_hw_free,
655 .trigger = fsl_sai_trigger,
656 .startup = fsl_sai_startup,
657 .shutdown = fsl_sai_shutdown,
660 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
662 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
663 unsigned int ofs = sai->soc_data->reg_offset;
665 /* Software Reset for both Tx and Rx */
666 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
667 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
668 /* Clear SR bit to finish the reset */
669 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
670 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
672 regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
673 FSL_SAI_CR1_RFW_MASK,
674 sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
675 regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
676 FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
678 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
679 &sai->dma_params_rx);
681 snd_soc_dai_set_drvdata(cpu_dai, sai);
686 static struct snd_soc_dai_driver fsl_sai_dai = {
687 .probe = fsl_sai_dai_probe,
689 .stream_name = "CPU-Playback",
694 .rates = SNDRV_PCM_RATE_KNOT,
695 .formats = FSL_SAI_FORMATS,
698 .stream_name = "CPU-Capture",
703 .rates = SNDRV_PCM_RATE_KNOT,
704 .formats = FSL_SAI_FORMATS,
706 .ops = &fsl_sai_pcm_dai_ops,
709 static const struct snd_soc_component_driver fsl_component = {
713 static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
714 {FSL_SAI_TCR1(0), 0},
715 {FSL_SAI_TCR2(0), 0},
716 {FSL_SAI_TCR3(0), 0},
717 {FSL_SAI_TCR4(0), 0},
718 {FSL_SAI_TCR5(0), 0},
728 {FSL_SAI_RCR1(0), 0},
729 {FSL_SAI_RCR2(0), 0},
730 {FSL_SAI_RCR3(0), 0},
731 {FSL_SAI_RCR4(0), 0},
732 {FSL_SAI_RCR5(0), 0},
736 static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
737 {FSL_SAI_TCR1(8), 0},
738 {FSL_SAI_TCR2(8), 0},
739 {FSL_SAI_TCR3(8), 0},
740 {FSL_SAI_TCR4(8), 0},
741 {FSL_SAI_TCR5(8), 0},
751 {FSL_SAI_RCR1(8), 0},
752 {FSL_SAI_RCR2(8), 0},
753 {FSL_SAI_RCR3(8), 0},
754 {FSL_SAI_RCR4(8), 0},
755 {FSL_SAI_RCR5(8), 0},
759 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
761 struct fsl_sai *sai = dev_get_drvdata(dev);
762 unsigned int ofs = sai->soc_data->reg_offset;
764 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
767 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
803 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
805 struct fsl_sai *sai = dev_get_drvdata(dev);
806 unsigned int ofs = sai->soc_data->reg_offset;
808 if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
842 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
844 struct fsl_sai *sai = dev_get_drvdata(dev);
845 unsigned int ofs = sai->soc_data->reg_offset;
847 if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
850 if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
870 static struct regmap_config fsl_sai_regmap_config = {
876 .max_register = FSL_SAI_RMR,
877 .reg_defaults = fsl_sai_reg_defaults_ofs0,
878 .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
879 .readable_reg = fsl_sai_readable_reg,
880 .volatile_reg = fsl_sai_volatile_reg,
881 .writeable_reg = fsl_sai_writeable_reg,
882 .cache_type = REGCACHE_FLAT,
885 static int fsl_sai_probe(struct platform_device *pdev)
887 struct device_node *np = pdev->dev.of_node;
890 struct resource *res;
896 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
901 sai->soc_data = of_device_get_match_data(&pdev->dev);
903 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
905 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
906 base = devm_ioremap_resource(&pdev->dev, res);
908 return PTR_ERR(base);
910 if (sai->soc_data->reg_offset == 8) {
911 fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
912 fsl_sai_regmap_config.num_reg_defaults =
913 ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
916 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
917 "bus", base, &fsl_sai_regmap_config);
919 /* Compatible with old DTB cases */
920 if (IS_ERR(sai->regmap))
921 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
922 "sai", base, &fsl_sai_regmap_config);
923 if (IS_ERR(sai->regmap)) {
924 dev_err(&pdev->dev, "regmap init failed\n");
925 return PTR_ERR(sai->regmap);
928 /* No error out for old DTB cases but only mark the clock NULL */
929 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
930 if (IS_ERR(sai->bus_clk)) {
931 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
932 PTR_ERR(sai->bus_clk));
936 sai->mclk_clk[0] = sai->bus_clk;
937 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
938 sprintf(tmp, "mclk%d", i);
939 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
940 if (IS_ERR(sai->mclk_clk[i])) {
941 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
942 i + 1, PTR_ERR(sai->mclk_clk[i]));
943 sai->mclk_clk[i] = NULL;
947 irq = platform_get_irq(pdev, 0);
951 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
953 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
957 /* Sync Tx with Rx as default by following old DT binding */
958 sai->synchronous[RX] = true;
959 sai->synchronous[TX] = false;
960 fsl_sai_dai.symmetric_rates = 1;
961 fsl_sai_dai.symmetric_channels = 1;
962 fsl_sai_dai.symmetric_samplebits = 1;
964 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
965 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
966 /* error out if both synchronous and asynchronous are present */
967 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
971 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
972 /* Sync Rx with Tx */
973 sai->synchronous[RX] = false;
974 sai->synchronous[TX] = true;
975 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
976 /* Discard all settings for asynchronous mode */
977 sai->synchronous[RX] = false;
978 sai->synchronous[TX] = false;
979 fsl_sai_dai.symmetric_rates = 0;
980 fsl_sai_dai.symmetric_channels = 0;
981 fsl_sai_dai.symmetric_samplebits = 0;
984 if (of_find_property(np, "fsl,sai-mclk-direction-output", NULL) &&
985 of_device_is_compatible(np, "fsl,imx6ul-sai")) {
986 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6ul-iomuxc-gpr");
988 dev_err(&pdev->dev, "cannot find iomuxc registers\n");
992 index = of_alias_get_id(np, "sai");
996 regmap_update_bits(gpr, IOMUXC_GPR1, MCLK_DIR(index),
1000 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
1001 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
1002 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
1003 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
1005 platform_set_drvdata(pdev, sai);
1007 pm_runtime_enable(&pdev->dev);
1009 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
1014 if (sai->soc_data->use_imx_pcm)
1015 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
1017 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1020 static int fsl_sai_remove(struct platform_device *pdev)
1022 pm_runtime_disable(&pdev->dev);
1027 static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
1028 .use_imx_pcm = false,
1033 static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
1034 .use_imx_pcm = true,
1039 static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
1040 .use_imx_pcm = true,
1045 static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
1046 .use_imx_pcm = true,
1051 static const struct fsl_sai_soc_data fsl_sai_imx8qm_data = {
1052 .use_imx_pcm = true,
1057 static const struct of_device_id fsl_sai_ids[] = {
1058 { .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
1059 { .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
1060 { .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
1061 { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
1062 { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
1063 { .compatible = "fsl,imx8qm-sai", .data = &fsl_sai_imx8qm_data },
1066 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
1069 static int fsl_sai_runtime_suspend(struct device *dev)
1071 struct fsl_sai *sai = dev_get_drvdata(dev);
1073 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1074 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1076 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1077 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1079 clk_disable_unprepare(sai->bus_clk);
1081 regcache_cache_only(sai->regmap, true);
1082 regcache_mark_dirty(sai->regmap);
1087 static int fsl_sai_runtime_resume(struct device *dev)
1089 struct fsl_sai *sai = dev_get_drvdata(dev);
1090 unsigned int ofs = sai->soc_data->reg_offset;
1093 ret = clk_prepare_enable(sai->bus_clk);
1095 dev_err(dev, "failed to enable bus clock: %d\n", ret);
1099 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK)) {
1100 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[1]]);
1102 goto disable_bus_clk;
1105 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE)) {
1106 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[0]]);
1108 goto disable_tx_clk;
1111 regcache_cache_only(sai->regmap, false);
1112 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
1113 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
1114 usleep_range(1000, 2000);
1115 regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
1116 regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
1118 ret = regcache_sync(sai->regmap);
1120 goto disable_rx_clk;
1125 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_CAPTURE))
1126 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[0]]);
1128 if (sai->mclk_streams & BIT(SNDRV_PCM_STREAM_PLAYBACK))
1129 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[1]]);
1131 clk_disable_unprepare(sai->bus_clk);
1135 #endif /* CONFIG_PM */
1137 static const struct dev_pm_ops fsl_sai_pm_ops = {
1138 SET_RUNTIME_PM_OPS(fsl_sai_runtime_suspend,
1139 fsl_sai_runtime_resume, NULL)
1140 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1141 pm_runtime_force_resume)
1144 static struct platform_driver fsl_sai_driver = {
1145 .probe = fsl_sai_probe,
1146 .remove = fsl_sai_remove,
1149 .pm = &fsl_sai_pm_ops,
1150 .of_match_table = fsl_sai_ids,
1153 module_platform_driver(fsl_sai_driver);
1155 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
1156 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
1157 MODULE_ALIAS("platform:fsl-sai");
1158 MODULE_LICENSE("GPL");