sound/soc/dwc/designware_i2s.c

   1 /*
   2  * ALSA SoC Synopsys I2S Audio Layer
   3  *
   4  * sound/soc/dwc/designware_i2s.c
   5  *
   6  * Copyright (C) 2010 ST Microelectronics
   7  * Rajeev Kumar <rajeevkumar.linux@gmail.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <sound/designware_i2s.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/dmaengine_pcm.h>
  26
  27 /* common register for all channel */
  28 #define IER             0x000
  29 #define IRER            0x004
  30 #define ITER            0x008
  31 #define CER             0x00C
  32 #define CCR             0x010
  33 #define RXFFR           0x014
  34 #define TXFFR           0x018
  35
  36 /* I2STxRxRegisters for all channels */
  37 #define LRBR_LTHR(x)    (0x40 * x + 0x020)
  38 #define RRBR_RTHR(x)    (0x40 * x + 0x024)
  39 #define RER(x)          (0x40 * x + 0x028)
  40 #define TER(x)          (0x40 * x + 0x02C)
  41 #define RCR(x)          (0x40 * x + 0x030)
  42 #define TCR(x)          (0x40 * x + 0x034)
  43 #define ISR(x)          (0x40 * x + 0x038)
  44 #define IMR(x)          (0x40 * x + 0x03C)
  45 #define ROR(x)          (0x40 * x + 0x040)
  46 #define TOR(x)          (0x40 * x + 0x044)
  47 #define RFCR(x)         (0x40 * x + 0x048)
  48 #define TFCR(x)         (0x40 * x + 0x04C)
  49 #define RFF(x)          (0x40 * x + 0x050)
  50 #define TFF(x)          (0x40 * x + 0x054)
  51
  52 /* I2SCOMPRegisters */
  53 #define I2S_COMP_PARAM_2        0x01F0
  54 #define I2S_COMP_PARAM_1        0x01F4
  55 #define I2S_COMP_VERSION        0x01F8
  56 #define I2S_COMP_TYPE           0x01FC
  57
  58 /*
  59  * Component parameter register fields - define the I2S block's
  60  * configuration.
  61  */
  62 #define COMP1_TX_WORDSIZE_3(r)  (((r) & GENMASK(27, 25)) >> 25)
  63 #define COMP1_TX_WORDSIZE_2(r)  (((r) & GENMASK(24, 22)) >> 22)
  64 #define COMP1_TX_WORDSIZE_1(r)  (((r) & GENMASK(21, 19)) >> 19)
  65 #define COMP1_TX_WORDSIZE_0(r)  (((r) & GENMASK(18, 16)) >> 16)
  66 #define COMP1_TX_CHANNELS(r)    (((r) & GENMASK(10, 9)) >> 9)
  67 #define COMP1_RX_CHANNELS(r)    (((r) & GENMASK(8, 7)) >> 7)
  68 #define COMP1_RX_ENABLED(r)     (((r) & BIT(6)) >> 6)
  69 #define COMP1_TX_ENABLED(r)     (((r) & BIT(5)) >> 5)
  70 #define COMP1_MODE_EN(r)        (((r) & BIT(4)) >> 4)
  71 #define COMP1_FIFO_DEPTH_GLOBAL(r)      (((r) & GENMASK(3, 2)) >> 2)
  72 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
  73
  74 #define COMP2_RX_WORDSIZE_3(r)  (((r) & GENMASK(12, 10)) >> 10)
  75 #define COMP2_RX_WORDSIZE_2(r)  (((r) & GENMASK(9, 7)) >> 7)
  76 #define COMP2_RX_WORDSIZE_1(r)  (((r) & GENMASK(5, 3)) >> 3)
  77 #define COMP2_RX_WORDSIZE_0(r)  (((r) & GENMASK(2, 0)) >> 0)
  78
  79 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
  80 #define COMP_MAX_WORDSIZE       (1 << 3)
  81 #define COMP_MAX_DATA_WIDTH     (1 << 2)
  82
  83 #define MAX_CHANNEL_NUM         8
  84 #define MIN_CHANNEL_NUM         2
  85
  86 union dw_i2s_snd_dma_data {
  87         struct i2s_dma_data pd;
  88         struct snd_dmaengine_dai_dma_data dt;
  89 };
  90
  91 struct dw_i2s_dev {
  92         void __iomem *i2s_base;
  93         struct clk *clk;
  94         int active;
  95         unsigned int capability;
  96         struct device *dev;
  97
  98         /* data related to DMA transfers b/w i2s and DMAC */
  99         union dw_i2s_snd_dma_data play_dma_data;
 100         union dw_i2s_snd_dma_data capture_dma_data;
 101         struct i2s_clk_config_data config;
 102         int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
 103 };
 104
 105 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
 106 {
 107         writel(val, io_base + reg);
 108 }
 109
 110 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
 111 {
 112         return readl(io_base + reg);
 113 }
 114
 115 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
 116 {
 117         u32 i = 0;
 118
 119         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 120                 for (i = 0; i < 4; i++)
 121                         i2s_write_reg(dev->i2s_base, TER(i), 0);
 122         } else {
 123                 for (i = 0; i < 4; i++)
 124                         i2s_write_reg(dev->i2s_base, RER(i), 0);
 125         }
 126 }
 127
 128 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
 129 {
 130         u32 i = 0;
 131
 132         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 133                 for (i = 0; i < 4; i++)
 134                         i2s_write_reg(dev->i2s_base, TOR(i), 0);
 135         } else {
 136                 for (i = 0; i < 4; i++)
 137                         i2s_write_reg(dev->i2s_base, ROR(i), 0);
 138         }
 139 }
 140
 141 static void i2s_start(struct dw_i2s_dev *dev,
 142                       struct snd_pcm_substream *substream)
 143 {
 144
 145         i2s_write_reg(dev->i2s_base, IER, 1);
 146
 147         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 148                 i2s_write_reg(dev->i2s_base, ITER, 1);
 149         else
 150                 i2s_write_reg(dev->i2s_base, IRER, 1);
 151
 152         i2s_write_reg(dev->i2s_base, CER, 1);
 153 }
 154
 155 static void i2s_stop(struct dw_i2s_dev *dev,
 156                 struct snd_pcm_substream *substream)
 157 {
 158         u32 i = 0, irq;
 159
 160         i2s_clear_irqs(dev, substream->stream);
 161         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 162                 i2s_write_reg(dev->i2s_base, ITER, 0);
 163
 164                 for (i = 0; i < 4; i++) {
 165                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 166                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
 167                 }
 168         } else {
 169                 i2s_write_reg(dev->i2s_base, IRER, 0);
 170
 171                 for (i = 0; i < 4; i++) {
 172                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 173                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
 174                 }
 175         }
 176
 177         if (!dev->active) {
 178                 i2s_write_reg(dev->i2s_base, CER, 0);
 179                 i2s_write_reg(dev->i2s_base, IER, 0);
 180         }
 181 }
 182
 183 static int dw_i2s_startup(struct snd_pcm_substream *substream,
 184                 struct snd_soc_dai *cpu_dai)
 185 {
 186         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 187         union dw_i2s_snd_dma_data *dma_data = NULL;
 188
 189         if (!(dev->capability & DWC_I2S_RECORD) &&
 190                         (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
 191                 return -EINVAL;
 192
 193         if (!(dev->capability & DWC_I2S_PLAY) &&
 194                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
 195                 return -EINVAL;
 196
 197         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 198                 dma_data = &dev->play_dma_data;
 199         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 200                 dma_data = &dev->capture_dma_data;
 201
 202         snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
 203
 204         return 0;
 205 }
 206
 207 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 208                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 209 {
 210         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 211         struct i2s_clk_config_data *config = &dev->config;
 212         u32 ccr, xfer_resolution, ch_reg, irq;
 213         int ret;
 214
 215         switch (params_format(params)) {
 216         case SNDRV_PCM_FORMAT_S16_LE:
 217                 config->data_width = 16;
 218                 ccr = 0x00;
 219                 xfer_resolution = 0x02;
 220                 break;
 221
 222         case SNDRV_PCM_FORMAT_S24_LE:
 223                 config->data_width = 24;
 224                 ccr = 0x08;
 225                 xfer_resolution = 0x04;
 226                 break;
 227
 228         case SNDRV_PCM_FORMAT_S32_LE:
 229                 config->data_width = 32;
 230                 ccr = 0x10;
 231                 xfer_resolution = 0x05;
 232                 break;
 233
 234         default:
 235                 dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
 236                 return -EINVAL;
 237         }
 238
 239         config->chan_nr = params_channels(params);
 240
 241         switch (config->chan_nr) {
 242         case EIGHT_CHANNEL_SUPPORT:
 243                 ch_reg = 3;
 244                 break;
 245         case SIX_CHANNEL_SUPPORT:
 246                 ch_reg = 2;
 247                 break;
 248         case FOUR_CHANNEL_SUPPORT:
 249                 ch_reg = 1;
 250                 break;
 251         case TWO_CHANNEL_SUPPORT:
 252                 ch_reg = 0;
 253                 break;
 254         default:
 255                 dev_err(dev->dev, "channel not supported\n");
 256                 return -EINVAL;
 257         }
 258
 259         i2s_disable_channels(dev, substream->stream);
 260
 261         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 262                 i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution);
 263                 i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
 264                 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
 265                 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
 266                 i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 267         } else {
 268                 i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution);
 269                 i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
 270                 irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
 271                 i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
 272                 i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 273         }
 274
 275         i2s_write_reg(dev->i2s_base, CCR, ccr);
 276
 277         config->sample_rate = params_rate(params);
 278
 279         if (dev->i2s_clk_cfg) {
 280                 ret = dev->i2s_clk_cfg(config);
 281                 if (ret < 0) {
 282                         dev_err(dev->dev, "runtime audio clk config fail\n");
 283                         return ret;
 284                 }
 285         } else {
 286                 u32 bitclk = config->sample_rate * config->data_width * 2;
 287
 288                 ret = clk_set_rate(dev->clk, bitclk);
 289                 if (ret) {
 290                         dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
 291                                 ret);
 292                         return ret;
 293                 }
 294         }
 295
 296         return 0;
 297 }
 298
 299 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
 300                 struct snd_soc_dai *dai)
 301 {
 302         snd_soc_dai_set_dma_data(dai, substream, NULL);
 303 }
 304
 305 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 306                 int cmd, struct snd_soc_dai *dai)
 307 {
 308         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 309         int ret = 0;
 310
 311         switch (cmd) {
 312         case SNDRV_PCM_TRIGGER_START:
 313         case SNDRV_PCM_TRIGGER_RESUME:
 314         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 315                 dev->active++;
 316                 i2s_start(dev, substream);
 317                 break;
 318
 319         case SNDRV_PCM_TRIGGER_STOP:
 320         case SNDRV_PCM_TRIGGER_SUSPEND:
 321         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 322                 dev->active--;
 323                 i2s_stop(dev, substream);
 324                 break;
 325         default:
 326                 ret = -EINVAL;
 327                 break;
 328         }
 329         return ret;
 330 }
 331
 332 static struct snd_soc_dai_ops dw_i2s_dai_ops = {
 333         .startup        = dw_i2s_startup,
 334         .shutdown       = dw_i2s_shutdown,
 335         .hw_params      = dw_i2s_hw_params,
 336         .trigger        = dw_i2s_trigger,
 337 };
 338
 339 static const struct snd_soc_component_driver dw_i2s_component = {
 340         .name           = "dw-i2s",
 341 };
 342
 343 #ifdef CONFIG_PM
 344
 345 static int dw_i2s_suspend(struct snd_soc_dai *dai)
 346 {
 347         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 348
 349         clk_disable(dev->clk);
 350         return 0;
 351 }
 352
 353 static int dw_i2s_resume(struct snd_soc_dai *dai)
 354 {
 355         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 356
 357         clk_enable(dev->clk);
 358         return 0;
 359 }
 360
 361 #else
 362 #define dw_i2s_suspend  NULL
 363 #define dw_i2s_resume   NULL
 364 #endif
 365
 366 /*
 367  * The following tables allow a direct lookup of various parameters
 368  * defined in the I2S block's configuration in terms of sound system
 369  * parameters.  Each table is sized to the number of entries possible
 370  * according to the number of configuration bits describing an I2S
 371  * block parameter.
 372  */
 373
 374 /* Maximum bit resolution of a channel - not uniformly spaced */
 375 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 376         12, 16, 20, 24, 32, 0, 0, 0
 377 };
 378
 379 /* Width of (DMA) bus */
 380 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 381         DMA_SLAVE_BUSWIDTH_1_BYTE,
 382         DMA_SLAVE_BUSWIDTH_2_BYTES,
 383         DMA_SLAVE_BUSWIDTH_4_BYTES,
 384         DMA_SLAVE_BUSWIDTH_UNDEFINED
 385 };
 386
 387 /* PCM format to support channel resolution */
 388 static const u32 formats[COMP_MAX_WORDSIZE] = {
 389         SNDRV_PCM_FMTBIT_S16_LE,
 390         SNDRV_PCM_FMTBIT_S16_LE,
 391         SNDRV_PCM_FMTBIT_S24_LE,
 392         SNDRV_PCM_FMTBIT_S24_LE,
 393         SNDRV_PCM_FMTBIT_S32_LE,
 394         0,
 395         0,
 396         0
 397 };
 398
 399 static int dw_configure_dai(struct dw_i2s_dev *dev,
 400                                    struct snd_soc_dai_driver *dw_i2s_dai,
 401                                    unsigned int rates)
 402 {
 403         /*
 404          * Read component parameter registers to extract
 405          * the I2S block's configuration.
 406          */
 407         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 408         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 409         u32 idx;
 410
 411         if (COMP1_TX_ENABLED(comp1)) {
 412                 dev_dbg(dev->dev, " designware: play supported\n");
 413                 idx = COMP1_TX_WORDSIZE_0(comp1);
 414                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 415                         return -EINVAL;
 416                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 417                 dw_i2s_dai->playback.channels_max =
 418                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
 419                 dw_i2s_dai->playback.formats = formats[idx];
 420                 dw_i2s_dai->playback.rates = rates;
 421         }
 422
 423         if (COMP1_RX_ENABLED(comp1)) {
 424                 dev_dbg(dev->dev, "designware: record supported\n");
 425                 idx = COMP2_RX_WORDSIZE_0(comp2);
 426                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 427                         return -EINVAL;
 428                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
 429                 dw_i2s_dai->capture.channels_max =
 430                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
 431                 dw_i2s_dai->capture.formats = formats[idx];
 432                 dw_i2s_dai->capture.rates = rates;
 433         }
 434
 435         return 0;
 436 }
 437
 438 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
 439                                    struct snd_soc_dai_driver *dw_i2s_dai,
 440                                    struct resource *res,
 441                                    const struct i2s_platform_data *pdata)
 442 {
 443         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 444         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 445         int ret;
 446
 447         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 448                 return -EINVAL;
 449
 450         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
 451         if (ret < 0)
 452                 return ret;
 453
 454         /* Set DMA slaves info */
 455         dev->play_dma_data.pd.data = pdata->play_dma_data;
 456         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
 457         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
 458         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
 459         dev->play_dma_data.pd.max_burst = 16;
 460         dev->capture_dma_data.pd.max_burst = 16;
 461         dev->play_dma_data.pd.addr_width = bus_widths[idx];
 462         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
 463         dev->play_dma_data.pd.filter = pdata->filter;
 464         dev->capture_dma_data.pd.filter = pdata->filter;
 465
 466         return 0;
 467 }
 468
 469 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
 470                                    struct snd_soc_dai_driver *dw_i2s_dai,
 471                                    struct resource *res)
 472 {
 473         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 474         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 475         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 476         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 477         u32 idx2;
 478         int ret;
 479
 480         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 481                 return -EINVAL;
 482
 483         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
 484         if (ret < 0)
 485                 return ret;
 486
 487         if (COMP1_TX_ENABLED(comp1)) {
 488                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
 489
 490                 dev->capability |= DWC_I2S_PLAY;
 491                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
 492                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
 493                 dev->play_dma_data.dt.chan_name = "TX";
 494                 dev->play_dma_data.dt.fifo_size = fifo_depth *
 495                         (fifo_width[idx2]) >> 8;
 496                 dev->play_dma_data.dt.maxburst = 16;
 497         }
 498         if (COMP1_RX_ENABLED(comp1)) {
 499                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
 500
 501                 dev->capability |= DWC_I2S_RECORD;
 502                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
 503                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
 504                 dev->capture_dma_data.dt.chan_name = "RX";
 505                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
 506                         (fifo_width[idx2] >> 8);
 507                 dev->capture_dma_data.dt.maxburst = 16;
 508         }
 509
 510         return 0;
 511
 512 }
 513
 514 static int dw_i2s_probe(struct platform_device *pdev)
 515 {
 516         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
 517         struct dw_i2s_dev *dev;
 518         struct resource *res;
 519         int ret;
 520         struct snd_soc_dai_driver *dw_i2s_dai;
 521
 522         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 523         if (!dev) {
 524                 dev_warn(&pdev->dev, "kzalloc fail\n");
 525                 return -ENOMEM;
 526         }
 527
 528         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
 529         if (!dw_i2s_dai)
 530                 return -ENOMEM;
 531
 532         dw_i2s_dai->ops = &dw_i2s_dai_ops;
 533         dw_i2s_dai->suspend = dw_i2s_suspend;
 534         dw_i2s_dai->resume = dw_i2s_resume;
 535
 536         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 537         dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
 538         if (IS_ERR(dev->i2s_base))
 539                 return PTR_ERR(dev->i2s_base);
 540
 541         dev->dev = &pdev->dev;
 542         if (pdata) {
 543                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
 544                 if (ret < 0)
 545                         return ret;
 546
 547                 dev->capability = pdata->cap;
 548                 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
 549                 if (!dev->i2s_clk_cfg) {
 550                         dev_err(&pdev->dev, "no clock configure method\n");
 551                         return -ENODEV;
 552                 }
 553
 554                 dev->clk = devm_clk_get(&pdev->dev, NULL);
 555         } else {
 556                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
 557                 if (ret < 0)
 558                         return ret;
 559
 560                 dev->clk = devm_clk_get(&pdev->dev, "i2sclk");
 561         }
 562         if (IS_ERR(dev->clk))
 563                 return PTR_ERR(dev->clk);
 564
 565         ret = clk_prepare_enable(dev->clk);
 566         if (ret < 0)
 567                 return ret;
 568
 569         dev_set_drvdata(&pdev->dev, dev);
 570         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
 571                                          dw_i2s_dai, 1);
 572         if (ret != 0) {
 573                 dev_err(&pdev->dev, "not able to register dai\n");
 574                 goto err_clk_disable;
 575         }
 576
 577         if (!pdata) {
 578                 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 579                 if (ret) {
 580                         dev_err(&pdev->dev,
 581                                 "Could not register PCM: %d\n", ret);
 582                         goto err_clk_disable;
 583                 }
 584         }
 585
 586         return 0;
 587
 588 err_clk_disable:
 589         clk_disable_unprepare(dev->clk);
 590         return ret;
 591 }
 592
 593 static int dw_i2s_remove(struct platform_device *pdev)
 594 {
 595         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
 596
 597         clk_disable_unprepare(dev->clk);
 598
 599         return 0;
 600 }
 601
 602 #ifdef CONFIG_OF
 603 static const struct of_device_id dw_i2s_of_match[] = {
 604         { .compatible = "snps,designware-i2s",   },
 605         {},
 606 };
 607
 608 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
 609 #endif
 610
 611 static struct platform_driver dw_i2s_driver = {
 612         .probe          = dw_i2s_probe,
 613         .remove         = dw_i2s_remove,
 614         .driver         = {
 615                 .name   = "designware-i2s",
 616                 .of_match_table = of_match_ptr(dw_i2s_of_match),
 617         },
 618 };
 619
 620 module_platform_driver(dw_i2s_driver);
 621
 622 MODULE_AUTHOR("Rajeev Kumar <rajeevkumar.linux@gmail.com>");
 623 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
 624 MODULE_LICENSE("GPL");
 625 MODULE_ALIAS("platform:designware_i2s");