2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor
4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com>
5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/delay.h>
18 #include <linux/clk.h>
19 #include <linux/platform_data/davinci_asp.h>
21 #include <sound/core.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
27 #include "davinci-pcm.h"
28 #include "davinci-i2s.h"
32 * NOTE: terminology here is confusing.
34 * - This driver supports the "Audio Serial Port" (ASP),
35 * found on dm6446, dm355, and other DaVinci chips.
37 * - But it labels it a "Multi-channel Buffered Serial Port"
38 * (McBSP) as on older chips like the dm642 ... which was
39 * backward-compatible, possibly explaining that confusion.
41 * - OMAP chips have a controller called McBSP, which is
42 * incompatible with the DaVinci flavor of McBSP.
44 * - Newer DaVinci chips have a controller called McASP,
45 * incompatible with ASP and with either McBSP.
47 * In short: this uses ASP to implement I2S, not McBSP.
48 * And it won't be the only DaVinci implemention of I2S.
50 #define DAVINCI_MCBSP_DRR_REG 0x00
51 #define DAVINCI_MCBSP_DXR_REG 0x04
52 #define DAVINCI_MCBSP_SPCR_REG 0x08
53 #define DAVINCI_MCBSP_RCR_REG 0x0c
54 #define DAVINCI_MCBSP_XCR_REG 0x10
55 #define DAVINCI_MCBSP_SRGR_REG 0x14
56 #define DAVINCI_MCBSP_PCR_REG 0x24
58 #define DAVINCI_MCBSP_SPCR_RRST (1 << 0)
59 #define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4)
60 #define DAVINCI_MCBSP_SPCR_XRST (1 << 16)
61 #define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20)
62 #define DAVINCI_MCBSP_SPCR_GRST (1 << 22)
63 #define DAVINCI_MCBSP_SPCR_FRST (1 << 23)
64 #define DAVINCI_MCBSP_SPCR_FREE (1 << 25)
66 #define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5)
67 #define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8)
68 #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
69 #define DAVINCI_MCBSP_RCR_RFIG (1 << 18)
70 #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
71 #define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
72 #define DAVINCI_MCBSP_RCR_RPHASE BIT(31)
74 #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
75 #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
76 #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
77 #define DAVINCI_MCBSP_XCR_XFIG (1 << 18)
78 #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
79 #define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
80 #define DAVINCI_MCBSP_XCR_XPHASE BIT(31)
82 #define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8)
83 #define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16)
84 #define DAVINCI_MCBSP_SRGR_FSGM (1 << 28)
85 #define DAVINCI_MCBSP_SRGR_CLKSM BIT(29)
87 #define DAVINCI_MCBSP_PCR_CLKRP (1 << 0)
88 #define DAVINCI_MCBSP_PCR_CLKXP (1 << 1)
89 #define DAVINCI_MCBSP_PCR_FSRP (1 << 2)
90 #define DAVINCI_MCBSP_PCR_FSXP (1 << 3)
91 #define DAVINCI_MCBSP_PCR_SCLKME (1 << 7)
92 #define DAVINCI_MCBSP_PCR_CLKRM (1 << 8)
93 #define DAVINCI_MCBSP_PCR_CLKXM (1 << 9)
94 #define DAVINCI_MCBSP_PCR_FSRM (1 << 10)
95 #define DAVINCI_MCBSP_PCR_FSXM (1 << 11)
98 DAVINCI_MCBSP_WORD_8 = 0,
99 DAVINCI_MCBSP_WORD_12,
100 DAVINCI_MCBSP_WORD_16,
101 DAVINCI_MCBSP_WORD_20,
102 DAVINCI_MCBSP_WORD_24,
103 DAVINCI_MCBSP_WORD_32,
106 static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = {
107 [SNDRV_PCM_FORMAT_S8] = 1,
108 [SNDRV_PCM_FORMAT_S16_LE] = 2,
109 [SNDRV_PCM_FORMAT_S32_LE] = 4,
112 static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = {
113 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8,
114 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16,
115 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32,
118 static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = {
119 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE,
120 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE,
123 struct davinci_mcbsp_dev {
125 struct davinci_pcm_dma_params dma_params[2];
133 * Combining both channels into 1 element will at least double the
134 * amount of time between servicing the dma channel, increase
135 * effiency, and reduce the chance of overrun/underrun. But,
136 * it will result in the left & right channels being swapped.
138 * If relabeling the left and right channels is not possible,
139 * you may want to let the codec know to swap them back.
141 * It may allow x10 the amount of time to service dma requests,
142 * if the codec is master and is using an unnecessarily fast bit clock
143 * (ie. tlvaic23b), independent of the sample rate. So, having an
144 * entire frame at once means it can be serviced at the sample rate
145 * instead of the bit clock rate.
147 * In the now unlikely case that an underrun still
148 * occurs, both the left and right samples will be repeated
149 * so that no pops are heard, and the left and right channels
150 * won't end up being swapped because of the underrun.
152 unsigned enable_channel_combine:1;
157 bool i2s_accurate_sck;
160 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
163 __raw_writel(val, dev->base + reg);
166 static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
168 return __raw_readl(dev->base + reg);
171 static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
173 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
174 /* The clock needs to toggle to complete reset.
175 * So, fake it by toggling the clk polarity.
177 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
181 static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
182 struct snd_pcm_substream *substream)
184 struct snd_soc_pcm_runtime *rtd = substream->private_data;
185 struct snd_soc_platform *platform = rtd->platform;
186 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
188 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
189 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
191 /* start off disabled */
192 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
194 toggle_clock(dev, playback);
196 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM |
197 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) {
198 /* Start the sample generator */
199 spcr |= DAVINCI_MCBSP_SPCR_GRST;
200 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
204 /* Stop the DMA to avoid data loss */
205 /* while the transmitter is out of reset to handle XSYNCERR */
206 if (platform->driver->ops->trigger) {
207 int ret = platform->driver->ops->trigger(substream,
208 SNDRV_PCM_TRIGGER_STOP);
210 printk(KERN_DEBUG "Playback DMA stop failed\n");
213 /* Enable the transmitter */
214 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
215 spcr |= DAVINCI_MCBSP_SPCR_XRST;
216 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
218 /* wait for any unexpected frame sync error to occur */
221 /* Disable the transmitter to clear any outstanding XSYNCERR */
222 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
223 spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
224 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
225 toggle_clock(dev, playback);
227 /* Restart the DMA */
228 if (platform->driver->ops->trigger) {
229 int ret = platform->driver->ops->trigger(substream,
230 SNDRV_PCM_TRIGGER_START);
232 printk(KERN_DEBUG "Playback DMA start failed\n");
236 /* Enable transmitter or receiver */
237 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
240 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) {
241 /* Start frame sync */
242 spcr |= DAVINCI_MCBSP_SPCR_FRST;
244 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
247 static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
251 /* Reset transmitter/receiver and sample rate/frame sync generators */
252 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
253 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
254 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
255 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
256 toggle_clock(dev, playback);
259 #define DEFAULT_BITPERSAMPLE 16
261 static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
264 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
268 /* Attention srgr is updated by hw_params! */
269 srgr = DAVINCI_MCBSP_SRGR_FSGM |
270 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
271 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
274 /* set master/slave audio interface */
275 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
276 case SND_SOC_DAIFMT_CBS_CFS:
278 pcr = DAVINCI_MCBSP_PCR_FSXM |
279 DAVINCI_MCBSP_PCR_FSRM |
280 DAVINCI_MCBSP_PCR_CLKXM |
281 DAVINCI_MCBSP_PCR_CLKRM;
283 case SND_SOC_DAIFMT_CBM_CFS:
284 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
286 * Selection of the clock input pin that is the
287 * input for the Sample Rate Generator.
288 * McBSP FSR and FSX are driven by the Sample Rate
291 switch (dev->clk_input_pin) {
293 pcr |= DAVINCI_MCBSP_PCR_CLKXM |
294 DAVINCI_MCBSP_PCR_CLKRM;
297 pcr |= DAVINCI_MCBSP_PCR_SCLKME;
300 dev_err(dev->dev, "bad clk_input_pin\n");
305 case SND_SOC_DAIFMT_CBM_CFM:
306 /* codec is master */
310 printk(KERN_ERR "%s:bad master\n", __func__);
314 /* interface format */
315 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
316 case SND_SOC_DAIFMT_I2S:
317 /* Davinci doesn't support TRUE I2S, but some codecs will have
318 * the left and right channels contiguous. This allows
319 * dsp_a mode to be used with an inverted normal frame clk.
320 * If your codec is master and does not have contiguous
321 * channels, then you will have sound on only one channel.
322 * Try using a different mode, or codec as slave.
324 * The TLV320AIC33 is an example of a codec where this works.
325 * It has a variable bit clock frequency allowing it to have
326 * valid data on every bit clock.
328 * The TLV320AIC23 is an example of a codec where this does not
329 * work. It has a fixed bit clock frequency with progressively
330 * more empty bit clock slots between channels as the sample
334 case SND_SOC_DAIFMT_DSP_A:
335 dev->mode = MOD_DSP_A;
337 case SND_SOC_DAIFMT_DSP_B:
338 dev->mode = MOD_DSP_B;
341 printk(KERN_ERR "%s:bad format\n", __func__);
345 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
346 case SND_SOC_DAIFMT_NB_NF:
347 /* CLKRP Receive clock polarity,
348 * 1 - sampled on rising edge of CLKR
349 * valid on rising edge
350 * CLKXP Transmit clock polarity,
351 * 1 - clocked on falling edge of CLKX
352 * valid on rising edge
353 * FSRP Receive frame sync pol, 0 - active high
354 * FSXP Transmit frame sync pol, 0 - active high
356 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP);
358 case SND_SOC_DAIFMT_IB_IF:
359 /* CLKRP Receive clock polarity,
360 * 0 - sampled on falling edge of CLKR
361 * valid on falling edge
362 * CLKXP Transmit clock polarity,
363 * 0 - clocked on rising edge of CLKX
364 * valid on falling edge
365 * FSRP Receive frame sync pol, 1 - active low
366 * FSXP Transmit frame sync pol, 1 - active low
368 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
370 case SND_SOC_DAIFMT_NB_IF:
371 /* CLKRP Receive clock polarity,
372 * 1 - sampled on rising edge of CLKR
373 * valid on rising edge
374 * CLKXP Transmit clock polarity,
375 * 1 - clocked on falling edge of CLKX
376 * valid on rising edge
377 * FSRP Receive frame sync pol, 1 - active low
378 * FSXP Transmit frame sync pol, 1 - active low
380 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP |
381 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
383 case SND_SOC_DAIFMT_IB_NF:
384 /* CLKRP Receive clock polarity,
385 * 0 - sampled on falling edge of CLKR
386 * valid on falling edge
387 * CLKXP Transmit clock polarity,
388 * 0 - clocked on rising edge of CLKX
389 * valid on falling edge
390 * FSRP Receive frame sync pol, 0 - active high
391 * FSXP Transmit frame sync pol, 0 - active high
398 pcr ^= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP);
399 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
401 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
405 static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
408 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
410 if (div_id != DAVINCI_MCBSP_CLKGDV)
417 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
418 struct snd_pcm_hw_params *params,
419 struct snd_soc_dai *dai)
421 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
422 struct davinci_pcm_dma_params *dma_params =
423 &dev->dma_params[substream->stream];
424 struct snd_interval *i = NULL;
425 int mcbsp_word_length, master;
426 unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
428 snd_pcm_format_t fmt;
429 unsigned element_cnt = 1;
431 /* general line settings */
432 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
433 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
434 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
435 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
437 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
438 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
441 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
442 fmt = params_format(params);
443 mcbsp_word_length = asp_word_length[fmt];
446 case SND_SOC_DAIFMT_CBS_CFS:
447 freq = clk_get_rate(dev->clk);
448 srgr = DAVINCI_MCBSP_SRGR_FSGM |
449 DAVINCI_MCBSP_SRGR_CLKSM;
450 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
452 if (dev->i2s_accurate_sck) {
455 framesize = (freq / (--clk_div)) /
458 } while (((framesize < 33) || (framesize > 4095)) &&
461 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
463 /* symmetric waveforms */
464 clk_div = freq / (mcbsp_word_length * 16) /
465 params->rate_num * params->rate_den;
466 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
472 case SND_SOC_DAIFMT_CBM_CFS:
473 srgr = DAVINCI_MCBSP_SRGR_FSGM;
474 clk_div = dev->clk_div - 1;
475 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
476 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
480 case SND_SOC_DAIFMT_CBM_CFM:
481 /* Clock and frame sync given from external sources */
482 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
483 srgr = DAVINCI_MCBSP_SRGR_FSGM;
484 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
485 pr_debug("%s - %d FWID set: re-read srgr = %X\n",
486 __func__, __LINE__, snd_interval_value(i) - 1);
488 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
489 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
494 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
496 rcr = DAVINCI_MCBSP_RCR_RFIG;
497 xcr = DAVINCI_MCBSP_XCR_XFIG;
498 if (dev->mode == MOD_DSP_B) {
499 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0);
500 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0);
502 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1);
503 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1);
505 /* Determine xfer data type */
506 fmt = params_format(params);
507 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) {
508 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n");
512 if (params_channels(params) == 2) {
514 if (double_fmt[fmt] && dev->enable_channel_combine) {
516 fmt = double_fmt[fmt];
519 case SND_SOC_DAIFMT_CBS_CFS:
520 case SND_SOC_DAIFMT_CBS_CFM:
521 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
522 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
523 rcr |= DAVINCI_MCBSP_RCR_RPHASE;
524 xcr |= DAVINCI_MCBSP_XCR_XPHASE;
526 case SND_SOC_DAIFMT_CBM_CFM:
527 case SND_SOC_DAIFMT_CBM_CFS:
528 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
529 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
535 dma_params->acnt = dma_params->data_type = data_type[fmt];
536 dma_params->fifo_level = 0;
537 mcbsp_word_length = asp_word_length[fmt];
540 case SND_SOC_DAIFMT_CBS_CFS:
541 case SND_SOC_DAIFMT_CBS_CFM:
542 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
543 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
545 case SND_SOC_DAIFMT_CBM_CFM:
546 case SND_SOC_DAIFMT_CBM_CFS:
547 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
548 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
554 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
555 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
556 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
557 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
559 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
560 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
562 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
564 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr);
565 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr);
566 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr);
570 static int davinci_i2s_prepare(struct snd_pcm_substream *substream,
571 struct snd_soc_dai *dai)
573 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
574 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
575 davinci_mcbsp_stop(dev, playback);
579 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
580 struct snd_soc_dai *dai)
582 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
584 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
587 case SNDRV_PCM_TRIGGER_START:
588 case SNDRV_PCM_TRIGGER_RESUME:
589 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
590 davinci_mcbsp_start(dev, substream);
592 case SNDRV_PCM_TRIGGER_STOP:
593 case SNDRV_PCM_TRIGGER_SUSPEND:
594 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
595 davinci_mcbsp_stop(dev, playback);
603 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
604 struct snd_soc_dai *dai)
606 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
608 snd_soc_dai_set_dma_data(dai, substream, dev->dma_params);
612 static void davinci_i2s_shutdown(struct snd_pcm_substream *substream,
613 struct snd_soc_dai *dai)
615 struct davinci_mcbsp_dev *dev = snd_soc_dai_get_drvdata(dai);
616 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
617 davinci_mcbsp_stop(dev, playback);
620 #define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000
622 static const struct snd_soc_dai_ops davinci_i2s_dai_ops = {
623 .startup = davinci_i2s_startup,
624 .shutdown = davinci_i2s_shutdown,
625 .prepare = davinci_i2s_prepare,
626 .trigger = davinci_i2s_trigger,
627 .hw_params = davinci_i2s_hw_params,
628 .set_fmt = davinci_i2s_set_dai_fmt,
629 .set_clkdiv = davinci_i2s_dai_set_clkdiv,
633 static struct snd_soc_dai_driver davinci_i2s_dai = {
637 .rates = DAVINCI_I2S_RATES,
638 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
642 .rates = DAVINCI_I2S_RATES,
643 .formats = SNDRV_PCM_FMTBIT_S16_LE,},
644 .ops = &davinci_i2s_dai_ops,
648 static const struct snd_soc_component_driver davinci_i2s_component = {
649 .name = "davinci-i2s",
652 static int davinci_i2s_probe(struct platform_device *pdev)
654 struct snd_platform_data *pdata = pdev->dev.platform_data;
655 struct davinci_mcbsp_dev *dev;
656 struct resource *mem, *ioarea, *res;
657 enum dma_event_q asp_chan_q = EVENTQ_0;
658 enum dma_event_q ram_chan_q = EVENTQ_1;
661 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
663 dev_err(&pdev->dev, "no mem resource?\n");
667 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
671 dev_err(&pdev->dev, "McBSP region already claimed\n");
675 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcbsp_dev),
680 dev->enable_channel_combine = pdata->enable_channel_combine;
681 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
682 pdata->sram_size_playback;
683 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
684 pdata->sram_size_capture;
685 dev->clk_input_pin = pdata->clk_input_pin;
686 dev->i2s_accurate_sck = pdata->i2s_accurate_sck;
687 asp_chan_q = pdata->asp_chan_q;
688 ram_chan_q = pdata->ram_chan_q;
691 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q;
692 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q;
693 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q;
694 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q;
696 dev->clk = clk_get(&pdev->dev, NULL);
697 if (IS_ERR(dev->clk))
699 clk_enable(dev->clk);
701 dev->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
703 dev_err(&pdev->dev, "ioremap failed\n");
705 goto err_release_clk;
708 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr =
709 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DXR_REG);
711 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr =
712 (dma_addr_t)(mem->start + DAVINCI_MCBSP_DRR_REG);
714 /* first TX, then RX */
715 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
717 dev_err(&pdev->dev, "no DMA resource\n");
719 goto err_release_clk;
721 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start;
723 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
725 dev_err(&pdev->dev, "no DMA resource\n");
727 goto err_release_clk;
729 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start;
730 dev->dev = &pdev->dev;
732 dev_set_drvdata(&pdev->dev, dev);
734 ret = snd_soc_register_component(&pdev->dev, &davinci_i2s_component,
735 &davinci_i2s_dai, 1);
737 goto err_release_clk;
739 ret = davinci_soc_platform_register(&pdev->dev);
741 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
742 goto err_unregister_component;
747 err_unregister_component:
748 snd_soc_unregister_component(&pdev->dev);
750 clk_disable(dev->clk);
755 static int davinci_i2s_remove(struct platform_device *pdev)
757 struct davinci_mcbsp_dev *dev = dev_get_drvdata(&pdev->dev);
759 snd_soc_unregister_component(&pdev->dev);
760 davinci_soc_platform_unregister(&pdev->dev);
762 clk_disable(dev->clk);
769 static struct platform_driver davinci_mcbsp_driver = {
770 .probe = davinci_i2s_probe,
771 .remove = davinci_i2s_remove,
773 .name = "davinci-mcbsp",
774 .owner = THIS_MODULE,
778 module_platform_driver(davinci_mcbsp_driver);
780 MODULE_AUTHOR("Vladimir Barinov");
781 MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface");
782 MODULE_LICENSE("GPL");