2 * wm_adsp.c -- Wolfson ADSP support
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/ctype.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/firmware.h>
19 #include <linux/list.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/vmalloc.h>
26 #include <linux/workqueue.h>
27 #include <linux/debugfs.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/soc.h>
32 #include <sound/jack.h>
33 #include <sound/initval.h>
34 #include <sound/tlv.h>
38 #define adsp_crit(_dsp, fmt, ...) \
39 dev_crit(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
40 #define adsp_err(_dsp, fmt, ...) \
41 dev_err(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
42 #define adsp_warn(_dsp, fmt, ...) \
43 dev_warn(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
44 #define adsp_info(_dsp, fmt, ...) \
45 dev_info(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
46 #define adsp_dbg(_dsp, fmt, ...) \
47 dev_dbg(_dsp->dev, "%s: " fmt, _dsp->name, ##__VA_ARGS__)
49 #define compr_err(_obj, fmt, ...) \
50 adsp_err(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
52 #define compr_dbg(_obj, fmt, ...) \
53 adsp_dbg(_obj->dsp, "%s: " fmt, _obj->name ? _obj->name : "legacy", \
56 #define ADSP1_CONTROL_1 0x00
57 #define ADSP1_CONTROL_2 0x02
58 #define ADSP1_CONTROL_3 0x03
59 #define ADSP1_CONTROL_4 0x04
60 #define ADSP1_CONTROL_5 0x06
61 #define ADSP1_CONTROL_6 0x07
62 #define ADSP1_CONTROL_7 0x08
63 #define ADSP1_CONTROL_8 0x09
64 #define ADSP1_CONTROL_9 0x0A
65 #define ADSP1_CONTROL_10 0x0B
66 #define ADSP1_CONTROL_11 0x0C
67 #define ADSP1_CONTROL_12 0x0D
68 #define ADSP1_CONTROL_13 0x0F
69 #define ADSP1_CONTROL_14 0x10
70 #define ADSP1_CONTROL_15 0x11
71 #define ADSP1_CONTROL_16 0x12
72 #define ADSP1_CONTROL_17 0x13
73 #define ADSP1_CONTROL_18 0x14
74 #define ADSP1_CONTROL_19 0x16
75 #define ADSP1_CONTROL_20 0x17
76 #define ADSP1_CONTROL_21 0x18
77 #define ADSP1_CONTROL_22 0x1A
78 #define ADSP1_CONTROL_23 0x1B
79 #define ADSP1_CONTROL_24 0x1C
80 #define ADSP1_CONTROL_25 0x1E
81 #define ADSP1_CONTROL_26 0x20
82 #define ADSP1_CONTROL_27 0x21
83 #define ADSP1_CONTROL_28 0x22
84 #define ADSP1_CONTROL_29 0x23
85 #define ADSP1_CONTROL_30 0x24
86 #define ADSP1_CONTROL_31 0x26
91 #define ADSP1_WDMA_BUFFER_LENGTH_MASK 0x00FF /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
92 #define ADSP1_WDMA_BUFFER_LENGTH_SHIFT 0 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
93 #define ADSP1_WDMA_BUFFER_LENGTH_WIDTH 8 /* DSP1_WDMA_BUFFER_LENGTH - [7:0] */
99 #define ADSP1_DBG_CLK_ENA 0x0008 /* DSP1_DBG_CLK_ENA */
100 #define ADSP1_DBG_CLK_ENA_MASK 0x0008 /* DSP1_DBG_CLK_ENA */
101 #define ADSP1_DBG_CLK_ENA_SHIFT 3 /* DSP1_DBG_CLK_ENA */
102 #define ADSP1_DBG_CLK_ENA_WIDTH 1 /* DSP1_DBG_CLK_ENA */
103 #define ADSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
104 #define ADSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
105 #define ADSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
106 #define ADSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
107 #define ADSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
108 #define ADSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
109 #define ADSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
110 #define ADSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
111 #define ADSP1_START 0x0001 /* DSP1_START */
112 #define ADSP1_START_MASK 0x0001 /* DSP1_START */
113 #define ADSP1_START_SHIFT 0 /* DSP1_START */
114 #define ADSP1_START_WIDTH 1 /* DSP1_START */
119 #define ADSP1_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
120 #define ADSP1_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
121 #define ADSP1_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
123 #define ADSP2_CONTROL 0x0
124 #define ADSP2_CLOCKING 0x1
125 #define ADSP2V2_CLOCKING 0x2
126 #define ADSP2_STATUS1 0x4
127 #define ADSP2_WDMA_CONFIG_1 0x30
128 #define ADSP2_WDMA_CONFIG_2 0x31
129 #define ADSP2V2_WDMA_CONFIG_2 0x32
130 #define ADSP2_RDMA_CONFIG_1 0x34
132 #define ADSP2_SCRATCH0 0x40
133 #define ADSP2_SCRATCH1 0x41
134 #define ADSP2_SCRATCH2 0x42
135 #define ADSP2_SCRATCH3 0x43
137 #define ADSP2V2_SCRATCH0_1 0x40
138 #define ADSP2V2_SCRATCH2_3 0x42
144 #define ADSP2_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
145 #define ADSP2_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
146 #define ADSP2_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
147 #define ADSP2_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
148 #define ADSP2_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
149 #define ADSP2_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
150 #define ADSP2_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
151 #define ADSP2_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
152 #define ADSP2_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
153 #define ADSP2_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
154 #define ADSP2_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
155 #define ADSP2_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
156 #define ADSP2_START 0x0001 /* DSP1_START */
157 #define ADSP2_START_MASK 0x0001 /* DSP1_START */
158 #define ADSP2_START_SHIFT 0 /* DSP1_START */
159 #define ADSP2_START_WIDTH 1 /* DSP1_START */
164 #define ADSP2_CLK_SEL_MASK 0x0007 /* CLK_SEL_ENA */
165 #define ADSP2_CLK_SEL_SHIFT 0 /* CLK_SEL_ENA */
166 #define ADSP2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
171 #define ADSP2V2_CLK_SEL_MASK 0x70000 /* CLK_SEL_ENA */
172 #define ADSP2V2_CLK_SEL_SHIFT 16 /* CLK_SEL_ENA */
173 #define ADSP2V2_CLK_SEL_WIDTH 3 /* CLK_SEL_ENA */
175 #define ADSP2V2_RATE_MASK 0x7800 /* DSP_RATE */
176 #define ADSP2V2_RATE_SHIFT 11 /* DSP_RATE */
177 #define ADSP2V2_RATE_WIDTH 4 /* DSP_RATE */
182 #define ADSP2_RAM_RDY 0x0001
183 #define ADSP2_RAM_RDY_MASK 0x0001
184 #define ADSP2_RAM_RDY_SHIFT 0
185 #define ADSP2_RAM_RDY_WIDTH 1
190 #define ADSP2_LOCK_CODE_0 0x5555
191 #define ADSP2_LOCK_CODE_1 0xAAAA
193 #define ADSP2_WATCHDOG 0x0A
194 #define ADSP2_BUS_ERR_ADDR 0x52
195 #define ADSP2_REGION_LOCK_STATUS 0x64
196 #define ADSP2_LOCK_REGION_1_LOCK_REGION_0 0x66
197 #define ADSP2_LOCK_REGION_3_LOCK_REGION_2 0x68
198 #define ADSP2_LOCK_REGION_5_LOCK_REGION_4 0x6A
199 #define ADSP2_LOCK_REGION_7_LOCK_REGION_6 0x6C
200 #define ADSP2_LOCK_REGION_9_LOCK_REGION_8 0x6E
201 #define ADSP2_LOCK_REGION_CTRL 0x7A
202 #define ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR 0x7C
204 #define ADSP2_REGION_LOCK_ERR_MASK 0x8000
205 #define ADSP2_SLAVE_ERR_MASK 0x4000
206 #define ADSP2_WDT_TIMEOUT_STS_MASK 0x2000
207 #define ADSP2_CTRL_ERR_PAUSE_ENA 0x0002
208 #define ADSP2_CTRL_ERR_EINT 0x0001
210 #define ADSP2_BUS_ERR_ADDR_MASK 0x00FFFFFF
211 #define ADSP2_XMEM_ERR_ADDR_MASK 0x0000FFFF
212 #define ADSP2_PMEM_ERR_ADDR_MASK 0x7FFF0000
213 #define ADSP2_PMEM_ERR_ADDR_SHIFT 16
214 #define ADSP2_WDT_ENA_MASK 0xFFFFFFFD
216 #define ADSP2_LOCK_REGION_SHIFT 16
218 #define ADSP_MAX_STD_CTRL_SIZE 512
220 #define WM_ADSP_ACKED_CTL_TIMEOUT_MS 100
221 #define WM_ADSP_ACKED_CTL_N_QUICKPOLLS 10
222 #define WM_ADSP_ACKED_CTL_MIN_VALUE 0
223 #define WM_ADSP_ACKED_CTL_MAX_VALUE 0xFFFFFF
226 * Event control messages
228 #define WM_ADSP_FW_EVENT_SHUTDOWN 0x000001
231 struct list_head list;
235 static struct wm_adsp_buf *wm_adsp_buf_alloc(const void *src, size_t len,
236 struct list_head *list)
238 struct wm_adsp_buf *buf = kzalloc(sizeof(*buf), GFP_KERNEL);
243 buf->buf = vmalloc(len);
248 memcpy(buf->buf, src, len);
251 list_add_tail(&buf->list, list);
256 static void wm_adsp_buf_free(struct list_head *list)
258 while (!list_empty(list)) {
259 struct wm_adsp_buf *buf = list_first_entry(list,
262 list_del(&buf->list);
268 #define WM_ADSP_FW_MBC_VSS 0
269 #define WM_ADSP_FW_HIFI 1
270 #define WM_ADSP_FW_TX 2
271 #define WM_ADSP_FW_TX_SPK 3
272 #define WM_ADSP_FW_RX 4
273 #define WM_ADSP_FW_RX_ANC 5
274 #define WM_ADSP_FW_CTRL 6
275 #define WM_ADSP_FW_ASR 7
276 #define WM_ADSP_FW_TRACE 8
277 #define WM_ADSP_FW_SPK_PROT 9
278 #define WM_ADSP_FW_MISC 10
280 #define WM_ADSP_NUM_FW 11
282 static const char *wm_adsp_fw_text[WM_ADSP_NUM_FW] = {
283 [WM_ADSP_FW_MBC_VSS] = "MBC/VSS",
284 [WM_ADSP_FW_HIFI] = "MasterHiFi",
285 [WM_ADSP_FW_TX] = "Tx",
286 [WM_ADSP_FW_TX_SPK] = "Tx Speaker",
287 [WM_ADSP_FW_RX] = "Rx",
288 [WM_ADSP_FW_RX_ANC] = "Rx ANC",
289 [WM_ADSP_FW_CTRL] = "Voice Ctrl",
290 [WM_ADSP_FW_ASR] = "ASR Assist",
291 [WM_ADSP_FW_TRACE] = "Dbg Trace",
292 [WM_ADSP_FW_SPK_PROT] = "Protection",
293 [WM_ADSP_FW_MISC] = "Misc",
296 struct wm_adsp_system_config_xm_hdr {
302 __be32 dma_buffer_size;
305 __be32 build_job_name[3];
306 __be32 build_job_number;
309 struct wm_adsp_alg_xm_struct {
315 __be32 high_water_mark;
316 __be32 low_water_mark;
317 __be64 smoothed_power;
320 struct wm_adsp_host_buf_coeff_v1 {
321 __be32 host_buf_ptr; /* Host buffer pointer */
322 __be32 versions; /* Version numbers */
323 __be32 name[4]; /* The buffer name */
326 struct wm_adsp_buffer {
327 __be32 buf1_base; /* Base addr of first buffer area */
328 __be32 buf1_size; /* Size of buf1 area in DSP words */
329 __be32 buf2_base; /* Base addr of 2nd buffer area */
330 __be32 buf1_buf2_size; /* Size of buf1+buf2 in DSP words */
331 __be32 buf3_base; /* Base addr of buf3 area */
332 __be32 buf_total_size; /* Size of buf1+buf2+buf3 in DSP words */
333 __be32 high_water_mark; /* Point at which IRQ is asserted */
334 __be32 irq_count; /* bits 1-31 count IRQ assertions */
335 __be32 irq_ack; /* acked IRQ count, bit 0 enables IRQ */
336 __be32 next_write_index; /* word index of next write */
337 __be32 next_read_index; /* word index of next read */
338 __be32 error; /* error if any */
339 __be32 oldest_block_index; /* word index of oldest surviving */
340 __be32 requested_rewind; /* how many blocks rewind was done */
341 __be32 reserved_space; /* internal */
342 __be32 min_free; /* min free space since stream start */
343 __be32 blocks_written[2]; /* total blocks written (64 bit) */
344 __be32 words_written[2]; /* total words written (64 bit) */
347 struct wm_adsp_compr;
349 struct wm_adsp_compr_buf {
350 struct list_head list;
352 struct wm_adsp_compr *compr;
354 struct wm_adsp_buffer_region *regions;
361 int host_buf_mem_type;
366 struct wm_adsp_compr {
367 struct list_head list;
369 struct wm_adsp_compr_buf *buf;
371 struct snd_compr_stream *stream;
372 struct snd_compressed_buffer size;
375 unsigned int copied_total;
377 unsigned int sample_rate;
382 #define WM_ADSP_DATA_WORD_SIZE 3
384 #define WM_ADSP_MIN_FRAGMENTS 1
385 #define WM_ADSP_MAX_FRAGMENTS 256
386 #define WM_ADSP_MIN_FRAGMENT_SIZE (64 * WM_ADSP_DATA_WORD_SIZE)
387 #define WM_ADSP_MAX_FRAGMENT_SIZE (4096 * WM_ADSP_DATA_WORD_SIZE)
389 #define WM_ADSP_ALG_XM_STRUCT_MAGIC 0x49aec7
391 #define HOST_BUFFER_FIELD(field) \
392 (offsetof(struct wm_adsp_buffer, field) / sizeof(__be32))
394 #define ALG_XM_FIELD(field) \
395 (offsetof(struct wm_adsp_alg_xm_struct, field) / sizeof(__be32))
397 #define HOST_BUF_COEFF_SUPPORTED_COMPAT_VER 1
399 #define HOST_BUF_COEFF_COMPAT_VER_MASK 0xFF00
400 #define HOST_BUF_COEFF_COMPAT_VER_SHIFT 8
402 static int wm_adsp_buffer_init(struct wm_adsp *dsp);
403 static int wm_adsp_buffer_free(struct wm_adsp *dsp);
405 struct wm_adsp_buffer_region {
407 unsigned int cumulative_size;
408 unsigned int mem_type;
409 unsigned int base_addr;
412 struct wm_adsp_buffer_region_def {
413 unsigned int mem_type;
414 unsigned int base_offset;
415 unsigned int size_offset;
418 static const struct wm_adsp_buffer_region_def default_regions[] = {
420 .mem_type = WMFW_ADSP2_XM,
421 .base_offset = HOST_BUFFER_FIELD(buf1_base),
422 .size_offset = HOST_BUFFER_FIELD(buf1_size),
425 .mem_type = WMFW_ADSP2_XM,
426 .base_offset = HOST_BUFFER_FIELD(buf2_base),
427 .size_offset = HOST_BUFFER_FIELD(buf1_buf2_size),
430 .mem_type = WMFW_ADSP2_YM,
431 .base_offset = HOST_BUFFER_FIELD(buf3_base),
432 .size_offset = HOST_BUFFER_FIELD(buf_total_size),
436 struct wm_adsp_fw_caps {
438 struct snd_codec_desc desc;
440 const struct wm_adsp_buffer_region_def *region_defs;
443 static const struct wm_adsp_fw_caps ctrl_caps[] = {
445 .id = SND_AUDIOCODEC_BESPOKE,
448 .sample_rates = { 16000 },
449 .num_sample_rates = 1,
450 .formats = SNDRV_PCM_FMTBIT_S16_LE,
452 .num_regions = ARRAY_SIZE(default_regions),
453 .region_defs = default_regions,
457 static const struct wm_adsp_fw_caps trace_caps[] = {
459 .id = SND_AUDIOCODEC_BESPOKE,
463 4000, 8000, 11025, 12000, 16000, 22050,
464 24000, 32000, 44100, 48000, 64000, 88200,
465 96000, 176400, 192000
467 .num_sample_rates = 15,
468 .formats = SNDRV_PCM_FMTBIT_S16_LE,
470 .num_regions = ARRAY_SIZE(default_regions),
471 .region_defs = default_regions,
475 static const struct {
479 const struct wm_adsp_fw_caps *caps;
481 } wm_adsp_fw[WM_ADSP_NUM_FW] = {
482 [WM_ADSP_FW_MBC_VSS] = { .file = "mbc-vss" },
483 [WM_ADSP_FW_HIFI] = { .file = "hifi" },
484 [WM_ADSP_FW_TX] = { .file = "tx" },
485 [WM_ADSP_FW_TX_SPK] = { .file = "tx-spk" },
486 [WM_ADSP_FW_RX] = { .file = "rx" },
487 [WM_ADSP_FW_RX_ANC] = { .file = "rx-anc" },
488 [WM_ADSP_FW_CTRL] = {
490 .compr_direction = SND_COMPRESS_CAPTURE,
491 .num_caps = ARRAY_SIZE(ctrl_caps),
493 .voice_trigger = true,
495 [WM_ADSP_FW_ASR] = { .file = "asr" },
496 [WM_ADSP_FW_TRACE] = {
498 .compr_direction = SND_COMPRESS_CAPTURE,
499 .num_caps = ARRAY_SIZE(trace_caps),
502 [WM_ADSP_FW_SPK_PROT] = { .file = "spk-prot" },
503 [WM_ADSP_FW_MISC] = { .file = "misc" },
506 struct wm_coeff_ctl_ops {
507 int (*xget)(struct snd_kcontrol *kcontrol,
508 struct snd_ctl_elem_value *ucontrol);
509 int (*xput)(struct snd_kcontrol *kcontrol,
510 struct snd_ctl_elem_value *ucontrol);
513 struct wm_coeff_ctl {
516 struct wm_adsp_alg_region alg_region;
517 struct wm_coeff_ctl_ops ops;
519 unsigned int enabled:1;
520 struct list_head list;
525 struct soc_bytes_ext bytes_ext;
530 static const char *wm_adsp_mem_region_name(unsigned int type)
548 #ifdef CONFIG_DEBUG_FS
549 static void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp, const char *s)
551 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
553 kfree(dsp->wmfw_file_name);
554 dsp->wmfw_file_name = tmp;
557 static void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp, const char *s)
559 char *tmp = kasprintf(GFP_KERNEL, "%s\n", s);
561 kfree(dsp->bin_file_name);
562 dsp->bin_file_name = tmp;
565 static void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
567 kfree(dsp->wmfw_file_name);
568 kfree(dsp->bin_file_name);
569 dsp->wmfw_file_name = NULL;
570 dsp->bin_file_name = NULL;
573 static ssize_t wm_adsp_debugfs_wmfw_read(struct file *file,
574 char __user *user_buf,
575 size_t count, loff_t *ppos)
577 struct wm_adsp *dsp = file->private_data;
580 mutex_lock(&dsp->pwr_lock);
582 if (!dsp->wmfw_file_name || !dsp->booted)
585 ret = simple_read_from_buffer(user_buf, count, ppos,
587 strlen(dsp->wmfw_file_name));
589 mutex_unlock(&dsp->pwr_lock);
593 static ssize_t wm_adsp_debugfs_bin_read(struct file *file,
594 char __user *user_buf,
595 size_t count, loff_t *ppos)
597 struct wm_adsp *dsp = file->private_data;
600 mutex_lock(&dsp->pwr_lock);
602 if (!dsp->bin_file_name || !dsp->booted)
605 ret = simple_read_from_buffer(user_buf, count, ppos,
607 strlen(dsp->bin_file_name));
609 mutex_unlock(&dsp->pwr_lock);
613 static const struct {
615 const struct file_operations fops;
616 } wm_adsp_debugfs_fops[] = {
618 .name = "wmfw_file_name",
621 .read = wm_adsp_debugfs_wmfw_read,
625 .name = "bin_file_name",
628 .read = wm_adsp_debugfs_bin_read,
633 static void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
634 struct snd_soc_component *component)
636 struct dentry *root = NULL;
639 if (!component->debugfs_root) {
640 adsp_err(dsp, "No codec debugfs root\n");
644 root = debugfs_create_dir(dsp->name, component->debugfs_root);
649 if (!debugfs_create_bool("booted", 0444, root, &dsp->booted))
652 if (!debugfs_create_bool("running", 0444, root, &dsp->running))
655 if (!debugfs_create_x32("fw_id", 0444, root, &dsp->fw_id))
658 if (!debugfs_create_x32("fw_version", 0444, root, &dsp->fw_id_version))
661 for (i = 0; i < ARRAY_SIZE(wm_adsp_debugfs_fops); ++i) {
662 if (!debugfs_create_file(wm_adsp_debugfs_fops[i].name,
664 &wm_adsp_debugfs_fops[i].fops))
668 dsp->debugfs_root = root;
672 debugfs_remove_recursive(root);
673 adsp_err(dsp, "Failed to create debugfs\n");
676 static void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
678 wm_adsp_debugfs_clear(dsp);
679 debugfs_remove_recursive(dsp->debugfs_root);
682 static inline void wm_adsp2_init_debugfs(struct wm_adsp *dsp,
683 struct snd_soc_component *component)
687 static inline void wm_adsp2_cleanup_debugfs(struct wm_adsp *dsp)
691 static inline void wm_adsp_debugfs_save_wmfwname(struct wm_adsp *dsp,
696 static inline void wm_adsp_debugfs_save_binname(struct wm_adsp *dsp,
701 static inline void wm_adsp_debugfs_clear(struct wm_adsp *dsp)
706 int wm_adsp_fw_get(struct snd_kcontrol *kcontrol,
707 struct snd_ctl_elem_value *ucontrol)
709 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
710 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
711 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
713 ucontrol->value.enumerated.item[0] = dsp[e->shift_l].fw;
717 EXPORT_SYMBOL_GPL(wm_adsp_fw_get);
719 int wm_adsp_fw_put(struct snd_kcontrol *kcontrol,
720 struct snd_ctl_elem_value *ucontrol)
722 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
723 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
724 struct wm_adsp *dsp = snd_soc_component_get_drvdata(component);
727 if (ucontrol->value.enumerated.item[0] == dsp[e->shift_l].fw)
730 if (ucontrol->value.enumerated.item[0] >= WM_ADSP_NUM_FW)
733 mutex_lock(&dsp[e->shift_l].pwr_lock);
735 if (dsp[e->shift_l].booted || !list_empty(&dsp[e->shift_l].compr_list))
738 dsp[e->shift_l].fw = ucontrol->value.enumerated.item[0];
740 mutex_unlock(&dsp[e->shift_l].pwr_lock);
744 EXPORT_SYMBOL_GPL(wm_adsp_fw_put);
746 const struct soc_enum wm_adsp_fw_enum[] = {
747 SOC_ENUM_SINGLE(0, 0, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
748 SOC_ENUM_SINGLE(0, 1, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
749 SOC_ENUM_SINGLE(0, 2, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
750 SOC_ENUM_SINGLE(0, 3, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
751 SOC_ENUM_SINGLE(0, 4, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
752 SOC_ENUM_SINGLE(0, 5, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
753 SOC_ENUM_SINGLE(0, 6, ARRAY_SIZE(wm_adsp_fw_text), wm_adsp_fw_text),
755 EXPORT_SYMBOL_GPL(wm_adsp_fw_enum);
757 static struct wm_adsp_region const *wm_adsp_find_region(struct wm_adsp *dsp,
762 for (i = 0; i < dsp->num_mems; i++)
763 if (dsp->mem[i].type == type)
769 static unsigned int wm_adsp_region_to_reg(struct wm_adsp_region const *mem,
776 return mem->base + (offset * 3);
778 return mem->base + (offset * 2);
780 return mem->base + (offset * 2);
782 return mem->base + (offset * 2);
784 return mem->base + (offset * 2);
786 WARN(1, "Unknown memory region type");
791 static void wm_adsp2_show_fw_status(struct wm_adsp *dsp)
793 unsigned int scratch[4];
794 unsigned int addr = dsp->base + ADSP2_SCRATCH0;
798 for (i = 0; i < ARRAY_SIZE(scratch); ++i) {
799 ret = regmap_read(dsp->regmap, addr + i, &scratch[i]);
801 adsp_err(dsp, "Failed to read SCRATCH%u: %d\n", i, ret);
806 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
807 scratch[0], scratch[1], scratch[2], scratch[3]);
810 static void wm_adsp2v2_show_fw_status(struct wm_adsp *dsp)
812 unsigned int scratch[2];
815 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH0_1,
818 adsp_err(dsp, "Failed to read SCRATCH0_1: %d\n", ret);
822 ret = regmap_read(dsp->regmap, dsp->base + ADSP2V2_SCRATCH2_3,
825 adsp_err(dsp, "Failed to read SCRATCH2_3: %d\n", ret);
829 adsp_dbg(dsp, "FW SCRATCH 0:0x%x 1:0x%x 2:0x%x 3:0x%x\n",
836 static inline struct wm_coeff_ctl *bytes_ext_to_ctl(struct soc_bytes_ext *ext)
838 return container_of(ext, struct wm_coeff_ctl, bytes_ext);
841 static int wm_coeff_base_reg(struct wm_coeff_ctl *ctl, unsigned int *reg)
843 const struct wm_adsp_alg_region *alg_region = &ctl->alg_region;
844 struct wm_adsp *dsp = ctl->dsp;
845 const struct wm_adsp_region *mem;
847 mem = wm_adsp_find_region(dsp, alg_region->type);
849 adsp_err(dsp, "No base for region %x\n",
854 *reg = wm_adsp_region_to_reg(mem, ctl->alg_region.base + ctl->offset);
859 static int wm_coeff_info(struct snd_kcontrol *kctl,
860 struct snd_ctl_elem_info *uinfo)
862 struct soc_bytes_ext *bytes_ext =
863 (struct soc_bytes_ext *)kctl->private_value;
864 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
867 case WMFW_CTL_TYPE_ACKED:
868 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
869 uinfo->value.integer.min = WM_ADSP_ACKED_CTL_MIN_VALUE;
870 uinfo->value.integer.max = WM_ADSP_ACKED_CTL_MAX_VALUE;
871 uinfo->value.integer.step = 1;
875 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
876 uinfo->count = ctl->len;
883 static int wm_coeff_write_acked_control(struct wm_coeff_ctl *ctl,
884 unsigned int event_id)
886 struct wm_adsp *dsp = ctl->dsp;
887 u32 val = cpu_to_be32(event_id);
891 ret = wm_coeff_base_reg(ctl, ®);
895 adsp_dbg(dsp, "Sending 0x%x to acked control alg 0x%x %s:0x%x\n",
896 event_id, ctl->alg_region.alg,
897 wm_adsp_mem_region_name(ctl->alg_region.type), ctl->offset);
899 ret = regmap_raw_write(dsp->regmap, reg, &val, sizeof(val));
901 adsp_err(dsp, "Failed to write %x: %d\n", reg, ret);
906 * Poll for ack, we initially poll at ~1ms intervals for firmwares
907 * that respond quickly, then go to ~10ms polls. A firmware is unlikely
908 * to ack instantly so we do the first 1ms delay before reading the
909 * control to avoid a pointless bus transaction
911 for (i = 0; i < WM_ADSP_ACKED_CTL_TIMEOUT_MS;) {
913 case 0 ... WM_ADSP_ACKED_CTL_N_QUICKPOLLS - 1:
914 usleep_range(1000, 2000);
918 usleep_range(10000, 20000);
923 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
925 adsp_err(dsp, "Failed to read %x: %d\n", reg, ret);
930 adsp_dbg(dsp, "Acked control ACKED at poll %u\n", i);
935 adsp_warn(dsp, "Acked control @0x%x alg:0x%x %s:0x%x timed out\n",
936 reg, ctl->alg_region.alg,
937 wm_adsp_mem_region_name(ctl->alg_region.type),
943 static int wm_coeff_write_control(struct wm_coeff_ctl *ctl,
944 const void *buf, size_t len)
946 struct wm_adsp *dsp = ctl->dsp;
951 ret = wm_coeff_base_reg(ctl, ®);
955 scratch = kmemdup(buf, len, GFP_KERNEL | GFP_DMA);
959 ret = regmap_raw_write(dsp->regmap, reg, scratch,
962 adsp_err(dsp, "Failed to write %zu bytes to %x: %d\n",
967 adsp_dbg(dsp, "Wrote %zu bytes to %x\n", len, reg);
974 static int wm_coeff_put(struct snd_kcontrol *kctl,
975 struct snd_ctl_elem_value *ucontrol)
977 struct soc_bytes_ext *bytes_ext =
978 (struct soc_bytes_ext *)kctl->private_value;
979 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
980 char *p = ucontrol->value.bytes.data;
983 mutex_lock(&ctl->dsp->pwr_lock);
985 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
988 memcpy(ctl->cache, p, ctl->len);
991 if (ctl->enabled && ctl->dsp->running)
992 ret = wm_coeff_write_control(ctl, p, ctl->len);
994 mutex_unlock(&ctl->dsp->pwr_lock);
999 static int wm_coeff_tlv_put(struct snd_kcontrol *kctl,
1000 const unsigned int __user *bytes, unsigned int size)
1002 struct soc_bytes_ext *bytes_ext =
1003 (struct soc_bytes_ext *)kctl->private_value;
1004 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1007 mutex_lock(&ctl->dsp->pwr_lock);
1009 if (copy_from_user(ctl->cache, bytes, size)) {
1013 if (ctl->enabled && ctl->dsp->running)
1014 ret = wm_coeff_write_control(ctl, ctl->cache, size);
1015 else if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1019 mutex_unlock(&ctl->dsp->pwr_lock);
1024 static int wm_coeff_put_acked(struct snd_kcontrol *kctl,
1025 struct snd_ctl_elem_value *ucontrol)
1027 struct soc_bytes_ext *bytes_ext =
1028 (struct soc_bytes_ext *)kctl->private_value;
1029 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1030 unsigned int val = ucontrol->value.integer.value[0];
1034 return 0; /* 0 means no event */
1036 mutex_lock(&ctl->dsp->pwr_lock);
1038 if (ctl->enabled && ctl->dsp->running)
1039 ret = wm_coeff_write_acked_control(ctl, val);
1043 mutex_unlock(&ctl->dsp->pwr_lock);
1048 static int wm_coeff_read_control(struct wm_coeff_ctl *ctl,
1049 void *buf, size_t len)
1051 struct wm_adsp *dsp = ctl->dsp;
1056 ret = wm_coeff_base_reg(ctl, ®);
1060 scratch = kmalloc(len, GFP_KERNEL | GFP_DMA);
1064 ret = regmap_raw_read(dsp->regmap, reg, scratch, len);
1066 adsp_err(dsp, "Failed to read %zu bytes from %x: %d\n",
1071 adsp_dbg(dsp, "Read %zu bytes from %x\n", len, reg);
1073 memcpy(buf, scratch, len);
1079 static int wm_coeff_get(struct snd_kcontrol *kctl,
1080 struct snd_ctl_elem_value *ucontrol)
1082 struct soc_bytes_ext *bytes_ext =
1083 (struct soc_bytes_ext *)kctl->private_value;
1084 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1085 char *p = ucontrol->value.bytes.data;
1088 mutex_lock(&ctl->dsp->pwr_lock);
1090 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1091 if (ctl->enabled && ctl->dsp->running)
1092 ret = wm_coeff_read_control(ctl, p, ctl->len);
1096 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1097 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1099 memcpy(p, ctl->cache, ctl->len);
1102 mutex_unlock(&ctl->dsp->pwr_lock);
1107 static int wm_coeff_tlv_get(struct snd_kcontrol *kctl,
1108 unsigned int __user *bytes, unsigned int size)
1110 struct soc_bytes_ext *bytes_ext =
1111 (struct soc_bytes_ext *)kctl->private_value;
1112 struct wm_coeff_ctl *ctl = bytes_ext_to_ctl(bytes_ext);
1115 mutex_lock(&ctl->dsp->pwr_lock);
1117 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE) {
1118 if (ctl->enabled && ctl->dsp->running)
1119 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1123 if (!ctl->flags && ctl->enabled && ctl->dsp->running)
1124 ret = wm_coeff_read_control(ctl, ctl->cache, size);
1127 if (!ret && copy_to_user(bytes, ctl->cache, size))
1130 mutex_unlock(&ctl->dsp->pwr_lock);
1135 static int wm_coeff_get_acked(struct snd_kcontrol *kcontrol,
1136 struct snd_ctl_elem_value *ucontrol)
1139 * Although it's not useful to read an acked control, we must satisfy
1140 * user-side assumptions that all controls are readable and that a
1141 * write of the same value should be filtered out (it's valid to send
1142 * the same event number again to the firmware). We therefore return 0,
1143 * meaning "no event" so valid event numbers will always be a change
1145 ucontrol->value.integer.value[0] = 0;
1150 struct wmfw_ctl_work {
1151 struct wm_adsp *dsp;
1152 struct wm_coeff_ctl *ctl;
1153 struct work_struct work;
1156 static unsigned int wmfw_convert_flags(unsigned int in, unsigned int len)
1158 unsigned int out, rd, wr, vol;
1160 if (len > ADSP_MAX_STD_CTRL_SIZE) {
1161 rd = SNDRV_CTL_ELEM_ACCESS_TLV_READ;
1162 wr = SNDRV_CTL_ELEM_ACCESS_TLV_WRITE;
1163 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1165 out = SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK;
1167 rd = SNDRV_CTL_ELEM_ACCESS_READ;
1168 wr = SNDRV_CTL_ELEM_ACCESS_WRITE;
1169 vol = SNDRV_CTL_ELEM_ACCESS_VOLATILE;
1175 if (in & WMFW_CTL_FLAG_READABLE)
1177 if (in & WMFW_CTL_FLAG_WRITEABLE)
1179 if (in & WMFW_CTL_FLAG_VOLATILE)
1182 out |= rd | wr | vol;
1188 static int wmfw_add_ctl(struct wm_adsp *dsp, struct wm_coeff_ctl *ctl)
1190 struct snd_kcontrol_new *kcontrol;
1193 if (!ctl || !ctl->name)
1196 kcontrol = kzalloc(sizeof(*kcontrol), GFP_KERNEL);
1200 kcontrol->name = ctl->name;
1201 kcontrol->info = wm_coeff_info;
1202 kcontrol->iface = SNDRV_CTL_ELEM_IFACE_MIXER;
1203 kcontrol->tlv.c = snd_soc_bytes_tlv_callback;
1204 kcontrol->private_value = (unsigned long)&ctl->bytes_ext;
1205 kcontrol->access = wmfw_convert_flags(ctl->flags, ctl->len);
1207 switch (ctl->type) {
1208 case WMFW_CTL_TYPE_ACKED:
1209 kcontrol->get = wm_coeff_get_acked;
1210 kcontrol->put = wm_coeff_put_acked;
1213 if (kcontrol->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1214 ctl->bytes_ext.max = ctl->len;
1215 ctl->bytes_ext.get = wm_coeff_tlv_get;
1216 ctl->bytes_ext.put = wm_coeff_tlv_put;
1218 kcontrol->get = wm_coeff_get;
1219 kcontrol->put = wm_coeff_put;
1224 ret = snd_soc_add_component_controls(dsp->component, kcontrol, 1);
1237 static int wm_coeff_init_control_caches(struct wm_adsp *dsp)
1239 struct wm_coeff_ctl *ctl;
1242 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1243 if (!ctl->enabled || ctl->set)
1245 if (ctl->flags & WMFW_CTL_FLAG_VOLATILE)
1249 * For readable controls populate the cache from the DSP memory.
1250 * For non-readable controls the cache was zero-filled when
1251 * created so we don't need to do anything.
1253 if (!ctl->flags || (ctl->flags & WMFW_CTL_FLAG_READABLE)) {
1254 ret = wm_coeff_read_control(ctl, ctl->cache, ctl->len);
1263 static int wm_coeff_sync_controls(struct wm_adsp *dsp)
1265 struct wm_coeff_ctl *ctl;
1268 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1271 if (ctl->set && !(ctl->flags & WMFW_CTL_FLAG_VOLATILE)) {
1272 ret = wm_coeff_write_control(ctl, ctl->cache, ctl->len);
1281 static void wm_adsp_signal_event_controls(struct wm_adsp *dsp,
1284 struct wm_coeff_ctl *ctl;
1287 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1288 if (ctl->type != WMFW_CTL_TYPE_HOSTEVENT)
1294 ret = wm_coeff_write_acked_control(ctl, event);
1297 "Failed to send 0x%x event to alg 0x%x (%d)\n",
1298 event, ctl->alg_region.alg, ret);
1302 static void wm_adsp_ctl_work(struct work_struct *work)
1304 struct wmfw_ctl_work *ctl_work = container_of(work,
1305 struct wmfw_ctl_work,
1308 wmfw_add_ctl(ctl_work->dsp, ctl_work->ctl);
1312 static void wm_adsp_free_ctl_blk(struct wm_coeff_ctl *ctl)
1319 static int wm_adsp_create_control(struct wm_adsp *dsp,
1320 const struct wm_adsp_alg_region *alg_region,
1321 unsigned int offset, unsigned int len,
1322 const char *subname, unsigned int subname_len,
1323 unsigned int flags, unsigned int type)
1325 struct wm_coeff_ctl *ctl;
1326 struct wmfw_ctl_work *ctl_work;
1327 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
1328 const char *region_name;
1331 region_name = wm_adsp_mem_region_name(alg_region->type);
1333 adsp_err(dsp, "Unknown region type: %d\n", alg_region->type);
1337 switch (dsp->fw_ver) {
1340 snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN, "%s %s %x",
1341 dsp->name, region_name, alg_region->alg);
1344 ret = snprintf(name, SNDRV_CTL_ELEM_ID_NAME_MAXLEN,
1345 "%s%c %.12s %x", dsp->name, *region_name,
1346 wm_adsp_fw_text[dsp->fw], alg_region->alg);
1348 /* Truncate the subname from the start if it is too long */
1350 int avail = SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret - 2;
1353 if (dsp->component->name_prefix)
1354 avail -= strlen(dsp->component->name_prefix) + 1;
1356 if (subname_len > avail)
1357 skip = subname_len - avail;
1359 snprintf(name + ret,
1360 SNDRV_CTL_ELEM_ID_NAME_MAXLEN - ret, " %.*s",
1361 subname_len - skip, subname + skip);
1366 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1367 if (!strcmp(ctl->name, name)) {
1374 ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
1377 ctl->fw_name = wm_adsp_fw_text[dsp->fw];
1378 ctl->alg_region = *alg_region;
1379 ctl->name = kmemdup(name, strlen(name) + 1, GFP_KERNEL);
1386 ctl->ops.xget = wm_coeff_get;
1387 ctl->ops.xput = wm_coeff_put;
1392 ctl->offset = offset;
1394 ctl->cache = kzalloc(ctl->len, GFP_KERNEL);
1400 list_add(&ctl->list, &dsp->ctl_list);
1402 if (flags & WMFW_CTL_FLAG_SYS)
1405 ctl_work = kzalloc(sizeof(*ctl_work), GFP_KERNEL);
1411 ctl_work->dsp = dsp;
1412 ctl_work->ctl = ctl;
1413 INIT_WORK(&ctl_work->work, wm_adsp_ctl_work);
1414 schedule_work(&ctl_work->work);
1428 struct wm_coeff_parsed_alg {
1435 struct wm_coeff_parsed_coeff {
1445 static int wm_coeff_parse_string(int bytes, const u8 **pos, const u8 **str)
1454 length = le16_to_cpu(*((__le16 *)*pos));
1461 *str = *pos + bytes;
1463 *pos += ((length + bytes) + 3) & ~0x03;
1468 static int wm_coeff_parse_int(int bytes, const u8 **pos)
1474 val = le16_to_cpu(*((__le16 *)*pos));
1477 val = le32_to_cpu(*((__le32 *)*pos));
1488 static inline void wm_coeff_parse_alg(struct wm_adsp *dsp, const u8 **data,
1489 struct wm_coeff_parsed_alg *blk)
1491 const struct wmfw_adsp_alg_data *raw;
1493 switch (dsp->fw_ver) {
1496 raw = (const struct wmfw_adsp_alg_data *)*data;
1499 blk->id = le32_to_cpu(raw->id);
1500 blk->name = raw->name;
1501 blk->name_len = strlen(raw->name);
1502 blk->ncoeff = le32_to_cpu(raw->ncoeff);
1505 blk->id = wm_coeff_parse_int(sizeof(raw->id), data);
1506 blk->name_len = wm_coeff_parse_string(sizeof(u8), data,
1508 wm_coeff_parse_string(sizeof(u16), data, NULL);
1509 blk->ncoeff = wm_coeff_parse_int(sizeof(raw->ncoeff), data);
1513 adsp_dbg(dsp, "Algorithm ID: %#x\n", blk->id);
1514 adsp_dbg(dsp, "Algorithm name: %.*s\n", blk->name_len, blk->name);
1515 adsp_dbg(dsp, "# of coefficient descriptors: %#x\n", blk->ncoeff);
1518 static inline void wm_coeff_parse_coeff(struct wm_adsp *dsp, const u8 **data,
1519 struct wm_coeff_parsed_coeff *blk)
1521 const struct wmfw_adsp_coeff_data *raw;
1525 switch (dsp->fw_ver) {
1528 raw = (const struct wmfw_adsp_coeff_data *)*data;
1529 *data = *data + sizeof(raw->hdr) + le32_to_cpu(raw->hdr.size);
1531 blk->offset = le16_to_cpu(raw->hdr.offset);
1532 blk->mem_type = le16_to_cpu(raw->hdr.type);
1533 blk->name = raw->name;
1534 blk->name_len = strlen(raw->name);
1535 blk->ctl_type = le16_to_cpu(raw->ctl_type);
1536 blk->flags = le16_to_cpu(raw->flags);
1537 blk->len = le32_to_cpu(raw->len);
1541 blk->offset = wm_coeff_parse_int(sizeof(raw->hdr.offset), &tmp);
1542 blk->mem_type = wm_coeff_parse_int(sizeof(raw->hdr.type), &tmp);
1543 length = wm_coeff_parse_int(sizeof(raw->hdr.size), &tmp);
1544 blk->name_len = wm_coeff_parse_string(sizeof(u8), &tmp,
1546 wm_coeff_parse_string(sizeof(u8), &tmp, NULL);
1547 wm_coeff_parse_string(sizeof(u16), &tmp, NULL);
1548 blk->ctl_type = wm_coeff_parse_int(sizeof(raw->ctl_type), &tmp);
1549 blk->flags = wm_coeff_parse_int(sizeof(raw->flags), &tmp);
1550 blk->len = wm_coeff_parse_int(sizeof(raw->len), &tmp);
1552 *data = *data + sizeof(raw->hdr) + length;
1556 adsp_dbg(dsp, "\tCoefficient type: %#x\n", blk->mem_type);
1557 adsp_dbg(dsp, "\tCoefficient offset: %#x\n", blk->offset);
1558 adsp_dbg(dsp, "\tCoefficient name: %.*s\n", blk->name_len, blk->name);
1559 adsp_dbg(dsp, "\tCoefficient flags: %#x\n", blk->flags);
1560 adsp_dbg(dsp, "\tALSA control type: %#x\n", blk->ctl_type);
1561 adsp_dbg(dsp, "\tALSA control len: %#x\n", blk->len);
1564 static int wm_adsp_check_coeff_flags(struct wm_adsp *dsp,
1565 const struct wm_coeff_parsed_coeff *coeff_blk,
1566 unsigned int f_required,
1567 unsigned int f_illegal)
1569 if ((coeff_blk->flags & f_illegal) ||
1570 ((coeff_blk->flags & f_required) != f_required)) {
1571 adsp_err(dsp, "Illegal flags 0x%x for control type 0x%x\n",
1572 coeff_blk->flags, coeff_blk->ctl_type);
1579 static int wm_adsp_parse_coeff(struct wm_adsp *dsp,
1580 const struct wmfw_region *region)
1582 struct wm_adsp_alg_region alg_region = {};
1583 struct wm_coeff_parsed_alg alg_blk;
1584 struct wm_coeff_parsed_coeff coeff_blk;
1585 const u8 *data = region->data;
1588 wm_coeff_parse_alg(dsp, &data, &alg_blk);
1589 for (i = 0; i < alg_blk.ncoeff; i++) {
1590 wm_coeff_parse_coeff(dsp, &data, &coeff_blk);
1592 switch (coeff_blk.ctl_type) {
1593 case SNDRV_CTL_ELEM_TYPE_BYTES:
1595 case WMFW_CTL_TYPE_ACKED:
1596 if (coeff_blk.flags & WMFW_CTL_FLAG_SYS)
1597 continue; /* ignore */
1599 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1600 WMFW_CTL_FLAG_VOLATILE |
1601 WMFW_CTL_FLAG_WRITEABLE |
1602 WMFW_CTL_FLAG_READABLE,
1607 case WMFW_CTL_TYPE_HOSTEVENT:
1608 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1610 WMFW_CTL_FLAG_VOLATILE |
1611 WMFW_CTL_FLAG_WRITEABLE |
1612 WMFW_CTL_FLAG_READABLE,
1617 case WMFW_CTL_TYPE_HOST_BUFFER:
1618 ret = wm_adsp_check_coeff_flags(dsp, &coeff_blk,
1620 WMFW_CTL_FLAG_VOLATILE |
1621 WMFW_CTL_FLAG_READABLE,
1627 adsp_err(dsp, "Unknown control type: %d\n",
1628 coeff_blk.ctl_type);
1632 alg_region.type = coeff_blk.mem_type;
1633 alg_region.alg = alg_blk.id;
1635 ret = wm_adsp_create_control(dsp, &alg_region,
1641 coeff_blk.ctl_type);
1643 adsp_err(dsp, "Failed to create control: %.*s, %d\n",
1644 coeff_blk.name_len, coeff_blk.name, ret);
1650 static int wm_adsp_load(struct wm_adsp *dsp)
1652 LIST_HEAD(buf_list);
1653 const struct firmware *firmware;
1654 struct regmap *regmap = dsp->regmap;
1655 unsigned int pos = 0;
1656 const struct wmfw_header *header;
1657 const struct wmfw_adsp1_sizes *adsp1_sizes;
1658 const struct wmfw_adsp2_sizes *adsp2_sizes;
1659 const struct wmfw_footer *footer;
1660 const struct wmfw_region *region;
1661 const struct wm_adsp_region *mem;
1662 const char *region_name;
1663 char *file, *text = NULL;
1664 struct wm_adsp_buf *buf;
1667 int ret, offset, type, sizes;
1669 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
1673 snprintf(file, PAGE_SIZE, "%s-%s-%s.wmfw", dsp->part, dsp->fwf_name,
1674 wm_adsp_fw[dsp->fw].file);
1675 file[PAGE_SIZE - 1] = '\0';
1677 ret = request_firmware(&firmware, file, dsp->dev);
1679 adsp_err(dsp, "Failed to request '%s'\n", file);
1684 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1685 if (pos >= firmware->size) {
1686 adsp_err(dsp, "%s: file too short, %zu bytes\n",
1687 file, firmware->size);
1691 header = (void *)&firmware->data[0];
1693 if (memcmp(&header->magic[0], "WMFW", 4) != 0) {
1694 adsp_err(dsp, "%s: invalid magic\n", file);
1698 switch (header->ver) {
1700 adsp_warn(dsp, "%s: Depreciated file format %d\n",
1707 adsp_err(dsp, "%s: unknown file format %d\n",
1712 adsp_info(dsp, "Firmware version: %d\n", header->ver);
1713 dsp->fw_ver = header->ver;
1715 if (header->core != dsp->type) {
1716 adsp_err(dsp, "%s: invalid core %d != %d\n",
1717 file, header->core, dsp->type);
1721 switch (dsp->type) {
1723 pos = sizeof(*header) + sizeof(*adsp1_sizes) + sizeof(*footer);
1724 adsp1_sizes = (void *)&(header[1]);
1725 footer = (void *)&(adsp1_sizes[1]);
1726 sizes = sizeof(*adsp1_sizes);
1728 adsp_dbg(dsp, "%s: %d DM, %d PM, %d ZM\n",
1729 file, le32_to_cpu(adsp1_sizes->dm),
1730 le32_to_cpu(adsp1_sizes->pm),
1731 le32_to_cpu(adsp1_sizes->zm));
1735 pos = sizeof(*header) + sizeof(*adsp2_sizes) + sizeof(*footer);
1736 adsp2_sizes = (void *)&(header[1]);
1737 footer = (void *)&(adsp2_sizes[1]);
1738 sizes = sizeof(*adsp2_sizes);
1740 adsp_dbg(dsp, "%s: %d XM, %d YM %d PM, %d ZM\n",
1741 file, le32_to_cpu(adsp2_sizes->xm),
1742 le32_to_cpu(adsp2_sizes->ym),
1743 le32_to_cpu(adsp2_sizes->pm),
1744 le32_to_cpu(adsp2_sizes->zm));
1748 WARN(1, "Unknown DSP type");
1752 if (le32_to_cpu(header->len) != sizeof(*header) +
1753 sizes + sizeof(*footer)) {
1754 adsp_err(dsp, "%s: unexpected header length %d\n",
1755 file, le32_to_cpu(header->len));
1759 adsp_dbg(dsp, "%s: timestamp %llu\n", file,
1760 le64_to_cpu(footer->timestamp));
1762 while (pos < firmware->size &&
1763 sizeof(*region) < firmware->size - pos) {
1764 region = (void *)&(firmware->data[pos]);
1765 region_name = "Unknown";
1768 offset = le32_to_cpu(region->offset) & 0xffffff;
1769 type = be32_to_cpu(region->type) & 0xff;
1770 mem = wm_adsp_find_region(dsp, type);
1773 case WMFW_NAME_TEXT:
1774 region_name = "Firmware name";
1775 text = kzalloc(le32_to_cpu(region->len) + 1,
1778 case WMFW_ALGORITHM_DATA:
1779 region_name = "Algorithm";
1780 ret = wm_adsp_parse_coeff(dsp, region);
1784 case WMFW_INFO_TEXT:
1785 region_name = "Information";
1786 text = kzalloc(le32_to_cpu(region->len) + 1,
1790 region_name = "Absolute";
1798 region_name = wm_adsp_mem_region_name(type);
1799 reg = wm_adsp_region_to_reg(mem, offset);
1803 "%s.%d: Unknown region type %x at %d(%x)\n",
1804 file, regions, type, pos, pos);
1808 adsp_dbg(dsp, "%s.%d: %d bytes at %d in %s\n", file,
1809 regions, le32_to_cpu(region->len), offset,
1812 if (le32_to_cpu(region->len) >
1813 firmware->size - pos - sizeof(*region)) {
1815 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
1816 file, regions, region_name,
1817 le32_to_cpu(region->len), firmware->size);
1823 memcpy(text, region->data, le32_to_cpu(region->len));
1824 adsp_info(dsp, "%s: %s\n", file, text);
1830 buf = wm_adsp_buf_alloc(region->data,
1831 le32_to_cpu(region->len),
1834 adsp_err(dsp, "Out of memory\n");
1839 ret = regmap_raw_write_async(regmap, reg, buf->buf,
1840 le32_to_cpu(region->len));
1843 "%s.%d: Failed to write %d bytes at %d in %s: %d\n",
1845 le32_to_cpu(region->len), offset,
1851 pos += le32_to_cpu(region->len) + sizeof(*region);
1855 ret = regmap_async_complete(regmap);
1857 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
1861 if (pos > firmware->size)
1862 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
1863 file, regions, pos - firmware->size);
1865 wm_adsp_debugfs_save_wmfwname(dsp, file);
1868 regmap_async_complete(regmap);
1869 wm_adsp_buf_free(&buf_list);
1870 release_firmware(firmware);
1878 static void wm_adsp_ctl_fixup_base(struct wm_adsp *dsp,
1879 const struct wm_adsp_alg_region *alg_region)
1881 struct wm_coeff_ctl *ctl;
1883 list_for_each_entry(ctl, &dsp->ctl_list, list) {
1884 if (ctl->fw_name == wm_adsp_fw_text[dsp->fw] &&
1885 alg_region->alg == ctl->alg_region.alg &&
1886 alg_region->type == ctl->alg_region.type) {
1887 ctl->alg_region.base = alg_region->base;
1892 static void *wm_adsp_read_algs(struct wm_adsp *dsp, size_t n_algs,
1893 const struct wm_adsp_region *mem,
1894 unsigned int pos, unsigned int len)
1902 adsp_err(dsp, "No algorithms\n");
1903 return ERR_PTR(-EINVAL);
1906 if (n_algs > 1024) {
1907 adsp_err(dsp, "Algorithm count %zx excessive\n", n_algs);
1908 return ERR_PTR(-EINVAL);
1911 /* Read the terminator first to validate the length */
1912 reg = wm_adsp_region_to_reg(mem, pos + len);
1914 ret = regmap_raw_read(dsp->regmap, reg, &val, sizeof(val));
1916 adsp_err(dsp, "Failed to read algorithm list end: %d\n",
1918 return ERR_PTR(ret);
1921 if (be32_to_cpu(val) != 0xbedead)
1922 adsp_warn(dsp, "Algorithm list end %x 0x%x != 0xbedead\n",
1923 reg, be32_to_cpu(val));
1925 /* Convert length from DSP words to bytes */
1928 alg = kzalloc(len, GFP_KERNEL | GFP_DMA);
1930 return ERR_PTR(-ENOMEM);
1932 reg = wm_adsp_region_to_reg(mem, pos);
1934 ret = regmap_raw_read(dsp->regmap, reg, alg, len);
1936 adsp_err(dsp, "Failed to read algorithm list: %d\n", ret);
1938 return ERR_PTR(ret);
1944 static struct wm_adsp_alg_region *
1945 wm_adsp_find_alg_region(struct wm_adsp *dsp, int type, unsigned int id)
1947 struct wm_adsp_alg_region *alg_region;
1949 list_for_each_entry(alg_region, &dsp->alg_regions, list) {
1950 if (id == alg_region->alg && type == alg_region->type)
1957 static struct wm_adsp_alg_region *wm_adsp_create_region(struct wm_adsp *dsp,
1958 int type, __be32 id,
1961 struct wm_adsp_alg_region *alg_region;
1963 alg_region = kzalloc(sizeof(*alg_region), GFP_KERNEL);
1965 return ERR_PTR(-ENOMEM);
1967 alg_region->type = type;
1968 alg_region->alg = be32_to_cpu(id);
1969 alg_region->base = be32_to_cpu(base);
1971 list_add_tail(&alg_region->list, &dsp->alg_regions);
1973 if (dsp->fw_ver > 0)
1974 wm_adsp_ctl_fixup_base(dsp, alg_region);
1979 static void wm_adsp_free_alg_regions(struct wm_adsp *dsp)
1981 struct wm_adsp_alg_region *alg_region;
1983 while (!list_empty(&dsp->alg_regions)) {
1984 alg_region = list_first_entry(&dsp->alg_regions,
1985 struct wm_adsp_alg_region,
1987 list_del(&alg_region->list);
1992 static int wm_adsp1_setup_algs(struct wm_adsp *dsp)
1994 struct wmfw_adsp1_id_hdr adsp1_id;
1995 struct wmfw_adsp1_alg_hdr *adsp1_alg;
1996 struct wm_adsp_alg_region *alg_region;
1997 const struct wm_adsp_region *mem;
1998 unsigned int pos, len;
2002 mem = wm_adsp_find_region(dsp, WMFW_ADSP1_DM);
2006 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp1_id,
2009 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2014 n_algs = be32_to_cpu(adsp1_id.n_algs);
2015 dsp->fw_id = be32_to_cpu(adsp1_id.fw.id);
2016 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2018 (be32_to_cpu(adsp1_id.fw.ver) & 0xff0000) >> 16,
2019 (be32_to_cpu(adsp1_id.fw.ver) & 0xff00) >> 8,
2020 be32_to_cpu(adsp1_id.fw.ver) & 0xff,
2023 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2024 adsp1_id.fw.id, adsp1_id.zm);
2025 if (IS_ERR(alg_region))
2026 return PTR_ERR(alg_region);
2028 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2029 adsp1_id.fw.id, adsp1_id.dm);
2030 if (IS_ERR(alg_region))
2031 return PTR_ERR(alg_region);
2033 /* Calculate offset and length in DSP words */
2034 pos = sizeof(adsp1_id) / sizeof(u32);
2035 len = (sizeof(*adsp1_alg) * n_algs) / sizeof(u32);
2037 adsp1_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2038 if (IS_ERR(adsp1_alg))
2039 return PTR_ERR(adsp1_alg);
2041 for (i = 0; i < n_algs; i++) {
2042 adsp_info(dsp, "%d: ID %x v%d.%d.%d DM@%x ZM@%x\n",
2043 i, be32_to_cpu(adsp1_alg[i].alg.id),
2044 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff0000) >> 16,
2045 (be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff00) >> 8,
2046 be32_to_cpu(adsp1_alg[i].alg.ver) & 0xff,
2047 be32_to_cpu(adsp1_alg[i].dm),
2048 be32_to_cpu(adsp1_alg[i].zm));
2050 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_DM,
2051 adsp1_alg[i].alg.id,
2053 if (IS_ERR(alg_region)) {
2054 ret = PTR_ERR(alg_region);
2057 if (dsp->fw_ver == 0) {
2058 if (i + 1 < n_algs) {
2059 len = be32_to_cpu(adsp1_alg[i + 1].dm);
2060 len -= be32_to_cpu(adsp1_alg[i].dm);
2062 wm_adsp_create_control(dsp, alg_region, 0,
2064 SNDRV_CTL_ELEM_TYPE_BYTES);
2066 adsp_warn(dsp, "Missing length info for region DM with ID %x\n",
2067 be32_to_cpu(adsp1_alg[i].alg.id));
2071 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP1_ZM,
2072 adsp1_alg[i].alg.id,
2074 if (IS_ERR(alg_region)) {
2075 ret = PTR_ERR(alg_region);
2078 if (dsp->fw_ver == 0) {
2079 if (i + 1 < n_algs) {
2080 len = be32_to_cpu(adsp1_alg[i + 1].zm);
2081 len -= be32_to_cpu(adsp1_alg[i].zm);
2083 wm_adsp_create_control(dsp, alg_region, 0,
2085 SNDRV_CTL_ELEM_TYPE_BYTES);
2087 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2088 be32_to_cpu(adsp1_alg[i].alg.id));
2098 static int wm_adsp2_setup_algs(struct wm_adsp *dsp)
2100 struct wmfw_adsp2_id_hdr adsp2_id;
2101 struct wmfw_adsp2_alg_hdr *adsp2_alg;
2102 struct wm_adsp_alg_region *alg_region;
2103 const struct wm_adsp_region *mem;
2104 unsigned int pos, len;
2108 mem = wm_adsp_find_region(dsp, WMFW_ADSP2_XM);
2112 ret = regmap_raw_read(dsp->regmap, mem->base, &adsp2_id,
2115 adsp_err(dsp, "Failed to read algorithm info: %d\n",
2120 n_algs = be32_to_cpu(adsp2_id.n_algs);
2121 dsp->fw_id = be32_to_cpu(adsp2_id.fw.id);
2122 dsp->fw_id_version = be32_to_cpu(adsp2_id.fw.ver);
2123 adsp_info(dsp, "Firmware: %x v%d.%d.%d, %zu algorithms\n",
2125 (dsp->fw_id_version & 0xff0000) >> 16,
2126 (dsp->fw_id_version & 0xff00) >> 8,
2127 dsp->fw_id_version & 0xff,
2130 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2131 adsp2_id.fw.id, adsp2_id.xm);
2132 if (IS_ERR(alg_region))
2133 return PTR_ERR(alg_region);
2135 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2136 adsp2_id.fw.id, adsp2_id.ym);
2137 if (IS_ERR(alg_region))
2138 return PTR_ERR(alg_region);
2140 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2141 adsp2_id.fw.id, adsp2_id.zm);
2142 if (IS_ERR(alg_region))
2143 return PTR_ERR(alg_region);
2145 /* Calculate offset and length in DSP words */
2146 pos = sizeof(adsp2_id) / sizeof(u32);
2147 len = (sizeof(*adsp2_alg) * n_algs) / sizeof(u32);
2149 adsp2_alg = wm_adsp_read_algs(dsp, n_algs, mem, pos, len);
2150 if (IS_ERR(adsp2_alg))
2151 return PTR_ERR(adsp2_alg);
2153 for (i = 0; i < n_algs; i++) {
2155 "%d: ID %x v%d.%d.%d XM@%x YM@%x ZM@%x\n",
2156 i, be32_to_cpu(adsp2_alg[i].alg.id),
2157 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff0000) >> 16,
2158 (be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff00) >> 8,
2159 be32_to_cpu(adsp2_alg[i].alg.ver) & 0xff,
2160 be32_to_cpu(adsp2_alg[i].xm),
2161 be32_to_cpu(adsp2_alg[i].ym),
2162 be32_to_cpu(adsp2_alg[i].zm));
2164 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_XM,
2165 adsp2_alg[i].alg.id,
2167 if (IS_ERR(alg_region)) {
2168 ret = PTR_ERR(alg_region);
2171 if (dsp->fw_ver == 0) {
2172 if (i + 1 < n_algs) {
2173 len = be32_to_cpu(adsp2_alg[i + 1].xm);
2174 len -= be32_to_cpu(adsp2_alg[i].xm);
2176 wm_adsp_create_control(dsp, alg_region, 0,
2178 SNDRV_CTL_ELEM_TYPE_BYTES);
2180 adsp_warn(dsp, "Missing length info for region XM with ID %x\n",
2181 be32_to_cpu(adsp2_alg[i].alg.id));
2185 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_YM,
2186 adsp2_alg[i].alg.id,
2188 if (IS_ERR(alg_region)) {
2189 ret = PTR_ERR(alg_region);
2192 if (dsp->fw_ver == 0) {
2193 if (i + 1 < n_algs) {
2194 len = be32_to_cpu(adsp2_alg[i + 1].ym);
2195 len -= be32_to_cpu(adsp2_alg[i].ym);
2197 wm_adsp_create_control(dsp, alg_region, 0,
2199 SNDRV_CTL_ELEM_TYPE_BYTES);
2201 adsp_warn(dsp, "Missing length info for region YM with ID %x\n",
2202 be32_to_cpu(adsp2_alg[i].alg.id));
2206 alg_region = wm_adsp_create_region(dsp, WMFW_ADSP2_ZM,
2207 adsp2_alg[i].alg.id,
2209 if (IS_ERR(alg_region)) {
2210 ret = PTR_ERR(alg_region);
2213 if (dsp->fw_ver == 0) {
2214 if (i + 1 < n_algs) {
2215 len = be32_to_cpu(adsp2_alg[i + 1].zm);
2216 len -= be32_to_cpu(adsp2_alg[i].zm);
2218 wm_adsp_create_control(dsp, alg_region, 0,
2220 SNDRV_CTL_ELEM_TYPE_BYTES);
2222 adsp_warn(dsp, "Missing length info for region ZM with ID %x\n",
2223 be32_to_cpu(adsp2_alg[i].alg.id));
2233 static int wm_adsp_load_coeff(struct wm_adsp *dsp)
2235 LIST_HEAD(buf_list);
2236 struct regmap *regmap = dsp->regmap;
2237 struct wmfw_coeff_hdr *hdr;
2238 struct wmfw_coeff_item *blk;
2239 const struct firmware *firmware;
2240 const struct wm_adsp_region *mem;
2241 struct wm_adsp_alg_region *alg_region;
2242 const char *region_name;
2243 int ret, pos, blocks, type, offset, reg;
2245 struct wm_adsp_buf *buf;
2247 file = kzalloc(PAGE_SIZE, GFP_KERNEL);
2251 snprintf(file, PAGE_SIZE, "%s-%s-%s.bin", dsp->part, dsp->fwf_name,
2252 wm_adsp_fw[dsp->fw].file);
2253 file[PAGE_SIZE - 1] = '\0';
2255 ret = request_firmware(&firmware, file, dsp->dev);
2257 adsp_warn(dsp, "Failed to request '%s'\n", file);
2263 if (sizeof(*hdr) >= firmware->size) {
2264 adsp_err(dsp, "%s: file too short, %zu bytes\n",
2265 file, firmware->size);
2269 hdr = (void *)&firmware->data[0];
2270 if (memcmp(hdr->magic, "WMDR", 4) != 0) {
2271 adsp_err(dsp, "%s: invalid magic\n", file);
2275 switch (be32_to_cpu(hdr->rev) & 0xff) {
2279 adsp_err(dsp, "%s: Unsupported coefficient file format %d\n",
2280 file, be32_to_cpu(hdr->rev) & 0xff);
2285 adsp_dbg(dsp, "%s: v%d.%d.%d\n", file,
2286 (le32_to_cpu(hdr->ver) >> 16) & 0xff,
2287 (le32_to_cpu(hdr->ver) >> 8) & 0xff,
2288 le32_to_cpu(hdr->ver) & 0xff);
2290 pos = le32_to_cpu(hdr->len);
2293 while (pos < firmware->size &&
2294 sizeof(*blk) < firmware->size - pos) {
2295 blk = (void *)(&firmware->data[pos]);
2297 type = le16_to_cpu(blk->type);
2298 offset = le16_to_cpu(blk->offset);
2300 adsp_dbg(dsp, "%s.%d: %x v%d.%d.%d\n",
2301 file, blocks, le32_to_cpu(blk->id),
2302 (le32_to_cpu(blk->ver) >> 16) & 0xff,
2303 (le32_to_cpu(blk->ver) >> 8) & 0xff,
2304 le32_to_cpu(blk->ver) & 0xff);
2305 adsp_dbg(dsp, "%s.%d: %d bytes at 0x%x in %x\n",
2306 file, blocks, le32_to_cpu(blk->len), offset, type);
2309 region_name = "Unknown";
2311 case (WMFW_NAME_TEXT << 8):
2312 case (WMFW_INFO_TEXT << 8):
2314 case (WMFW_ABSOLUTE << 8):
2316 * Old files may use this for global
2319 if (le32_to_cpu(blk->id) == dsp->fw_id &&
2321 region_name = "global coefficients";
2322 mem = wm_adsp_find_region(dsp, type);
2324 adsp_err(dsp, "No ZM\n");
2327 reg = wm_adsp_region_to_reg(mem, 0);
2330 region_name = "register";
2339 adsp_dbg(dsp, "%s.%d: %d bytes in %x for %x\n",
2340 file, blocks, le32_to_cpu(blk->len),
2341 type, le32_to_cpu(blk->id));
2343 mem = wm_adsp_find_region(dsp, type);
2345 adsp_err(dsp, "No base for region %x\n", type);
2349 alg_region = wm_adsp_find_alg_region(dsp, type,
2350 le32_to_cpu(blk->id));
2352 reg = alg_region->base;
2353 reg = wm_adsp_region_to_reg(mem, reg);
2356 adsp_err(dsp, "No %x for algorithm %x\n",
2357 type, le32_to_cpu(blk->id));
2362 adsp_err(dsp, "%s.%d: Unknown region type %x at %d\n",
2363 file, blocks, type, pos);
2368 if (le32_to_cpu(blk->len) >
2369 firmware->size - pos - sizeof(*blk)) {
2371 "%s.%d: %s region len %d bytes exceeds file length %zu\n",
2372 file, blocks, region_name,
2373 le32_to_cpu(blk->len),
2379 buf = wm_adsp_buf_alloc(blk->data,
2380 le32_to_cpu(blk->len),
2383 adsp_err(dsp, "Out of memory\n");
2388 adsp_dbg(dsp, "%s.%d: Writing %d bytes at %x\n",
2389 file, blocks, le32_to_cpu(blk->len),
2391 ret = regmap_raw_write_async(regmap, reg, buf->buf,
2392 le32_to_cpu(blk->len));
2395 "%s.%d: Failed to write to %x in %s: %d\n",
2396 file, blocks, reg, region_name, ret);
2400 pos += (le32_to_cpu(blk->len) + sizeof(*blk) + 3) & ~0x03;
2404 ret = regmap_async_complete(regmap);
2406 adsp_err(dsp, "Failed to complete async write: %d\n", ret);
2408 if (pos > firmware->size)
2409 adsp_warn(dsp, "%s.%d: %zu bytes at end of file\n",
2410 file, blocks, pos - firmware->size);
2412 wm_adsp_debugfs_save_binname(dsp, file);
2415 regmap_async_complete(regmap);
2416 release_firmware(firmware);
2417 wm_adsp_buf_free(&buf_list);
2423 static int wm_adsp_create_name(struct wm_adsp *dsp)
2428 dsp->name = devm_kasprintf(dsp->dev, GFP_KERNEL, "DSP%d",
2434 if (!dsp->fwf_name) {
2435 p = devm_kstrdup(dsp->dev, dsp->name, GFP_KERNEL);
2440 for (; *p != 0; ++p)
2447 static int wm_adsp_common_init(struct wm_adsp *dsp)
2451 ret = wm_adsp_create_name(dsp);
2455 INIT_LIST_HEAD(&dsp->alg_regions);
2456 INIT_LIST_HEAD(&dsp->ctl_list);
2457 INIT_LIST_HEAD(&dsp->compr_list);
2458 INIT_LIST_HEAD(&dsp->buffer_list);
2460 mutex_init(&dsp->pwr_lock);
2465 int wm_adsp1_init(struct wm_adsp *dsp)
2467 return wm_adsp_common_init(dsp);
2469 EXPORT_SYMBOL_GPL(wm_adsp1_init);
2471 int wm_adsp1_event(struct snd_soc_dapm_widget *w,
2472 struct snd_kcontrol *kcontrol,
2475 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2476 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2477 struct wm_adsp *dsp = &dsps[w->shift];
2478 struct wm_coeff_ctl *ctl;
2482 dsp->component = component;
2484 mutex_lock(&dsp->pwr_lock);
2487 case SND_SOC_DAPM_POST_PMU:
2488 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2489 ADSP1_SYS_ENA, ADSP1_SYS_ENA);
2492 * For simplicity set the DSP clock rate to be the
2493 * SYSCLK rate rather than making it configurable.
2495 if (dsp->sysclk_reg) {
2496 ret = regmap_read(dsp->regmap, dsp->sysclk_reg, &val);
2498 adsp_err(dsp, "Failed to read SYSCLK state: %d\n",
2503 val = (val & dsp->sysclk_mask) >> dsp->sysclk_shift;
2505 ret = regmap_update_bits(dsp->regmap,
2506 dsp->base + ADSP1_CONTROL_31,
2507 ADSP1_CLK_SEL_MASK, val);
2509 adsp_err(dsp, "Failed to set clock rate: %d\n",
2515 ret = wm_adsp_load(dsp);
2519 ret = wm_adsp1_setup_algs(dsp);
2523 ret = wm_adsp_load_coeff(dsp);
2527 /* Initialize caches for enabled and unset controls */
2528 ret = wm_coeff_init_control_caches(dsp);
2532 /* Sync set controls */
2533 ret = wm_coeff_sync_controls(dsp);
2539 /* Start the core running */
2540 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2541 ADSP1_CORE_ENA | ADSP1_START,
2542 ADSP1_CORE_ENA | ADSP1_START);
2544 dsp->running = true;
2547 case SND_SOC_DAPM_PRE_PMD:
2548 dsp->running = false;
2549 dsp->booted = false;
2552 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2553 ADSP1_CORE_ENA | ADSP1_START, 0);
2555 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_19,
2556 ADSP1_WDMA_BUFFER_LENGTH_MASK, 0);
2558 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2561 list_for_each_entry(ctl, &dsp->ctl_list, list)
2565 wm_adsp_free_alg_regions(dsp);
2572 mutex_unlock(&dsp->pwr_lock);
2577 regmap_update_bits(dsp->regmap, dsp->base + ADSP1_CONTROL_30,
2580 mutex_unlock(&dsp->pwr_lock);
2584 EXPORT_SYMBOL_GPL(wm_adsp1_event);
2586 static int wm_adsp2_ena(struct wm_adsp *dsp)
2593 ret = regmap_update_bits_async(dsp->regmap,
2594 dsp->base + ADSP2_CONTROL,
2595 ADSP2_SYS_ENA, ADSP2_SYS_ENA);
2603 /* Wait for the RAM to start, should be near instantaneous */
2604 for (count = 0; count < 10; ++count) {
2605 ret = regmap_read(dsp->regmap, dsp->base + ADSP2_STATUS1, &val);
2609 if (val & ADSP2_RAM_RDY)
2612 usleep_range(250, 500);
2615 if (!(val & ADSP2_RAM_RDY)) {
2616 adsp_err(dsp, "Failed to start DSP RAM\n");
2620 adsp_dbg(dsp, "RAM ready after %d polls\n", count);
2625 static void wm_adsp2_boot_work(struct work_struct *work)
2627 struct wm_adsp *dsp = container_of(work,
2632 mutex_lock(&dsp->pwr_lock);
2634 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2635 ADSP2_MEM_ENA, ADSP2_MEM_ENA);
2639 ret = wm_adsp2_ena(dsp);
2643 ret = wm_adsp_load(dsp);
2647 ret = wm_adsp2_setup_algs(dsp);
2651 ret = wm_adsp_load_coeff(dsp);
2655 /* Initialize caches for enabled and unset controls */
2656 ret = wm_coeff_init_control_caches(dsp);
2662 /* Turn DSP back off until we are ready to run */
2663 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2674 mutex_unlock(&dsp->pwr_lock);
2679 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2680 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2682 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2685 mutex_unlock(&dsp->pwr_lock);
2688 static void wm_adsp2_set_dspclk(struct wm_adsp *dsp, unsigned int freq)
2694 ret = regmap_update_bits_async(dsp->regmap,
2695 dsp->base + ADSP2_CLOCKING,
2697 freq << ADSP2_CLK_SEL_SHIFT);
2699 adsp_err(dsp, "Failed to set clock rate: %d\n", ret);
2704 /* clock is handled by parent codec driver */
2709 int wm_adsp2_preloader_get(struct snd_kcontrol *kcontrol,
2710 struct snd_ctl_elem_value *ucontrol)
2712 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2713 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2714 struct soc_mixer_control *mc =
2715 (struct soc_mixer_control *)kcontrol->private_value;
2716 struct wm_adsp *dsp = &dsps[mc->shift - 1];
2718 ucontrol->value.integer.value[0] = dsp->preloaded;
2722 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_get);
2724 int wm_adsp2_preloader_put(struct snd_kcontrol *kcontrol,
2725 struct snd_ctl_elem_value *ucontrol)
2727 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2728 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2729 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2730 struct soc_mixer_control *mc =
2731 (struct soc_mixer_control *)kcontrol->private_value;
2732 struct wm_adsp *dsp = &dsps[mc->shift - 1];
2735 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
2737 dsp->preloaded = ucontrol->value.integer.value[0];
2739 if (ucontrol->value.integer.value[0])
2740 snd_soc_component_force_enable_pin(component, preload);
2742 snd_soc_component_disable_pin(component, preload);
2744 snd_soc_dapm_sync(dapm);
2746 flush_work(&dsp->boot_work);
2750 EXPORT_SYMBOL_GPL(wm_adsp2_preloader_put);
2752 static void wm_adsp_stop_watchdog(struct wm_adsp *dsp)
2759 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_WATCHDOG,
2760 ADSP2_WDT_ENA_MASK, 0);
2764 int wm_adsp2_early_event(struct snd_soc_dapm_widget *w,
2765 struct snd_kcontrol *kcontrol, int event,
2768 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2769 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2770 struct wm_adsp *dsp = &dsps[w->shift];
2771 struct wm_coeff_ctl *ctl;
2774 case SND_SOC_DAPM_PRE_PMU:
2775 wm_adsp2_set_dspclk(dsp, freq);
2776 queue_work(system_unbound_wq, &dsp->boot_work);
2778 case SND_SOC_DAPM_PRE_PMD:
2779 mutex_lock(&dsp->pwr_lock);
2781 wm_adsp_debugfs_clear(dsp);
2784 dsp->fw_id_version = 0;
2786 dsp->booted = false;
2788 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2791 list_for_each_entry(ctl, &dsp->ctl_list, list)
2794 wm_adsp_free_alg_regions(dsp);
2796 mutex_unlock(&dsp->pwr_lock);
2798 adsp_dbg(dsp, "Shutdown complete\n");
2806 EXPORT_SYMBOL_GPL(wm_adsp2_early_event);
2808 int wm_adsp2_event(struct snd_soc_dapm_widget *w,
2809 struct snd_kcontrol *kcontrol, int event)
2811 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2812 struct wm_adsp *dsps = snd_soc_component_get_drvdata(component);
2813 struct wm_adsp *dsp = &dsps[w->shift];
2817 case SND_SOC_DAPM_POST_PMU:
2818 flush_work(&dsp->boot_work);
2820 mutex_lock(&dsp->pwr_lock);
2827 ret = wm_adsp2_ena(dsp);
2831 /* Sync set controls */
2832 ret = wm_coeff_sync_controls(dsp);
2836 wm_adsp2_lock(dsp, dsp->lock_regions);
2838 ret = regmap_update_bits(dsp->regmap,
2839 dsp->base + ADSP2_CONTROL,
2840 ADSP2_CORE_ENA | ADSP2_START,
2841 ADSP2_CORE_ENA | ADSP2_START);
2845 if (wm_adsp_fw[dsp->fw].num_caps != 0) {
2846 ret = wm_adsp_buffer_init(dsp);
2851 dsp->running = true;
2853 mutex_unlock(&dsp->pwr_lock);
2857 case SND_SOC_DAPM_PRE_PMD:
2858 /* Tell the firmware to cleanup */
2859 wm_adsp_signal_event_controls(dsp, WM_ADSP_FW_EVENT_SHUTDOWN);
2861 wm_adsp_stop_watchdog(dsp);
2863 /* Log firmware state, it can be useful for analysis */
2866 wm_adsp2_show_fw_status(dsp);
2869 wm_adsp2v2_show_fw_status(dsp);
2873 mutex_lock(&dsp->pwr_lock);
2875 dsp->running = false;
2877 regmap_update_bits(dsp->regmap,
2878 dsp->base + ADSP2_CONTROL,
2879 ADSP2_CORE_ENA | ADSP2_START, 0);
2881 /* Make sure DMAs are quiesced */
2884 regmap_write(dsp->regmap,
2885 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2886 regmap_write(dsp->regmap,
2887 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2888 regmap_write(dsp->regmap,
2889 dsp->base + ADSP2_WDMA_CONFIG_2, 0);
2891 regmap_update_bits(dsp->regmap,
2892 dsp->base + ADSP2_CONTROL,
2896 regmap_write(dsp->regmap,
2897 dsp->base + ADSP2_RDMA_CONFIG_1, 0);
2898 regmap_write(dsp->regmap,
2899 dsp->base + ADSP2_WDMA_CONFIG_1, 0);
2900 regmap_write(dsp->regmap,
2901 dsp->base + ADSP2V2_WDMA_CONFIG_2, 0);
2905 if (wm_adsp_fw[dsp->fw].num_caps != 0)
2906 wm_adsp_buffer_free(dsp);
2908 mutex_unlock(&dsp->pwr_lock);
2910 adsp_dbg(dsp, "Execution stopped\n");
2919 regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2920 ADSP2_SYS_ENA | ADSP2_CORE_ENA | ADSP2_START, 0);
2921 mutex_unlock(&dsp->pwr_lock);
2924 EXPORT_SYMBOL_GPL(wm_adsp2_event);
2926 int wm_adsp2_component_probe(struct wm_adsp *dsp, struct snd_soc_component *component)
2930 snprintf(preload, ARRAY_SIZE(preload), "%s Preload", dsp->name);
2931 snd_soc_component_disable_pin(component, preload);
2933 wm_adsp2_init_debugfs(dsp, component);
2935 dsp->component = component;
2939 EXPORT_SYMBOL_GPL(wm_adsp2_component_probe);
2941 int wm_adsp2_component_remove(struct wm_adsp *dsp, struct snd_soc_component *component)
2943 wm_adsp2_cleanup_debugfs(dsp);
2947 EXPORT_SYMBOL_GPL(wm_adsp2_component_remove);
2949 int wm_adsp2_init(struct wm_adsp *dsp)
2953 ret = wm_adsp_common_init(dsp);
2960 * Disable the DSP memory by default when in reset for a small
2963 ret = regmap_update_bits(dsp->regmap, dsp->base + ADSP2_CONTROL,
2967 "Failed to clear memory retention: %d\n", ret);
2975 INIT_WORK(&dsp->boot_work, wm_adsp2_boot_work);
2979 EXPORT_SYMBOL_GPL(wm_adsp2_init);
2981 void wm_adsp2_remove(struct wm_adsp *dsp)
2983 struct wm_coeff_ctl *ctl;
2985 while (!list_empty(&dsp->ctl_list)) {
2986 ctl = list_first_entry(&dsp->ctl_list, struct wm_coeff_ctl,
2988 list_del(&ctl->list);
2989 wm_adsp_free_ctl_blk(ctl);
2992 EXPORT_SYMBOL_GPL(wm_adsp2_remove);
2994 static inline int wm_adsp_compr_attached(struct wm_adsp_compr *compr)
2996 return compr->buf != NULL;
2999 static int wm_adsp_compr_attach(struct wm_adsp_compr *compr)
3001 struct wm_adsp_compr_buf *buf = NULL, *tmp;
3003 list_for_each_entry(tmp, &compr->dsp->buffer_list, list) {
3004 if (!tmp->name || !strcmp(compr->name, tmp->name)) {
3014 compr->buf->compr = compr;
3019 static void wm_adsp_compr_detach(struct wm_adsp_compr *compr)
3024 /* Wake the poll so it can see buffer is no longer attached */
3026 snd_compr_fragment_elapsed(compr->stream);
3028 if (wm_adsp_compr_attached(compr)) {
3029 compr->buf->compr = NULL;
3034 int wm_adsp_compr_open(struct wm_adsp *dsp, struct snd_compr_stream *stream)
3036 struct wm_adsp_compr *compr, *tmp;
3037 struct snd_soc_pcm_runtime *rtd = stream->private_data;
3040 mutex_lock(&dsp->pwr_lock);
3042 if (wm_adsp_fw[dsp->fw].num_caps == 0) {
3043 adsp_err(dsp, "%s: Firmware does not support compressed API\n",
3044 rtd->codec_dai->name);
3049 if (wm_adsp_fw[dsp->fw].compr_direction != stream->direction) {
3050 adsp_err(dsp, "%s: Firmware does not support stream direction\n",
3051 rtd->codec_dai->name);
3056 list_for_each_entry(tmp, &dsp->compr_list, list) {
3057 if (!strcmp(tmp->name, rtd->codec_dai->name)) {
3058 adsp_err(dsp, "%s: Only a single stream supported per dai\n",
3059 rtd->codec_dai->name);
3065 compr = kzalloc(sizeof(*compr), GFP_KERNEL);
3072 compr->stream = stream;
3073 compr->name = rtd->codec_dai->name;
3075 list_add_tail(&compr->list, &dsp->compr_list);
3077 stream->runtime->private_data = compr;
3080 mutex_unlock(&dsp->pwr_lock);
3084 EXPORT_SYMBOL_GPL(wm_adsp_compr_open);
3086 int wm_adsp_compr_free(struct snd_compr_stream *stream)
3088 struct wm_adsp_compr *compr = stream->runtime->private_data;
3089 struct wm_adsp *dsp = compr->dsp;
3091 mutex_lock(&dsp->pwr_lock);
3093 wm_adsp_compr_detach(compr);
3094 list_del(&compr->list);
3096 kfree(compr->raw_buf);
3099 mutex_unlock(&dsp->pwr_lock);
3103 EXPORT_SYMBOL_GPL(wm_adsp_compr_free);
3105 static int wm_adsp_compr_check_params(struct snd_compr_stream *stream,
3106 struct snd_compr_params *params)
3108 struct wm_adsp_compr *compr = stream->runtime->private_data;
3109 struct wm_adsp *dsp = compr->dsp;
3110 const struct wm_adsp_fw_caps *caps;
3111 const struct snd_codec_desc *desc;
3114 if (params->buffer.fragment_size < WM_ADSP_MIN_FRAGMENT_SIZE ||
3115 params->buffer.fragment_size > WM_ADSP_MAX_FRAGMENT_SIZE ||
3116 params->buffer.fragments < WM_ADSP_MIN_FRAGMENTS ||
3117 params->buffer.fragments > WM_ADSP_MAX_FRAGMENTS ||
3118 params->buffer.fragment_size % WM_ADSP_DATA_WORD_SIZE) {
3119 compr_err(compr, "Invalid buffer fragsize=%d fragments=%d\n",
3120 params->buffer.fragment_size,
3121 params->buffer.fragments);
3126 for (i = 0; i < wm_adsp_fw[dsp->fw].num_caps; i++) {
3127 caps = &wm_adsp_fw[dsp->fw].caps[i];
3130 if (caps->id != params->codec.id)
3133 if (stream->direction == SND_COMPRESS_PLAYBACK) {
3134 if (desc->max_ch < params->codec.ch_out)
3137 if (desc->max_ch < params->codec.ch_in)
3141 if (!(desc->formats & (1 << params->codec.format)))
3144 for (j = 0; j < desc->num_sample_rates; ++j)
3145 if (desc->sample_rates[j] == params->codec.sample_rate)
3149 compr_err(compr, "Invalid params id=%u ch=%u,%u rate=%u fmt=%u\n",
3150 params->codec.id, params->codec.ch_in, params->codec.ch_out,
3151 params->codec.sample_rate, params->codec.format);
3155 static inline unsigned int wm_adsp_compr_frag_words(struct wm_adsp_compr *compr)
3157 return compr->size.fragment_size / WM_ADSP_DATA_WORD_SIZE;
3160 int wm_adsp_compr_set_params(struct snd_compr_stream *stream,
3161 struct snd_compr_params *params)
3163 struct wm_adsp_compr *compr = stream->runtime->private_data;
3167 ret = wm_adsp_compr_check_params(stream, params);
3171 compr->size = params->buffer;
3173 compr_dbg(compr, "fragment_size=%d fragments=%d\n",
3174 compr->size.fragment_size, compr->size.fragments);
3176 size = wm_adsp_compr_frag_words(compr) * sizeof(*compr->raw_buf);
3177 compr->raw_buf = kmalloc(size, GFP_DMA | GFP_KERNEL);
3178 if (!compr->raw_buf)
3181 compr->sample_rate = params->codec.sample_rate;
3185 EXPORT_SYMBOL_GPL(wm_adsp_compr_set_params);
3187 int wm_adsp_compr_get_caps(struct snd_compr_stream *stream,
3188 struct snd_compr_caps *caps)
3190 struct wm_adsp_compr *compr = stream->runtime->private_data;
3191 int fw = compr->dsp->fw;
3194 if (wm_adsp_fw[fw].caps) {
3195 for (i = 0; i < wm_adsp_fw[fw].num_caps; i++)
3196 caps->codecs[i] = wm_adsp_fw[fw].caps[i].id;
3198 caps->num_codecs = i;
3199 caps->direction = wm_adsp_fw[fw].compr_direction;
3201 caps->min_fragment_size = WM_ADSP_MIN_FRAGMENT_SIZE;
3202 caps->max_fragment_size = WM_ADSP_MAX_FRAGMENT_SIZE;
3203 caps->min_fragments = WM_ADSP_MIN_FRAGMENTS;
3204 caps->max_fragments = WM_ADSP_MAX_FRAGMENTS;
3209 EXPORT_SYMBOL_GPL(wm_adsp_compr_get_caps);
3211 static int wm_adsp_read_data_block(struct wm_adsp *dsp, int mem_type,
3212 unsigned int mem_addr,
3213 unsigned int num_words, u32 *data)
3215 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3216 unsigned int i, reg;
3222 reg = wm_adsp_region_to_reg(mem, mem_addr);
3224 ret = regmap_raw_read(dsp->regmap, reg, data,
3225 sizeof(*data) * num_words);
3229 for (i = 0; i < num_words; ++i)
3230 data[i] = be32_to_cpu(data[i]) & 0x00ffffffu;
3235 static inline int wm_adsp_read_data_word(struct wm_adsp *dsp, int mem_type,
3236 unsigned int mem_addr, u32 *data)
3238 return wm_adsp_read_data_block(dsp, mem_type, mem_addr, 1, data);
3241 static int wm_adsp_write_data_word(struct wm_adsp *dsp, int mem_type,
3242 unsigned int mem_addr, u32 data)
3244 struct wm_adsp_region const *mem = wm_adsp_find_region(dsp, mem_type);
3250 reg = wm_adsp_region_to_reg(mem, mem_addr);
3252 data = cpu_to_be32(data & 0x00ffffffu);
3254 return regmap_raw_write(dsp->regmap, reg, &data, sizeof(data));
3257 static inline int wm_adsp_buffer_read(struct wm_adsp_compr_buf *buf,
3258 unsigned int field_offset, u32 *data)
3260 return wm_adsp_read_data_word(buf->dsp, buf->host_buf_mem_type,
3261 buf->host_buf_ptr + field_offset, data);
3264 static inline int wm_adsp_buffer_write(struct wm_adsp_compr_buf *buf,
3265 unsigned int field_offset, u32 data)
3267 return wm_adsp_write_data_word(buf->dsp, buf->host_buf_mem_type,
3268 buf->host_buf_ptr + field_offset, data);
3271 static void wm_adsp_remove_padding(u32 *buf, int nwords, int data_word_size)
3273 u8 *pack_in = (u8 *)buf;
3274 u8 *pack_out = (u8 *)buf;
3277 /* Remove the padding bytes from the data read from the DSP */
3278 for (i = 0; i < nwords; i++) {
3279 for (j = 0; j < data_word_size; j++)
3280 *pack_out++ = *pack_in++;
3282 pack_in += sizeof(*buf) - data_word_size;
3286 static int wm_adsp_buffer_populate(struct wm_adsp_compr_buf *buf)
3288 const struct wm_adsp_fw_caps *caps = wm_adsp_fw[buf->dsp->fw].caps;
3289 struct wm_adsp_buffer_region *region;
3293 buf->regions = kcalloc(caps->num_regions, sizeof(*buf->regions),
3298 for (i = 0; i < caps->num_regions; ++i) {
3299 region = &buf->regions[i];
3301 region->offset = offset;
3302 region->mem_type = caps->region_defs[i].mem_type;
3304 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].base_offset,
3305 ®ion->base_addr);
3309 ret = wm_adsp_buffer_read(buf, caps->region_defs[i].size_offset,
3314 region->cumulative_size = offset;
3317 "region=%d type=%d base=%08x off=%08x size=%08x\n",
3318 i, region->mem_type, region->base_addr,
3319 region->offset, region->cumulative_size);
3325 static void wm_adsp_buffer_clear(struct wm_adsp_compr_buf *buf)
3327 buf->irq_count = 0xFFFFFFFF;
3328 buf->read_index = -1;
3332 static struct wm_adsp_compr_buf *wm_adsp_buffer_alloc(struct wm_adsp *dsp)
3334 struct wm_adsp_compr_buf *buf;
3336 buf = kzalloc(sizeof(*buf), GFP_KERNEL);
3342 wm_adsp_buffer_clear(buf);
3344 list_add_tail(&buf->list, &dsp->buffer_list);
3349 static int wm_adsp_buffer_parse_legacy(struct wm_adsp *dsp)
3351 struct wm_adsp_alg_region *alg_region;
3352 struct wm_adsp_compr_buf *buf;
3353 u32 xmalg, addr, magic;
3356 buf = wm_adsp_buffer_alloc(dsp);
3360 alg_region = wm_adsp_find_alg_region(dsp, WMFW_ADSP2_XM, dsp->fw_id);
3361 xmalg = sizeof(struct wm_adsp_system_config_xm_hdr) / sizeof(__be32);
3363 addr = alg_region->base + xmalg + ALG_XM_FIELD(magic);
3364 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr, &magic);
3368 if (magic != WM_ADSP_ALG_XM_STRUCT_MAGIC)
3371 addr = alg_region->base + xmalg + ALG_XM_FIELD(host_buf_ptr);
3372 for (i = 0; i < 5; ++i) {
3373 ret = wm_adsp_read_data_word(dsp, WMFW_ADSP2_XM, addr,
3374 &buf->host_buf_ptr);
3378 if (buf->host_buf_ptr)
3381 usleep_range(1000, 2000);
3384 if (!buf->host_buf_ptr)
3387 buf->host_buf_mem_type = WMFW_ADSP2_XM;
3389 ret = wm_adsp_buffer_populate(buf);
3393 compr_dbg(buf, "legacy host_buf_ptr=%x\n", buf->host_buf_ptr);
3398 static int wm_adsp_buffer_parse_coeff(struct wm_coeff_ctl *ctl)
3400 struct wm_adsp_host_buf_coeff_v1 coeff_v1;
3401 struct wm_adsp_compr_buf *buf;
3402 unsigned int val, reg;
3405 ret = wm_coeff_base_reg(ctl, ®);
3409 for (i = 0; i < 5; ++i) {
3410 ret = regmap_raw_read(ctl->dsp->regmap, reg, &val, sizeof(val));
3417 usleep_range(1000, 2000);
3421 adsp_err(ctl->dsp, "Failed to acquire host buffer\n");
3425 buf = wm_adsp_buffer_alloc(ctl->dsp);
3429 buf->host_buf_mem_type = ctl->alg_region.type;
3430 buf->host_buf_ptr = be32_to_cpu(val);
3432 ret = wm_adsp_buffer_populate(buf);
3437 * v0 host_buffer coefficients didn't have versioning, so if the
3438 * control is one word, assume version 0.
3440 if (ctl->len == 4) {
3441 compr_dbg(buf, "host_buf_ptr=%x\n", buf->host_buf_ptr);
3445 ret = regmap_raw_read(ctl->dsp->regmap, reg, &coeff_v1,
3450 coeff_v1.versions = be32_to_cpu(coeff_v1.versions);
3451 val = coeff_v1.versions & HOST_BUF_COEFF_COMPAT_VER_MASK;
3452 val >>= HOST_BUF_COEFF_COMPAT_VER_SHIFT;
3454 if (val > HOST_BUF_COEFF_SUPPORTED_COMPAT_VER) {
3456 "Host buffer coeff ver %u > supported version %u\n",
3457 val, HOST_BUF_COEFF_SUPPORTED_COMPAT_VER);
3461 for (i = 0; i < ARRAY_SIZE(coeff_v1.name); i++)
3462 coeff_v1.name[i] = be32_to_cpu(coeff_v1.name[i]);
3464 wm_adsp_remove_padding((u32 *)&coeff_v1.name,
3465 ARRAY_SIZE(coeff_v1.name),
3466 WM_ADSP_DATA_WORD_SIZE);
3468 buf->name = kasprintf(GFP_KERNEL, "%s-dsp-%s", ctl->dsp->part,
3469 (char *)&coeff_v1.name);
3471 compr_dbg(buf, "host_buf_ptr=%x coeff version %u\n",
3472 buf->host_buf_ptr, val);
3477 static int wm_adsp_buffer_init(struct wm_adsp *dsp)
3479 struct wm_coeff_ctl *ctl;
3482 list_for_each_entry(ctl, &dsp->ctl_list, list) {
3483 if (ctl->type != WMFW_CTL_TYPE_HOST_BUFFER)
3489 ret = wm_adsp_buffer_parse_coeff(ctl);
3491 adsp_err(dsp, "Failed to parse coeff: %d\n", ret);
3493 } else if (ret == 0) {
3494 /* Only one buffer supported for version 0 */
3499 if (list_empty(&dsp->buffer_list)) {
3500 /* Fall back to legacy support */
3501 ret = wm_adsp_buffer_parse_legacy(dsp);
3503 adsp_err(dsp, "Failed to parse legacy: %d\n", ret);
3511 wm_adsp_buffer_free(dsp);
3515 static int wm_adsp_buffer_free(struct wm_adsp *dsp)
3517 struct wm_adsp_compr_buf *buf, *tmp;
3519 list_for_each_entry_safe(buf, tmp, &dsp->buffer_list, list) {
3521 wm_adsp_compr_detach(buf->compr);
3524 kfree(buf->regions);
3525 list_del(&buf->list);
3532 static int wm_adsp_buffer_get_error(struct wm_adsp_compr_buf *buf)
3536 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(error), &buf->error);
3538 adsp_err(buf->dsp, "Failed to check buffer error: %d\n", ret);
3541 if (buf->error != 0) {
3542 adsp_err(buf->dsp, "Buffer error occurred: %d\n", buf->error);
3549 int wm_adsp_compr_trigger(struct snd_compr_stream *stream, int cmd)
3551 struct wm_adsp_compr *compr = stream->runtime->private_data;
3552 struct wm_adsp *dsp = compr->dsp;
3555 compr_dbg(compr, "Trigger: %d\n", cmd);
3557 mutex_lock(&dsp->pwr_lock);
3560 case SNDRV_PCM_TRIGGER_START:
3561 if (!wm_adsp_compr_attached(compr)) {
3562 ret = wm_adsp_compr_attach(compr);
3564 compr_err(compr, "Failed to link buffer and stream: %d\n",
3570 ret = wm_adsp_buffer_get_error(compr->buf);
3574 wm_adsp_buffer_clear(compr->buf);
3576 /* Trigger the IRQ at one fragment of data */
3577 ret = wm_adsp_buffer_write(compr->buf,
3578 HOST_BUFFER_FIELD(high_water_mark),
3579 wm_adsp_compr_frag_words(compr));
3581 compr_err(compr, "Failed to set high water mark: %d\n",
3586 case SNDRV_PCM_TRIGGER_STOP:
3593 mutex_unlock(&dsp->pwr_lock);
3597 EXPORT_SYMBOL_GPL(wm_adsp_compr_trigger);
3599 static inline int wm_adsp_buffer_size(struct wm_adsp_compr_buf *buf)
3601 int last_region = wm_adsp_fw[buf->dsp->fw].caps->num_regions - 1;
3603 return buf->regions[last_region].cumulative_size;
3606 static int wm_adsp_buffer_update_avail(struct wm_adsp_compr_buf *buf)
3608 u32 next_read_index, next_write_index;
3609 int write_index, read_index, avail;
3612 /* Only sync read index if we haven't already read a valid index */
3613 if (buf->read_index < 0) {
3614 ret = wm_adsp_buffer_read(buf,
3615 HOST_BUFFER_FIELD(next_read_index),
3620 read_index = sign_extend32(next_read_index, 23);
3622 if (read_index < 0) {
3623 compr_dbg(buf, "Avail check on unstarted stream\n");
3627 buf->read_index = read_index;
3630 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(next_write_index),
3635 write_index = sign_extend32(next_write_index, 23);
3637 avail = write_index - buf->read_index;
3639 avail += wm_adsp_buffer_size(buf);
3641 compr_dbg(buf, "readindex=0x%x, writeindex=0x%x, avail=%d\n",
3642 buf->read_index, write_index, avail * WM_ADSP_DATA_WORD_SIZE);
3649 int wm_adsp_compr_handle_irq(struct wm_adsp *dsp)
3651 struct wm_adsp_compr_buf *buf;
3652 struct wm_adsp_compr *compr;
3655 mutex_lock(&dsp->pwr_lock);
3657 if (list_empty(&dsp->buffer_list)) {
3662 adsp_dbg(dsp, "Handling buffer IRQ\n");
3664 list_for_each_entry(buf, &dsp->buffer_list, list) {
3667 ret = wm_adsp_buffer_get_error(buf);
3669 goto out_notify; /* Wake poll to report error */
3671 ret = wm_adsp_buffer_read(buf, HOST_BUFFER_FIELD(irq_count),
3674 compr_err(buf, "Failed to get irq_count: %d\n", ret);
3678 ret = wm_adsp_buffer_update_avail(buf);
3680 compr_err(buf, "Error reading avail: %d\n", ret);
3684 if (wm_adsp_fw[dsp->fw].voice_trigger && buf->irq_count == 2)
3685 ret = WM_ADSP_COMPR_VOICE_TRIGGER;
3688 if (compr && compr->stream)
3689 snd_compr_fragment_elapsed(compr->stream);
3693 mutex_unlock(&dsp->pwr_lock);
3697 EXPORT_SYMBOL_GPL(wm_adsp_compr_handle_irq);
3699 static int wm_adsp_buffer_reenable_irq(struct wm_adsp_compr_buf *buf)
3701 if (buf->irq_count & 0x01)
3704 compr_dbg(buf, "Enable IRQ(0x%x) for next fragment\n", buf->irq_count);
3706 buf->irq_count |= 0x01;
3708 return wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(irq_ack),
3712 int wm_adsp_compr_pointer(struct snd_compr_stream *stream,
3713 struct snd_compr_tstamp *tstamp)
3715 struct wm_adsp_compr *compr = stream->runtime->private_data;
3716 struct wm_adsp *dsp = compr->dsp;
3717 struct wm_adsp_compr_buf *buf;
3720 compr_dbg(compr, "Pointer request\n");
3722 mutex_lock(&dsp->pwr_lock);
3726 if (!compr->buf || compr->buf->error) {
3727 snd_compr_stop_error(stream, SNDRV_PCM_STATE_XRUN);
3732 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3733 ret = wm_adsp_buffer_update_avail(buf);
3735 compr_err(compr, "Error reading avail: %d\n", ret);
3740 * If we really have less than 1 fragment available tell the
3741 * DSP to inform us once a whole fragment is available.
3743 if (buf->avail < wm_adsp_compr_frag_words(compr)) {
3744 ret = wm_adsp_buffer_get_error(buf);
3746 if (compr->buf->error)
3747 snd_compr_stop_error(stream,
3748 SNDRV_PCM_STATE_XRUN);
3752 ret = wm_adsp_buffer_reenable_irq(buf);
3754 compr_err(compr, "Failed to re-enable buffer IRQ: %d\n",
3761 tstamp->copied_total = compr->copied_total;
3762 tstamp->copied_total += buf->avail * WM_ADSP_DATA_WORD_SIZE;
3763 tstamp->sampling_rate = compr->sample_rate;
3766 mutex_unlock(&dsp->pwr_lock);
3770 EXPORT_SYMBOL_GPL(wm_adsp_compr_pointer);
3772 static int wm_adsp_buffer_capture_block(struct wm_adsp_compr *compr, int target)
3774 struct wm_adsp_compr_buf *buf = compr->buf;
3775 unsigned int adsp_addr;
3776 int mem_type, nwords, max_read;
3779 /* Calculate read parameters */
3780 for (i = 0; i < wm_adsp_fw[buf->dsp->fw].caps->num_regions; ++i)
3781 if (buf->read_index < buf->regions[i].cumulative_size)
3784 if (i == wm_adsp_fw[buf->dsp->fw].caps->num_regions)
3787 mem_type = buf->regions[i].mem_type;
3788 adsp_addr = buf->regions[i].base_addr +
3789 (buf->read_index - buf->regions[i].offset);
3791 max_read = wm_adsp_compr_frag_words(compr);
3792 nwords = buf->regions[i].cumulative_size - buf->read_index;
3794 if (nwords > target)
3796 if (nwords > buf->avail)
3797 nwords = buf->avail;
3798 if (nwords > max_read)
3803 /* Read data from DSP */
3804 ret = wm_adsp_read_data_block(buf->dsp, mem_type, adsp_addr,
3805 nwords, compr->raw_buf);
3809 wm_adsp_remove_padding(compr->raw_buf, nwords, WM_ADSP_DATA_WORD_SIZE);
3811 /* update read index to account for words read */
3812 buf->read_index += nwords;
3813 if (buf->read_index == wm_adsp_buffer_size(buf))
3814 buf->read_index = 0;
3816 ret = wm_adsp_buffer_write(buf, HOST_BUFFER_FIELD(next_read_index),
3821 /* update avail to account for words read */
3822 buf->avail -= nwords;
3827 static int wm_adsp_compr_read(struct wm_adsp_compr *compr,
3828 char __user *buf, size_t count)
3833 compr_dbg(compr, "Requested read of %zu bytes\n", count);
3835 if (!compr->buf || compr->buf->error) {
3836 snd_compr_stop_error(compr->stream, SNDRV_PCM_STATE_XRUN);
3840 count /= WM_ADSP_DATA_WORD_SIZE;
3843 nwords = wm_adsp_buffer_capture_block(compr, count);
3845 compr_err(compr, "Failed to capture block: %d\n",
3850 nbytes = nwords * WM_ADSP_DATA_WORD_SIZE;
3852 compr_dbg(compr, "Read %d bytes\n", nbytes);
3854 if (copy_to_user(buf + ntotal, compr->raw_buf, nbytes)) {
3855 compr_err(compr, "Failed to copy data to user: %d, %d\n",
3862 } while (nwords > 0 && count > 0);
3864 compr->copied_total += ntotal;
3869 int wm_adsp_compr_copy(struct snd_compr_stream *stream, char __user *buf,
3872 struct wm_adsp_compr *compr = stream->runtime->private_data;
3873 struct wm_adsp *dsp = compr->dsp;
3876 mutex_lock(&dsp->pwr_lock);
3878 if (stream->direction == SND_COMPRESS_CAPTURE)
3879 ret = wm_adsp_compr_read(compr, buf, count);
3883 mutex_unlock(&dsp->pwr_lock);
3887 EXPORT_SYMBOL_GPL(wm_adsp_compr_copy);
3889 int wm_adsp2_lock(struct wm_adsp *dsp, unsigned int lock_regions)
3891 struct regmap *regmap = dsp->regmap;
3892 unsigned int code0, code1, lock_reg;
3894 if (!(lock_regions & WM_ADSP2_REGION_ALL))
3897 lock_regions &= WM_ADSP2_REGION_ALL;
3898 lock_reg = dsp->base + ADSP2_LOCK_REGION_1_LOCK_REGION_0;
3900 while (lock_regions) {
3902 if (lock_regions & BIT(0)) {
3903 code0 = ADSP2_LOCK_CODE_0;
3904 code1 = ADSP2_LOCK_CODE_1;
3906 if (lock_regions & BIT(1)) {
3907 code0 |= ADSP2_LOCK_CODE_0 << ADSP2_LOCK_REGION_SHIFT;
3908 code1 |= ADSP2_LOCK_CODE_1 << ADSP2_LOCK_REGION_SHIFT;
3910 regmap_write(regmap, lock_reg, code0);
3911 regmap_write(regmap, lock_reg, code1);
3918 EXPORT_SYMBOL_GPL(wm_adsp2_lock);
3920 irqreturn_t wm_adsp2_bus_error(struct wm_adsp *dsp)
3923 struct regmap *regmap = dsp->regmap;
3926 ret = regmap_read(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL, &val);
3929 "Failed to read Region Lock Ctrl register: %d\n", ret);
3933 if (val & ADSP2_WDT_TIMEOUT_STS_MASK) {
3934 adsp_err(dsp, "watchdog timeout error\n");
3935 wm_adsp_stop_watchdog(dsp);
3938 if (val & (ADSP2_SLAVE_ERR_MASK | ADSP2_REGION_LOCK_ERR_MASK)) {
3939 if (val & ADSP2_SLAVE_ERR_MASK)
3940 adsp_err(dsp, "bus error: slave error\n");
3942 adsp_err(dsp, "bus error: region lock error\n");
3944 ret = regmap_read(regmap, dsp->base + ADSP2_BUS_ERR_ADDR, &val);
3947 "Failed to read Bus Err Addr register: %d\n",
3952 adsp_err(dsp, "bus error address = 0x%x\n",
3953 val & ADSP2_BUS_ERR_ADDR_MASK);
3955 ret = regmap_read(regmap,
3956 dsp->base + ADSP2_PMEM_ERR_ADDR_XMEM_ERR_ADDR,
3960 "Failed to read Pmem Xmem Err Addr register: %d\n",
3965 adsp_err(dsp, "xmem error address = 0x%x\n",
3966 val & ADSP2_XMEM_ERR_ADDR_MASK);
3967 adsp_err(dsp, "pmem error address = 0x%x\n",
3968 (val & ADSP2_PMEM_ERR_ADDR_MASK) >>
3969 ADSP2_PMEM_ERR_ADDR_SHIFT);
3972 regmap_update_bits(regmap, dsp->base + ADSP2_LOCK_REGION_CTRL,
3973 ADSP2_CTRL_ERR_EINT, ADSP2_CTRL_ERR_EINT);
3977 EXPORT_SYMBOL_GPL(wm_adsp2_bus_error);
3979 MODULE_LICENSE("GPL v2");