sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/soc.h>
  33 #include <sound/soc-dapm.h>
  34 #include <sound/tlv.h>
  35 #include <sound/initval.h>
  36 #include <asm/div64.h>
  37
  38 #include "wm8580.h"
  39
  40 /* WM8580 register space */
  41 #define WM8580_PLLA1                         0x00
  42 #define WM8580_PLLA2                         0x01
  43 #define WM8580_PLLA3                         0x02
  44 #define WM8580_PLLA4                         0x03
  45 #define WM8580_PLLB1                         0x04
  46 #define WM8580_PLLB2                         0x05
  47 #define WM8580_PLLB3                         0x06
  48 #define WM8580_PLLB4                         0x07
  49 #define WM8580_CLKSEL                        0x08
  50 #define WM8580_PAIF1                         0x09
  51 #define WM8580_PAIF2                         0x0A
  52 #define WM8580_SAIF1                         0x0B
  53 #define WM8580_PAIF3                         0x0C
  54 #define WM8580_PAIF4                         0x0D
  55 #define WM8580_SAIF2                         0x0E
  56 #define WM8580_DAC_CONTROL1                  0x0F
  57 #define WM8580_DAC_CONTROL2                  0x10
  58 #define WM8580_DAC_CONTROL3                  0x11
  59 #define WM8580_DAC_CONTROL4                  0x12
  60 #define WM8580_DAC_CONTROL5                  0x13
  61 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  62 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  63 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  64 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  65 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  66 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  67 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  68 #define WM8580_ADC_CONTROL1                  0x1D
  69 #define WM8580_SPDTXCHAN0                    0x1E
  70 #define WM8580_SPDTXCHAN1                    0x1F
  71 #define WM8580_SPDTXCHAN2                    0x20
  72 #define WM8580_SPDTXCHAN3                    0x21
  73 #define WM8580_SPDTXCHAN4                    0x22
  74 #define WM8580_SPDTXCHAN5                    0x23
  75 #define WM8580_SPDMODE                       0x24
  76 #define WM8580_INTMASK                       0x25
  77 #define WM8580_GPO1                          0x26
  78 #define WM8580_GPO2                          0x27
  79 #define WM8580_GPO3                          0x28
  80 #define WM8580_GPO4                          0x29
  81 #define WM8580_GPO5                          0x2A
  82 #define WM8580_INTSTAT                       0x2B
  83 #define WM8580_SPDRXCHAN1                    0x2C
  84 #define WM8580_SPDRXCHAN2                    0x2D
  85 #define WM8580_SPDRXCHAN3                    0x2E
  86 #define WM8580_SPDRXCHAN4                    0x2F
  87 #define WM8580_SPDRXCHAN5                    0x30
  88 #define WM8580_SPDSTAT                       0x31
  89 #define WM8580_PWRDN1                        0x32
  90 #define WM8580_PWRDN2                        0x33
  91 #define WM8580_READBACK                      0x34
  92 #define WM8580_RESET                         0x35
  93
  94 #define WM8580_MAX_REGISTER                  0x35
  95
  96 /* PLLB4 (register 7h) */
  97 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
  98 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
  99 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 100 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 101
 102 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 103 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 104 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 105 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 106
 107 /* CLKSEL (register 8h) */
 108 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 109 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 110 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 111
 112 /* AIF control 1 (registers 9h-bh) */
 113 #define WM8580_AIF_RATE_MASK       0x7
 114 #define WM8580_AIF_RATE_128        0x0
 115 #define WM8580_AIF_RATE_192        0x1
 116 #define WM8580_AIF_RATE_256        0x2
 117 #define WM8580_AIF_RATE_384        0x3
 118 #define WM8580_AIF_RATE_512        0x4
 119 #define WM8580_AIF_RATE_768        0x5
 120 #define WM8580_AIF_RATE_1152       0x6
 121
 122 #define WM8580_AIF_BCLKSEL_MASK   0x18
 123 #define WM8580_AIF_BCLKSEL_64     0x00
 124 #define WM8580_AIF_BCLKSEL_128    0x08
 125 #define WM8580_AIF_BCLKSEL_256    0x10
 126 #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
 127
 128 #define WM8580_AIF_MS             0x20
 129
 130 #define WM8580_AIF_CLKSRC_MASK    0xc0
 131 #define WM8580_AIF_CLKSRC_PLLA    0x40
 132 #define WM8580_AIF_CLKSRC_PLLB    0x40
 133 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 134
 135 /* AIF control 2 (registers ch-eh) */
 136 #define WM8580_AIF_FMT_MASK    0x03
 137 #define WM8580_AIF_FMT_RIGHTJ  0x00
 138 #define WM8580_AIF_FMT_LEFTJ   0x01
 139 #define WM8580_AIF_FMT_I2S     0x02
 140 #define WM8580_AIF_FMT_DSP     0x03
 141
 142 #define WM8580_AIF_LENGTH_MASK   0x0c
 143 #define WM8580_AIF_LENGTH_16     0x00
 144 #define WM8580_AIF_LENGTH_20     0x04
 145 #define WM8580_AIF_LENGTH_24     0x08
 146 #define WM8580_AIF_LENGTH_32     0x0c
 147
 148 #define WM8580_AIF_LRP         0x10
 149 #define WM8580_AIF_BCP         0x20
 150
 151 /* Powerdown Register 1 (register 32h) */
 152 #define WM8580_PWRDN1_PWDN     0x001
 153 #define WM8580_PWRDN1_ALLDACPD 0x040
 154
 155 /* Powerdown Register 2 (register 33h) */
 156 #define WM8580_PWRDN2_OSSCPD   0x001
 157 #define WM8580_PWRDN2_PLLAPD   0x002
 158 #define WM8580_PWRDN2_PLLBPD   0x004
 159 #define WM8580_PWRDN2_SPDIFPD  0x008
 160 #define WM8580_PWRDN2_SPDIFTXD 0x010
 161 #define WM8580_PWRDN2_SPDIFRXD 0x020
 162
 163 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 164
 165 /*
 166  * wm8580 register cache
 167  * We can't read the WM8580 register space when we
 168  * are using 2 wire for device control, so we cache them instead.
 169  */
 170 static const u16 wm8580_reg[] = {
 171         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 172         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 173         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 174         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 175         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 176         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 177         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 178         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 179         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 180         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 181         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 182         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 183         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 184         0x0000, 0x0000 /*R53*/
 185 };
 186
 187 struct pll_state {
 188         unsigned int in;
 189         unsigned int out;
 190 };
 191
 192 #define WM8580_NUM_SUPPLIES 3
 193 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 194         "AVDD",
 195         "DVDD",
 196         "PVDD",
 197 };
 198
 199 /* codec private data */
 200 struct wm8580_priv {
 201         struct snd_soc_codec codec;
 202         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 203         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 204         struct pll_state a;
 205         struct pll_state b;
 206 };
 207
 208 /*
 209  * read wm8580 register cache
 210  */
 211 static inline unsigned int wm8580_read_reg_cache(struct snd_soc_codec *codec,
 212         unsigned int reg)
 213 {
 214         u16 *cache = codec->reg_cache;
 215         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 216         return cache[reg];
 217 }
 218
 219 /*
 220  * write wm8580 register cache
 221  */
 222 static inline void wm8580_write_reg_cache(struct snd_soc_codec *codec,
 223         unsigned int reg, unsigned int value)
 224 {
 225         u16 *cache = codec->reg_cache;
 226
 227         cache[reg] = value;
 228 }
 229
 230 /*
 231  * write to the WM8580 register space
 232  */
 233 static int wm8580_write(struct snd_soc_codec *codec, unsigned int reg,
 234         unsigned int value)
 235 {
 236         u8 data[2];
 237
 238         BUG_ON(reg >= ARRAY_SIZE(wm8580_reg));
 239
 240         /* Registers are 9 bits wide */
 241         value &= 0x1ff;
 242
 243         switch (reg) {
 244         case WM8580_RESET:
 245                 /* Uncached */
 246                 break;
 247         default:
 248                 if (value == wm8580_read_reg_cache(codec, reg))
 249                         return 0;
 250         }
 251
 252         /* data is
 253          *   D15..D9 WM8580 register offset
 254          *   D8...D0 register data
 255          */
 256         data[0] = (reg << 1) | ((value >> 8) & 0x0001);
 257         data[1] = value & 0x00ff;
 258
 259         wm8580_write_reg_cache(codec, reg, value);
 260         if (codec->hw_write(codec->control_data, data, 2) == 2)
 261                 return 0;
 262         else
 263                 return -EIO;
 264 }
 265
 266 static inline unsigned int wm8580_read(struct snd_soc_codec *codec,
 267                                        unsigned int reg)
 268 {
 269         switch (reg) {
 270         default:
 271                 return wm8580_read_reg_cache(codec, reg);
 272         }
 273 }
 274
 275 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 276
 277 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 278                          struct snd_ctl_elem_value *ucontrol)
 279 {
 280         struct soc_mixer_control *mc =
 281                 (struct soc_mixer_control *)kcontrol->private_value;
 282         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 283         unsigned int reg = mc->reg;
 284         unsigned int reg2 = mc->rreg;
 285         int ret;
 286         u16 val;
 287
 288         /* Clear the register cache so we write without VU set */
 289         wm8580_write_reg_cache(codec, reg, 0);
 290         wm8580_write_reg_cache(codec, reg2, 0);
 291
 292         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 293         if (ret < 0)
 294                 return ret;
 295
 296         /* Now write again with the volume update bit set */
 297         val = wm8580_read_reg_cache(codec, reg);
 298         wm8580_write(codec, reg, val | 0x0100);
 299
 300         val = wm8580_read_reg_cache(codec, reg2);
 301         wm8580_write(codec, reg2, val | 0x0100);
 302
 303         return 0;
 304 }
 305
 306 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 307                                     xinvert, tlv_array)                 \
 308 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 309         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 310                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 311         .tlv.p = (tlv_array), \
 312         .info = snd_soc_info_volsw_2r, \
 313         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 314         .private_value = (unsigned long)&(struct soc_mixer_control) \
 315                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 316                 .max = xmax, .invert = xinvert} }
 317
 318 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 319 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 320                             WM8580_DIGITAL_ATTENUATION_DACL1,
 321                             WM8580_DIGITAL_ATTENUATION_DACR1,
 322                             0, 0xff, 0, dac_tlv),
 323 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 324                             WM8580_DIGITAL_ATTENUATION_DACL2,
 325                             WM8580_DIGITAL_ATTENUATION_DACR2,
 326                             0, 0xff, 0, dac_tlv),
 327 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 328                             WM8580_DIGITAL_ATTENUATION_DACL3,
 329                             WM8580_DIGITAL_ATTENUATION_DACR3,
 330                             0, 0xff, 0, dac_tlv),
 331
 332 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 333 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 334 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 335
 336 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 337 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 338 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 339
 340 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 341 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 0),
 342 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 0),
 343 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 0),
 344
 345 SOC_DOUBLE("ADC Mute Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 0),
 346 SOC_SINGLE("ADC High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 347 };
 348
 349 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 350 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 351 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 352 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 353
 354 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 355 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 356 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 357 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 358 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 359 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 360
 361 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 362
 363 SND_SOC_DAPM_INPUT("AINL"),
 364 SND_SOC_DAPM_INPUT("AINR"),
 365 };
 366
 367 static const struct snd_soc_dapm_route audio_map[] = {
 368         { "VOUT1L", NULL, "DAC1" },
 369         { "VOUT1R", NULL, "DAC1" },
 370
 371         { "VOUT2L", NULL, "DAC2" },
 372         { "VOUT2R", NULL, "DAC2" },
 373
 374         { "VOUT3L", NULL, "DAC3" },
 375         { "VOUT3R", NULL, "DAC3" },
 376
 377         { "ADC", NULL, "AINL" },
 378         { "ADC", NULL, "AINR" },
 379 };
 380
 381 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 382 {
 383         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 384                                   ARRAY_SIZE(wm8580_dapm_widgets));
 385
 386         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 387
 388         snd_soc_dapm_new_widgets(codec);
 389         return 0;
 390 }
 391
 392 /* PLL divisors */
 393 struct _pll_div {
 394         u32 prescale:1;
 395         u32 postscale:1;
 396         u32 freqmode:2;
 397         u32 n:4;
 398         u32 k:24;
 399 };
 400
 401 /* The size in bits of the pll divide */
 402 #define FIXED_PLL_SIZE (1 << 22)
 403
 404 /* PLL rate to output rate divisions */
 405 static struct {
 406         unsigned int div;
 407         unsigned int freqmode;
 408         unsigned int postscale;
 409 } post_table[] = {
 410         {  2,  0, 0 },
 411         {  4,  0, 1 },
 412         {  4,  1, 0 },
 413         {  8,  1, 1 },
 414         {  8,  2, 0 },
 415         { 16,  2, 1 },
 416         { 12,  3, 0 },
 417         { 24,  3, 1 }
 418 };
 419
 420 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 421                        unsigned int source)
 422 {
 423         u64 Kpart;
 424         unsigned int K, Ndiv, Nmod;
 425         int i;
 426
 427         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 428
 429         /* Scale the output frequency up; the PLL should run in the
 430          * region of 90-100MHz.
 431          */
 432         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 433                 if (target * post_table[i].div >=  90000000 &&
 434                     target * post_table[i].div <= 100000000) {
 435                         pll_div->freqmode = post_table[i].freqmode;
 436                         pll_div->postscale = post_table[i].postscale;
 437                         target *= post_table[i].div;
 438                         break;
 439                 }
 440         }
 441
 442         if (i == ARRAY_SIZE(post_table)) {
 443                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 444                        "%u\n", target);
 445                 return -EINVAL;
 446         }
 447
 448         Ndiv = target / source;
 449
 450         if (Ndiv < 5) {
 451                 source /= 2;
 452                 pll_div->prescale = 1;
 453                 Ndiv = target / source;
 454         } else
 455                 pll_div->prescale = 0;
 456
 457         if ((Ndiv < 5) || (Ndiv > 13)) {
 458                 printk(KERN_ERR
 459                         "WM8580 N=%u outside supported range\n", Ndiv);
 460                 return -EINVAL;
 461         }
 462
 463         pll_div->n = Ndiv;
 464         Nmod = target % source;
 465         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 466
 467         do_div(Kpart, source);
 468
 469         K = Kpart & 0xFFFFFFFF;
 470
 471         pll_div->k = K;
 472
 473         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 474                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 475                  pll_div->postscale);
 476
 477         return 0;
 478 }
 479
 480 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai,
 481                 int pll_id, unsigned int freq_in, unsigned int freq_out)
 482 {
 483         int offset;
 484         struct snd_soc_codec *codec = codec_dai->codec;
 485         struct wm8580_priv *wm8580 = codec->private_data;
 486         struct pll_state *state;
 487         struct _pll_div pll_div;
 488         unsigned int reg;
 489         unsigned int pwr_mask;
 490         int ret;
 491
 492         /* GCC isn't able to work out the ifs below for initialising/using
 493          * pll_div so suppress warnings.
 494          */
 495         memset(&pll_div, 0, sizeof(pll_div));
 496
 497         switch (pll_id) {
 498         case WM8580_PLLA:
 499                 state = &wm8580->a;
 500                 offset = 0;
 501                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 502                 break;
 503         case WM8580_PLLB:
 504                 state = &wm8580->b;
 505                 offset = 4;
 506                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 507                 break;
 508         default:
 509                 return -ENODEV;
 510         }
 511
 512         if (freq_in && freq_out) {
 513                 ret = pll_factors(&pll_div, freq_out, freq_in);
 514                 if (ret != 0)
 515                         return ret;
 516         }
 517
 518         state->in = freq_in;
 519         state->out = freq_out;
 520
 521         /* Always disable the PLL - it is not safe to leave it running
 522          * while reprogramming it.
 523          */
 524         reg = wm8580_read(codec, WM8580_PWRDN2);
 525         wm8580_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 526
 527         if (!freq_in || !freq_out)
 528                 return 0;
 529
 530         wm8580_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 531         wm8580_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0xff);
 532         wm8580_write(codec, WM8580_PLLA3 + offset,
 533                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 534
 535         reg = wm8580_read(codec, WM8580_PLLA4 + offset);
 536         reg &= ~0x3f;
 537         reg |= pll_div.prescale | pll_div.postscale << 1 |
 538                 pll_div.freqmode << 3;
 539
 540         wm8580_write(codec, WM8580_PLLA4 + offset, reg);
 541
 542         /* All done, turn it on */
 543         reg = wm8580_read(codec, WM8580_PWRDN2);
 544         wm8580_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 545
 546         return 0;
 547 }
 548
 549 /*
 550  * Set PCM DAI bit size and sample rate.
 551  */
 552 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 553                                  struct snd_pcm_hw_params *params,
 554                                  struct snd_soc_dai *dai)
 555 {
 556         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 557         struct snd_soc_device *socdev = rtd->socdev;
 558         struct snd_soc_codec *codec = socdev->card->codec;
 559         u16 paifb = wm8580_read(codec, WM8580_PAIF3 + dai->id);
 560
 561         paifb &= ~WM8580_AIF_LENGTH_MASK;
 562         /* bit size */
 563         switch (params_format(params)) {
 564         case SNDRV_PCM_FORMAT_S16_LE:
 565                 break;
 566         case SNDRV_PCM_FORMAT_S20_3LE:
 567                 paifb |= WM8580_AIF_LENGTH_20;
 568                 break;
 569         case SNDRV_PCM_FORMAT_S24_LE:
 570                 paifb |= WM8580_AIF_LENGTH_24;
 571                 break;
 572         case SNDRV_PCM_FORMAT_S32_LE:
 573                 paifb |= WM8580_AIF_LENGTH_24;
 574                 break;
 575         default:
 576                 return -EINVAL;
 577         }
 578
 579         wm8580_write(codec, WM8580_PAIF3 + dai->id, paifb);
 580         return 0;
 581 }
 582
 583 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 584                                       unsigned int fmt)
 585 {
 586         struct snd_soc_codec *codec = codec_dai->codec;
 587         unsigned int aifa;
 588         unsigned int aifb;
 589         int can_invert_lrclk;
 590
 591         aifa = wm8580_read(codec, WM8580_PAIF1 + codec_dai->id);
 592         aifb = wm8580_read(codec, WM8580_PAIF3 + codec_dai->id);
 593
 594         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 595
 596         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 597         case SND_SOC_DAIFMT_CBS_CFS:
 598                 aifa &= ~WM8580_AIF_MS;
 599                 break;
 600         case SND_SOC_DAIFMT_CBM_CFM:
 601                 aifa |= WM8580_AIF_MS;
 602                 break;
 603         default:
 604                 return -EINVAL;
 605         }
 606
 607         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 608         case SND_SOC_DAIFMT_I2S:
 609                 can_invert_lrclk = 1;
 610                 aifb |= WM8580_AIF_FMT_I2S;
 611                 break;
 612         case SND_SOC_DAIFMT_RIGHT_J:
 613                 can_invert_lrclk = 1;
 614                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 615                 break;
 616         case SND_SOC_DAIFMT_LEFT_J:
 617                 can_invert_lrclk = 1;
 618                 aifb |= WM8580_AIF_FMT_LEFTJ;
 619                 break;
 620         case SND_SOC_DAIFMT_DSP_A:
 621                 can_invert_lrclk = 0;
 622                 aifb |= WM8580_AIF_FMT_DSP;
 623                 break;
 624         case SND_SOC_DAIFMT_DSP_B:
 625                 can_invert_lrclk = 0;
 626                 aifb |= WM8580_AIF_FMT_DSP;
 627                 aifb |= WM8580_AIF_LRP;
 628                 break;
 629         default:
 630                 return -EINVAL;
 631         }
 632
 633         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 634         case SND_SOC_DAIFMT_NB_NF:
 635                 break;
 636
 637         case SND_SOC_DAIFMT_IB_IF:
 638                 if (!can_invert_lrclk)
 639                         return -EINVAL;
 640                 aifb |= WM8580_AIF_BCP;
 641                 aifb |= WM8580_AIF_LRP;
 642                 break;
 643
 644         case SND_SOC_DAIFMT_IB_NF:
 645                 aifb |= WM8580_AIF_BCP;
 646                 break;
 647
 648         case SND_SOC_DAIFMT_NB_IF:
 649                 if (!can_invert_lrclk)
 650                         return -EINVAL;
 651                 aifb |= WM8580_AIF_LRP;
 652                 break;
 653
 654         default:
 655                 return -EINVAL;
 656         }
 657
 658         wm8580_write(codec, WM8580_PAIF1 + codec_dai->id, aifa);
 659         wm8580_write(codec, WM8580_PAIF3 + codec_dai->id, aifb);
 660
 661         return 0;
 662 }
 663
 664 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 665                                  int div_id, int div)
 666 {
 667         struct snd_soc_codec *codec = codec_dai->codec;
 668         unsigned int reg;
 669
 670         switch (div_id) {
 671         case WM8580_MCLK:
 672                 reg = wm8580_read(codec, WM8580_PLLB4);
 673                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 674
 675                 switch (div) {
 676                 case WM8580_CLKSRC_MCLK:
 677                         /* Input */
 678                         break;
 679
 680                 case WM8580_CLKSRC_PLLA:
 681                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 682                         break;
 683                 case WM8580_CLKSRC_PLLB:
 684                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 685                         break;
 686
 687                 case WM8580_CLKSRC_OSC:
 688                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 689                         break;
 690
 691                 default:
 692                         return -EINVAL;
 693                 }
 694                 wm8580_write(codec, WM8580_PLLB4, reg);
 695                 break;
 696
 697         case WM8580_DAC_CLKSEL:
 698                 reg = wm8580_read(codec, WM8580_CLKSEL);
 699                 reg &= ~WM8580_CLKSEL_DAC_CLKSEL_MASK;
 700
 701                 switch (div) {
 702                 case WM8580_CLKSRC_MCLK:
 703                         break;
 704
 705                 case WM8580_CLKSRC_PLLA:
 706                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLA;
 707                         break;
 708
 709                 case WM8580_CLKSRC_PLLB:
 710                         reg |= WM8580_CLKSEL_DAC_CLKSEL_PLLB;
 711                         break;
 712
 713                 default:
 714                         return -EINVAL;
 715                 }
 716                 wm8580_write(codec, WM8580_CLKSEL, reg);
 717                 break;
 718
 719         case WM8580_CLKOUTSRC:
 720                 reg = wm8580_read(codec, WM8580_PLLB4);
 721                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 722
 723                 switch (div) {
 724                 case WM8580_CLKSRC_NONE:
 725                         break;
 726
 727                 case WM8580_CLKSRC_PLLA:
 728                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 729                         break;
 730
 731                 case WM8580_CLKSRC_PLLB:
 732                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 733                         break;
 734
 735                 case WM8580_CLKSRC_OSC:
 736                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 737                         break;
 738
 739                 default:
 740                         return -EINVAL;
 741                 }
 742                 wm8580_write(codec, WM8580_PLLB4, reg);
 743                 break;
 744
 745         default:
 746                 return -EINVAL;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 753 {
 754         struct snd_soc_codec *codec = codec_dai->codec;
 755         unsigned int reg;
 756
 757         reg = wm8580_read(codec, WM8580_DAC_CONTROL5);
 758
 759         if (mute)
 760                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 761         else
 762                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 763
 764         wm8580_write(codec, WM8580_DAC_CONTROL5, reg);
 765
 766         return 0;
 767 }
 768
 769 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 770         enum snd_soc_bias_level level)
 771 {
 772         u16 reg;
 773         switch (level) {
 774         case SND_SOC_BIAS_ON:
 775         case SND_SOC_BIAS_PREPARE:
 776                 break;
 777
 778         case SND_SOC_BIAS_STANDBY:
 779                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 780                         /* Power up and get individual control of the DACs */
 781                         reg = wm8580_read(codec, WM8580_PWRDN1);
 782                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 783                         wm8580_write(codec, WM8580_PWRDN1, reg);
 784
 785                         /* Make VMID high impedence */
 786                         reg = wm8580_read(codec,  WM8580_ADC_CONTROL1);
 787                         reg &= ~0x100;
 788                         wm8580_write(codec, WM8580_ADC_CONTROL1, reg);
 789                 }
 790                 break;
 791
 792         case SND_SOC_BIAS_OFF:
 793                 reg = wm8580_read(codec, WM8580_PWRDN1);
 794                 wm8580_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 795                 break;
 796         }
 797         codec->bias_level = level;
 798         return 0;
 799 }
 800
 801 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 802                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 803
 804 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 805         .hw_params      = wm8580_paif_hw_params,
 806         .set_fmt        = wm8580_set_paif_dai_fmt,
 807         .set_clkdiv     = wm8580_set_dai_clkdiv,
 808         .set_pll        = wm8580_set_dai_pll,
 809         .digital_mute   = wm8580_digital_mute,
 810 };
 811
 812 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 813         .hw_params      = wm8580_paif_hw_params,
 814         .set_fmt        = wm8580_set_paif_dai_fmt,
 815         .set_clkdiv     = wm8580_set_dai_clkdiv,
 816         .set_pll        = wm8580_set_dai_pll,
 817 };
 818
 819 struct snd_soc_dai wm8580_dai[] = {
 820         {
 821                 .name = "WM8580 PAIFRX",
 822                 .id = 0,
 823                 .playback = {
 824                         .stream_name = "Playback",
 825                         .channels_min = 1,
 826                         .channels_max = 6,
 827                         .rates = SNDRV_PCM_RATE_8000_192000,
 828                         .formats = WM8580_FORMATS,
 829                 },
 830                 .ops = &wm8580_dai_ops_playback,
 831         },
 832         {
 833                 .name = "WM8580 PAIFTX",
 834                 .id = 1,
 835                 .capture = {
 836                         .stream_name = "Capture",
 837                         .channels_min = 2,
 838                         .channels_max = 2,
 839                         .rates = SNDRV_PCM_RATE_8000_192000,
 840                         .formats = WM8580_FORMATS,
 841                 },
 842                 .ops = &wm8580_dai_ops_capture,
 843         },
 844 };
 845 EXPORT_SYMBOL_GPL(wm8580_dai);
 846
 847 static struct snd_soc_codec *wm8580_codec;
 848
 849 static int wm8580_probe(struct platform_device *pdev)
 850 {
 851         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 852         struct snd_soc_codec *codec;
 853         int ret = 0;
 854
 855         if (wm8580_codec == NULL) {
 856                 dev_err(&pdev->dev, "Codec device not registered\n");
 857                 return -ENODEV;
 858         }
 859
 860         socdev->card->codec = wm8580_codec;
 861         codec = wm8580_codec;
 862
 863         /* register pcms */
 864         ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
 865         if (ret < 0) {
 866                 dev_err(codec->dev, "failed to create pcms: %d\n", ret);
 867                 goto pcm_err;
 868         }
 869
 870         snd_soc_add_controls(codec, wm8580_snd_controls,
 871                              ARRAY_SIZE(wm8580_snd_controls));
 872         wm8580_add_widgets(codec);
 873         ret = snd_soc_init_card(socdev);
 874         if (ret < 0) {
 875                 dev_err(codec->dev, "failed to register card: %d\n", ret);
 876                 goto card_err;
 877         }
 878
 879         return ret;
 880
 881 card_err:
 882         snd_soc_free_pcms(socdev);
 883         snd_soc_dapm_free(socdev);
 884 pcm_err:
 885         return ret;
 886 }
 887
 888 /* power down chip */
 889 static int wm8580_remove(struct platform_device *pdev)
 890 {
 891         struct snd_soc_device *socdev = platform_get_drvdata(pdev);
 892
 893         snd_soc_free_pcms(socdev);
 894         snd_soc_dapm_free(socdev);
 895
 896         return 0;
 897 }
 898
 899 struct snd_soc_codec_device soc_codec_dev_wm8580 = {
 900         .probe =        wm8580_probe,
 901         .remove =       wm8580_remove,
 902 };
 903 EXPORT_SYMBOL_GPL(soc_codec_dev_wm8580);
 904
 905 static int wm8580_register(struct wm8580_priv *wm8580)
 906 {
 907         int ret, i;
 908         struct snd_soc_codec *codec = &wm8580->codec;
 909
 910         if (wm8580_codec) {
 911                 dev_err(codec->dev, "Another WM8580 is registered\n");
 912                 ret = -EINVAL;
 913                 goto err;
 914         }
 915
 916         mutex_init(&codec->mutex);
 917         INIT_LIST_HEAD(&codec->dapm_widgets);
 918         INIT_LIST_HEAD(&codec->dapm_paths);
 919
 920         codec->private_data = wm8580;
 921         codec->name = "WM8580";
 922         codec->owner = THIS_MODULE;
 923         codec->read = wm8580_read_reg_cache;
 924         codec->write = wm8580_write;
 925         codec->bias_level = SND_SOC_BIAS_OFF;
 926         codec->set_bias_level = wm8580_set_bias_level;
 927         codec->dai = wm8580_dai;
 928         codec->num_dai = ARRAY_SIZE(wm8580_dai);
 929         codec->reg_cache_size = ARRAY_SIZE(wm8580->reg_cache);
 930         codec->reg_cache = &wm8580->reg_cache;
 931
 932         memcpy(codec->reg_cache, wm8580_reg, sizeof(wm8580_reg));
 933
 934         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 935                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 936
 937         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 938                                  wm8580->supplies);
 939         if (ret != 0) {
 940                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 941                 goto err;
 942         }
 943
 944         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 945                                     wm8580->supplies);
 946         if (ret != 0) {
 947                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 948                 goto err_regulator_get;
 949         }
 950
 951         /* Get the codec into a known state */
 952         ret = wm8580_write(codec, WM8580_RESET, 0);
 953         if (ret != 0) {
 954                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 955                 goto err_regulator_enable;
 956         }
 957
 958         for (i = 0; i < ARRAY_SIZE(wm8580_dai); i++)
 959                 wm8580_dai[i].dev = codec->dev;
 960
 961         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 962
 963         wm8580_codec = codec;
 964
 965         ret = snd_soc_register_codec(codec);
 966         if (ret != 0) {
 967                 dev_err(codec->dev, "Failed to register codec: %d\n", ret);
 968                 goto err_regulator_enable;
 969         }
 970
 971         ret = snd_soc_register_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 972         if (ret != 0) {
 973                 dev_err(codec->dev, "Failed to register DAI: %d\n", ret);
 974                 goto err_codec;
 975         }
 976
 977         return 0;
 978
 979 err_codec:
 980         snd_soc_unregister_codec(codec);
 981 err_regulator_enable:
 982         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 983 err_regulator_get:
 984         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 985 err:
 986         kfree(wm8580);
 987         return ret;
 988 }
 989
 990 static void wm8580_unregister(struct wm8580_priv *wm8580)
 991 {
 992         wm8580_set_bias_level(&wm8580->codec, SND_SOC_BIAS_OFF);
 993         snd_soc_unregister_dais(wm8580_dai, ARRAY_SIZE(wm8580_dai));
 994         snd_soc_unregister_codec(&wm8580->codec);
 995         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 996         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 997         kfree(wm8580);
 998         wm8580_codec = NULL;
 999 }
1000
1001 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1002 static int wm8580_i2c_probe(struct i2c_client *i2c,
1003                             const struct i2c_device_id *id)
1004 {
1005         struct wm8580_priv *wm8580;
1006         struct snd_soc_codec *codec;
1007
1008         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
1009         if (wm8580 == NULL)
1010                 return -ENOMEM;
1011
1012         codec = &wm8580->codec;
1013         codec->hw_write = (hw_write_t)i2c_master_send;
1014
1015         i2c_set_clientdata(i2c, wm8580);
1016         codec->control_data = i2c;
1017
1018         codec->dev = &i2c->dev;
1019
1020         return wm8580_register(wm8580);
1021 }
1022
1023 static int wm8580_i2c_remove(struct i2c_client *client)
1024 {
1025         struct wm8580_priv *wm8580 = i2c_get_clientdata(client);
1026         wm8580_unregister(wm8580);
1027         return 0;
1028 }
1029
1030 #ifdef CONFIG_PM
1031 static int wm8580_i2c_suspend(struct i2c_client *client, pm_message_t msg)
1032 {
1033         return snd_soc_suspend_device(&client->dev);
1034 }
1035
1036 static int wm8580_i2c_resume(struct i2c_client *client)
1037 {
1038         return snd_soc_resume_device(&client->dev);
1039 }
1040 #else
1041 #define wm8580_i2c_suspend NULL
1042 #define wm8580_i2c_resume NULL
1043 #endif
1044
1045 static const struct i2c_device_id wm8580_i2c_id[] = {
1046         { "wm8580", 0 },
1047         { }
1048 };
1049 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
1050
1051 static struct i2c_driver wm8580_i2c_driver = {
1052         .driver = {
1053                 .name = "wm8580",
1054                 .owner = THIS_MODULE,
1055         },
1056         .probe =    wm8580_i2c_probe,
1057         .remove =   wm8580_i2c_remove,
1058         .suspend =  wm8580_i2c_suspend,
1059         .resume =   wm8580_i2c_resume,
1060         .id_table = wm8580_i2c_id,
1061 };
1062 #endif
1063
1064 static int __init wm8580_modinit(void)
1065 {
1066         int ret;
1067
1068 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1069         ret = i2c_add_driver(&wm8580_i2c_driver);
1070         if (ret != 0) {
1071                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
1072         }
1073 #endif
1074
1075         return 0;
1076 }
1077 module_init(wm8580_modinit);
1078
1079 static void __exit wm8580_exit(void)
1080 {
1081 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
1082         i2c_del_driver(&wm8580_i2c_driver);
1083 #endif
1084 }
1085 module_exit(wm8580_exit);
1086
1087 MODULE_DESCRIPTION("ASoC WM8580 driver");
1088 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
1089 MODULE_LICENSE("GPL");