1 // SPDX-License-Identifier: GPL-2.0
2 // TLV320ADCX140 Sound driver
3 // Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
5 #include <linux/module.h>
6 #include <linux/moduleparam.h>
7 #include <linux/init.h>
8 #include <linux/delay.h>
10 #include <linux/i2c.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/acpi.h>
15 #include <linux/of_gpio.h>
16 #include <linux/slab.h>
17 #include <sound/core.h>
18 #include <sound/pcm.h>
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/initval.h>
22 #include <sound/tlv.h>
24 #include "tlv320adcx140.h"
27 struct snd_soc_component *component;
28 struct regulator *supply_areg;
29 struct gpio_desc *gpio_reset;
30 struct regmap *regmap;
36 unsigned int slot_width;
39 static const char * const gpo_config_names[] = {
46 static const struct reg_default adcx140_reg_defaults[] = {
47 { ADCX140_PAGE_SELECT, 0x00 },
48 { ADCX140_SW_RESET, 0x00 },
49 { ADCX140_SLEEP_CFG, 0x00 },
50 { ADCX140_SHDN_CFG, 0x05 },
51 { ADCX140_ASI_CFG0, 0x30 },
52 { ADCX140_ASI_CFG1, 0x00 },
53 { ADCX140_ASI_CFG2, 0x00 },
54 { ADCX140_ASI_CH1, 0x00 },
55 { ADCX140_ASI_CH2, 0x01 },
56 { ADCX140_ASI_CH3, 0x02 },
57 { ADCX140_ASI_CH4, 0x03 },
58 { ADCX140_ASI_CH5, 0x04 },
59 { ADCX140_ASI_CH6, 0x05 },
60 { ADCX140_ASI_CH7, 0x06 },
61 { ADCX140_ASI_CH8, 0x07 },
62 { ADCX140_MST_CFG0, 0x02 },
63 { ADCX140_MST_CFG1, 0x48 },
64 { ADCX140_ASI_STS, 0xff },
65 { ADCX140_CLK_SRC, 0x10 },
66 { ADCX140_PDMCLK_CFG, 0x40 },
67 { ADCX140_PDM_CFG, 0x00 },
68 { ADCX140_GPIO_CFG0, 0x22 },
69 { ADCX140_GPO_CFG0, 0x00 },
70 { ADCX140_GPO_CFG1, 0x00 },
71 { ADCX140_GPO_CFG2, 0x00 },
72 { ADCX140_GPO_CFG3, 0x00 },
73 { ADCX140_GPO_VAL, 0x00 },
74 { ADCX140_GPIO_MON, 0x00 },
75 { ADCX140_GPI_CFG0, 0x00 },
76 { ADCX140_GPI_CFG1, 0x00 },
77 { ADCX140_GPI_MON, 0x00 },
78 { ADCX140_INT_CFG, 0x00 },
79 { ADCX140_INT_MASK0, 0xff },
80 { ADCX140_INT_LTCH0, 0x00 },
81 { ADCX140_BIAS_CFG, 0x00 },
82 { ADCX140_CH1_CFG0, 0x00 },
83 { ADCX140_CH1_CFG1, 0x00 },
84 { ADCX140_CH1_CFG2, 0xc9 },
85 { ADCX140_CH1_CFG3, 0x80 },
86 { ADCX140_CH1_CFG4, 0x00 },
87 { ADCX140_CH2_CFG0, 0x00 },
88 { ADCX140_CH2_CFG1, 0x00 },
89 { ADCX140_CH2_CFG2, 0xc9 },
90 { ADCX140_CH2_CFG3, 0x80 },
91 { ADCX140_CH2_CFG4, 0x00 },
92 { ADCX140_CH3_CFG0, 0x00 },
93 { ADCX140_CH3_CFG1, 0x00 },
94 { ADCX140_CH3_CFG2, 0xc9 },
95 { ADCX140_CH3_CFG3, 0x80 },
96 { ADCX140_CH3_CFG4, 0x00 },
97 { ADCX140_CH4_CFG0, 0x00 },
98 { ADCX140_CH4_CFG1, 0x00 },
99 { ADCX140_CH4_CFG2, 0xc9 },
100 { ADCX140_CH4_CFG3, 0x80 },
101 { ADCX140_CH4_CFG4, 0x00 },
102 { ADCX140_CH5_CFG2, 0xc9 },
103 { ADCX140_CH5_CFG3, 0x80 },
104 { ADCX140_CH5_CFG4, 0x00 },
105 { ADCX140_CH6_CFG2, 0xc9 },
106 { ADCX140_CH6_CFG3, 0x80 },
107 { ADCX140_CH6_CFG4, 0x00 },
108 { ADCX140_CH7_CFG2, 0xc9 },
109 { ADCX140_CH7_CFG3, 0x80 },
110 { ADCX140_CH7_CFG4, 0x00 },
111 { ADCX140_CH8_CFG2, 0xc9 },
112 { ADCX140_CH8_CFG3, 0x80 },
113 { ADCX140_CH8_CFG4, 0x00 },
114 { ADCX140_DSP_CFG0, 0x01 },
115 { ADCX140_DSP_CFG1, 0x40 },
116 { ADCX140_DRE_CFG0, 0x7b },
117 { ADCX140_AGC_CFG0, 0xe7 },
118 { ADCX140_IN_CH_EN, 0xf0 },
119 { ADCX140_ASI_OUT_CH_EN, 0x00 },
120 { ADCX140_PWR_CFG, 0x00 },
121 { ADCX140_DEV_STS0, 0x00 },
122 { ADCX140_DEV_STS1, 0x80 },
125 static const struct regmap_range_cfg adcx140_ranges[] = {
128 .range_max = 12 * 128,
129 .selector_reg = ADCX140_PAGE_SELECT,
130 .selector_mask = 0xff,
137 static bool adcx140_volatile(struct device *dev, unsigned int reg)
140 case ADCX140_SW_RESET:
141 case ADCX140_DEV_STS0:
142 case ADCX140_DEV_STS1:
143 case ADCX140_ASI_STS:
150 static const struct regmap_config adcx140_i2c_regmap = {
153 .reg_defaults = adcx140_reg_defaults,
154 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
155 .cache_type = REGCACHE_FLAT,
156 .ranges = adcx140_ranges,
157 .num_ranges = ARRAY_SIZE(adcx140_ranges),
158 .max_register = 12 * 128,
159 .volatile_reg = adcx140_volatile,
162 /* Digital Volume control. From -100 to 27 dB in 0.5 dB steps */
163 static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10050, 50, 0);
165 /* ADC gain. From 0 to 42 dB in 1 dB steps */
166 static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
168 /* DRE Level. From -12 dB to -66 dB in 1 dB steps */
169 static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
170 /* DRE Max Gain. From 2 dB to 26 dB in 2 dB steps */
171 static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
173 /* AGC Level. From -6 dB to -36 dB in 2 dB steps */
174 static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
175 /* AGC Max Gain. From 3 dB to 42 dB in 3 dB steps */
176 static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
178 static const char * const decimation_filter_text[] = {
179 "Linear Phase", "Low Latency", "Ultra-low Latency"
182 static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
183 decimation_filter_text);
185 static const struct snd_kcontrol_new decimation_filter_controls[] = {
186 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
189 static const char * const pdmclk_text[] = {
190 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
193 static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
196 static const struct snd_kcontrol_new pdmclk_div_controls[] = {
197 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
200 static const char * const resistor_text[] = {
201 "2.5 kOhm", "10 kOhm", "20 kOhm"
204 static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
206 static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
208 static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
210 static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
213 static const struct snd_kcontrol_new in1_resistor_controls[] = {
214 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
216 static const struct snd_kcontrol_new in2_resistor_controls[] = {
217 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
219 static const struct snd_kcontrol_new in3_resistor_controls[] = {
220 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
222 static const struct snd_kcontrol_new in4_resistor_controls[] = {
223 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
226 /* Analog/Digital Selection */
227 static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
228 static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
230 static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
232 adcx140_mic_sel_text);
234 static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
235 SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
237 static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
239 adcx140_analog_sel_text);
241 static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
242 SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
244 static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
246 adcx140_mic_sel_text);
248 static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
249 SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
251 static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
253 adcx140_mic_sel_text);
255 static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
256 SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
258 static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
260 adcx140_analog_sel_text);
262 static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
263 SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
265 static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
267 adcx140_mic_sel_text);
269 static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
270 SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
272 static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
274 adcx140_mic_sel_text);
276 static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
277 SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
279 static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
281 adcx140_analog_sel_text);
283 static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
284 SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
286 static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
288 adcx140_mic_sel_text);
290 static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
291 SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
293 static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
295 adcx140_mic_sel_text);
297 static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
298 SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
300 static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
302 adcx140_analog_sel_text);
304 static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
305 SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
307 static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
309 adcx140_mic_sel_text);
311 static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
312 SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
314 static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
315 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
316 static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
317 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
318 static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
319 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
320 static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
321 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
322 static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
323 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
324 static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
325 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
326 static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
327 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
328 static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
329 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
331 static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
332 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
333 static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
334 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
335 static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
336 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
337 static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
338 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
340 static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
341 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
344 static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
345 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
346 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
347 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
348 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
351 static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
352 /* Analog Differential Inputs */
353 SND_SOC_DAPM_INPUT("MIC1P"),
354 SND_SOC_DAPM_INPUT("MIC1M"),
355 SND_SOC_DAPM_INPUT("MIC2P"),
356 SND_SOC_DAPM_INPUT("MIC2M"),
357 SND_SOC_DAPM_INPUT("MIC3P"),
358 SND_SOC_DAPM_INPUT("MIC3M"),
359 SND_SOC_DAPM_INPUT("MIC4P"),
360 SND_SOC_DAPM_INPUT("MIC4M"),
362 SND_SOC_DAPM_OUTPUT("CH1_OUT"),
363 SND_SOC_DAPM_OUTPUT("CH2_OUT"),
364 SND_SOC_DAPM_OUTPUT("CH3_OUT"),
365 SND_SOC_DAPM_OUTPUT("CH4_OUT"),
366 SND_SOC_DAPM_OUTPUT("CH5_OUT"),
367 SND_SOC_DAPM_OUTPUT("CH6_OUT"),
368 SND_SOC_DAPM_OUTPUT("CH7_OUT"),
369 SND_SOC_DAPM_OUTPUT("CH8_OUT"),
371 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
372 &adcx140_output_mixer_controls[0],
373 ARRAY_SIZE(adcx140_output_mixer_controls)),
375 /* Input Selection to MIC_PGA */
376 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
377 &adcx140_dapm_mic1p_control),
378 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
379 &adcx140_dapm_mic2p_control),
380 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
381 &adcx140_dapm_mic3p_control),
382 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
383 &adcx140_dapm_mic4p_control),
385 /* Input Selection to MIC_PGA */
386 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
387 &adcx140_dapm_mic1_analog_control),
388 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
389 &adcx140_dapm_mic2_analog_control),
390 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
391 &adcx140_dapm_mic3_analog_control),
392 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
393 &adcx140_dapm_mic4_analog_control),
395 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
396 &adcx140_dapm_mic1m_control),
397 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
398 &adcx140_dapm_mic2m_control),
399 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
400 &adcx140_dapm_mic3m_control),
401 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
402 &adcx140_dapm_mic4m_control),
404 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
407 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
409 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
410 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
411 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
412 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
414 SND_SOC_DAPM_ADC("CH1_DIG", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
415 SND_SOC_DAPM_ADC("CH2_DIG", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
416 SND_SOC_DAPM_ADC("CH3_DIG", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
417 SND_SOC_DAPM_ADC("CH4_DIG", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
418 SND_SOC_DAPM_ADC("CH5_DIG", "CH5 Capture", ADCX140_IN_CH_EN, 3, 0),
419 SND_SOC_DAPM_ADC("CH6_DIG", "CH6 Capture", ADCX140_IN_CH_EN, 2, 0),
420 SND_SOC_DAPM_ADC("CH7_DIG", "CH7 Capture", ADCX140_IN_CH_EN, 1, 0),
421 SND_SOC_DAPM_ADC("CH8_DIG", "CH8 Capture", ADCX140_IN_CH_EN, 0, 0),
424 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
425 &adcx140_dapm_ch1_en_switch),
426 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
427 &adcx140_dapm_ch2_en_switch),
428 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
429 &adcx140_dapm_ch3_en_switch),
430 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
431 &adcx140_dapm_ch4_en_switch),
433 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
434 &adcx140_dapm_ch5_en_switch),
435 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
436 &adcx140_dapm_ch6_en_switch),
437 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
438 &adcx140_dapm_ch7_en_switch),
439 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
440 &adcx140_dapm_ch8_en_switch),
442 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
443 &adcx140_dapm_dre_en_switch),
445 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
446 &adcx140_dapm_ch1_dre_en_switch),
447 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
448 &adcx140_dapm_ch2_dre_en_switch),
449 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
450 &adcx140_dapm_ch3_dre_en_switch),
451 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
452 &adcx140_dapm_ch4_dre_en_switch),
454 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
455 in1_resistor_controls),
456 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
457 in2_resistor_controls),
458 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
459 in3_resistor_controls),
460 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
461 in4_resistor_controls),
463 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
464 pdmclk_div_controls),
466 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
467 decimation_filter_controls),
470 static const struct snd_soc_dapm_route adcx140_audio_map[] = {
472 {"CH1_OUT", NULL, "Output Mixer"},
473 {"CH2_OUT", NULL, "Output Mixer"},
474 {"CH3_OUT", NULL, "Output Mixer"},
475 {"CH4_OUT", NULL, "Output Mixer"},
477 {"CH1_ASI_EN", "Switch", "CH1_ADC"},
478 {"CH2_ASI_EN", "Switch", "CH2_ADC"},
479 {"CH3_ASI_EN", "Switch", "CH3_ADC"},
480 {"CH4_ASI_EN", "Switch", "CH4_ADC"},
482 {"CH1_ASI_EN", "Switch", "CH1_DIG"},
483 {"CH2_ASI_EN", "Switch", "CH2_DIG"},
484 {"CH3_ASI_EN", "Switch", "CH3_DIG"},
485 {"CH4_ASI_EN", "Switch", "CH4_DIG"},
486 {"CH5_ASI_EN", "Switch", "CH5_DIG"},
487 {"CH6_ASI_EN", "Switch", "CH6_DIG"},
488 {"CH7_ASI_EN", "Switch", "CH7_DIG"},
489 {"CH8_ASI_EN", "Switch", "CH8_DIG"},
491 {"CH5_ASI_EN", "Switch", "CH5_OUT"},
492 {"CH6_ASI_EN", "Switch", "CH6_OUT"},
493 {"CH7_ASI_EN", "Switch", "CH7_OUT"},
494 {"CH8_ASI_EN", "Switch", "CH8_OUT"},
496 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
497 {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
498 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
500 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
501 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
502 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
503 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
505 {"CH1_DRE_EN", "Switch", "CH1_ADC"},
506 {"CH2_DRE_EN", "Switch", "CH2_ADC"},
507 {"CH3_DRE_EN", "Switch", "CH3_ADC"},
508 {"CH4_DRE_EN", "Switch", "CH4_ADC"},
511 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
512 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
513 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
514 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
516 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
517 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
518 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
519 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
520 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
521 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
522 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
523 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
525 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
526 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
527 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
529 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
530 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
531 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
533 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
534 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
535 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
537 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
538 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
539 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
541 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
542 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
543 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
545 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
546 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
547 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
549 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
550 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
551 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
553 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
554 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
555 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
557 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
558 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
559 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
560 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
562 {"MIC1P Input Mux", NULL, "CH1_DIG"},
563 {"MIC1M Input Mux", NULL, "CH2_DIG"},
564 {"MIC2P Input Mux", NULL, "CH3_DIG"},
565 {"MIC2M Input Mux", NULL, "CH4_DIG"},
566 {"MIC3P Input Mux", NULL, "CH5_DIG"},
567 {"MIC3M Input Mux", NULL, "CH6_DIG"},
568 {"MIC4P Input Mux", NULL, "CH7_DIG"},
569 {"MIC4M Input Mux", NULL, "CH8_DIG"},
571 {"MIC1 Analog Mux", "Line In", "MIC1P"},
572 {"MIC2 Analog Mux", "Line In", "MIC2P"},
573 {"MIC3 Analog Mux", "Line In", "MIC3P"},
574 {"MIC4 Analog Mux", "Line In", "MIC4P"},
576 {"MIC1P Input Mux", "Analog", "MIC1P"},
577 {"MIC1M Input Mux", "Analog", "MIC1M"},
578 {"MIC2P Input Mux", "Analog", "MIC2P"},
579 {"MIC2M Input Mux", "Analog", "MIC2M"},
580 {"MIC3P Input Mux", "Analog", "MIC3P"},
581 {"MIC3M Input Mux", "Analog", "MIC3M"},
582 {"MIC4P Input Mux", "Analog", "MIC4P"},
583 {"MIC4M Input Mux", "Analog", "MIC4M"},
585 {"MIC1P Input Mux", "Digital", "MIC1P"},
586 {"MIC1M Input Mux", "Digital", "MIC1M"},
587 {"MIC2P Input Mux", "Digital", "MIC2P"},
588 {"MIC2M Input Mux", "Digital", "MIC2M"},
589 {"MIC3P Input Mux", "Digital", "MIC3P"},
590 {"MIC3M Input Mux", "Digital", "MIC3M"},
591 {"MIC4P Input Mux", "Digital", "MIC4P"},
592 {"MIC4M Input Mux", "Digital", "MIC4M"},
595 static const struct snd_kcontrol_new adcx140_snd_controls[] = {
596 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
598 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
600 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
602 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
605 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
607 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
610 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
612 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
615 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
616 0, 0xff, 0, dig_vol_tlv),
617 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
618 0, 0xff, 0, dig_vol_tlv),
619 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
620 0, 0xff, 0, dig_vol_tlv),
621 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
622 0, 0xff, 0, dig_vol_tlv),
623 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
624 0, 0xff, 0, dig_vol_tlv),
625 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
626 0, 0xff, 0, dig_vol_tlv),
627 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
628 0, 0xff, 0, dig_vol_tlv),
629 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
630 0, 0xff, 0, dig_vol_tlv),
633 static int adcx140_reset(struct adcx140_priv *adcx140)
637 if (adcx140->gpio_reset) {
638 gpiod_direction_output(adcx140->gpio_reset, 0);
639 /* 8.4.1: wait for hw shutdown (25ms) + >= 1ms */
640 usleep_range(30000, 100000);
641 gpiod_direction_output(adcx140->gpio_reset, 1);
643 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
647 /* 8.4.2: wait >= 10 ms after entering sleep mode. */
648 usleep_range(10000, 100000);
653 static void adcx140_pwr_ctrl(struct adcx140_priv *adcx140, bool power_state)
658 pwr_ctrl = ADCX140_PWR_CFG_ADC_PDZ | ADCX140_PWR_CFG_PLL_PDZ;
660 if (adcx140->micbias_vg && power_state)
661 pwr_ctrl |= ADCX140_PWR_CFG_BIAS_PDZ;
663 regmap_update_bits(adcx140->regmap, ADCX140_PWR_CFG,
664 ADCX140_PWR_CTRL_MSK, pwr_ctrl);
667 static int adcx140_hw_params(struct snd_pcm_substream *substream,
668 struct snd_pcm_hw_params *params,
669 struct snd_soc_dai *dai)
671 struct snd_soc_component *component = dai->component;
672 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
675 switch (params_width(params)) {
677 data = ADCX140_16_BIT_WORD;
680 data = ADCX140_20_BIT_WORD;
683 data = ADCX140_24_BIT_WORD;
686 data = ADCX140_32_BIT_WORD;
689 dev_err(component->dev, "%s: Unsupported width %d\n",
690 __func__, params_width(params));
694 adcx140_pwr_ctrl(adcx140, false);
696 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
697 ADCX140_WORD_LEN_MSK, data);
699 adcx140_pwr_ctrl(adcx140, true);
704 static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
707 struct snd_soc_component *component = codec_dai->component;
708 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
712 bool inverted_bclk = false;
714 /* set master/slave audio interface */
715 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
716 case SND_SOC_DAIFMT_CBM_CFM:
717 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
719 case SND_SOC_DAIFMT_CBS_CFS:
721 case SND_SOC_DAIFMT_CBS_CFM:
722 case SND_SOC_DAIFMT_CBM_CFS:
724 dev_err(component->dev, "Invalid DAI master/slave interface\n");
728 /* interface format */
729 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
730 case SND_SOC_DAIFMT_I2S:
731 iface_reg1 |= ADCX140_I2S_MODE_BIT;
733 case SND_SOC_DAIFMT_LEFT_J:
734 iface_reg1 |= ADCX140_LEFT_JUST_BIT;
736 case SND_SOC_DAIFMT_DSP_A:
738 inverted_bclk = true;
740 case SND_SOC_DAIFMT_DSP_B:
741 inverted_bclk = true;
744 dev_err(component->dev, "Invalid DAI interface format\n");
748 /* signal polarity */
749 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
750 case SND_SOC_DAIFMT_IB_NF:
751 case SND_SOC_DAIFMT_IB_IF:
752 inverted_bclk = !inverted_bclk;
754 case SND_SOC_DAIFMT_NB_IF:
755 iface_reg1 |= ADCX140_FSYNCINV_BIT;
757 case SND_SOC_DAIFMT_NB_NF:
760 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
765 iface_reg1 |= ADCX140_BCLKINV_BIT;
767 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
769 adcx140_pwr_ctrl(adcx140, false);
771 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
772 ADCX140_FSYNCINV_BIT |
773 ADCX140_BCLKINV_BIT |
774 ADCX140_ASI_FORMAT_MSK,
776 snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
777 ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
779 /* Configure data offset */
780 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
781 ADCX140_TX_OFFSET_MASK, offset);
783 adcx140_pwr_ctrl(adcx140, true);
788 static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
789 unsigned int tx_mask, unsigned int rx_mask,
790 int slots, int slot_width)
792 struct snd_soc_component *component = codec_dai->component;
793 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
796 * The chip itself supports arbitrary masks, but the driver currently
797 * only supports adjacent slots beginning at the first slot.
799 if (tx_mask != GENMASK(__fls(tx_mask), 0)) {
800 dev_err(component->dev, "Only lower adjacent slots are supported\n");
804 switch (slot_width) {
811 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
815 adcx140->slot_width = slot_width;
820 static const struct snd_soc_dai_ops adcx140_dai_ops = {
821 .hw_params = adcx140_hw_params,
822 .set_fmt = adcx140_set_dai_fmt,
823 .set_tdm_slot = adcx140_set_dai_tdm_slot,
826 static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
828 u32 gpo_outputs[ADCX140_NUM_GPOS];
829 u32 gpo_output_val = 0;
833 for (i = 0; i < ADCX140_NUM_GPOS; i++) {
834 ret = device_property_read_u32_array(adcx140->dev,
837 ADCX140_NUM_GPO_CFGS);
841 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
842 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
846 if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
847 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
851 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
853 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
863 static int adcx140_configure_gpio(struct adcx140_priv *adcx140)
866 u32 gpio_outputs[ADCX140_NUM_GPIO_CFGS];
867 u32 gpio_output_val = 0;
870 gpio_count = device_property_count_u32(adcx140->dev,
875 if (gpio_count != ADCX140_NUM_GPIO_CFGS)
878 ret = device_property_read_u32_array(adcx140->dev, "ti,gpio-config",
879 gpio_outputs, gpio_count);
883 if (gpio_outputs[0] > ADCX140_GPIO_CFG_MAX) {
884 dev_err(adcx140->dev, "GPIO config out of range\n");
888 if (gpio_outputs[1] > ADCX140_GPIO_DRV_MAX) {
889 dev_err(adcx140->dev, "GPIO drive out of range\n");
893 gpio_output_val = gpio_outputs[0] << ADCX140_GPIO_SHIFT
896 return regmap_write(adcx140->regmap, ADCX140_GPIO_CFG0, gpio_output_val);
899 static int adcx140_codec_probe(struct snd_soc_component *component)
901 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
902 int sleep_cfg_val = ADCX140_WAKE_DEV;
907 u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
908 u32 pdm_edge_val = 0;
910 u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
911 u32 gpi_input_val = 0;
916 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
918 if (ret || bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
919 bias_source = ADCX140_MIC_BIAS_VAL_VREF;
920 adcx140->micbias_vg = false;
922 adcx140->micbias_vg = true;
925 ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
928 vref_source = ADCX140_MIC_BIAS_VREF_275V;
930 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
931 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
935 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
937 ret = adcx140_reset(adcx140);
941 if (adcx140->supply_areg == NULL)
942 sleep_cfg_val |= ADCX140_AREG_INTERNAL;
944 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
946 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
950 /* 8.4.3: Wait >= 1ms after entering active mode. */
951 usleep_range(1000, 100000);
953 pdm_count = device_property_count_u32(adcx140->dev,
954 "ti,pdm-edge-select");
955 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
956 ret = device_property_read_u32_array(adcx140->dev,
957 "ti,pdm-edge-select",
958 pdm_edges, pdm_count);
962 for (i = 0; i < pdm_count; i++)
963 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
965 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
971 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
972 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
973 ret = device_property_read_u32_array(adcx140->dev,
975 gpi_inputs, gpi_count);
979 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
980 gpi_inputs[ADCX140_GPI2_INDEX];
982 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
987 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
988 gpi_inputs[ADCX140_GPI4_INDEX];
990 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
996 ret = adcx140_configure_gpio(adcx140);
1000 ret = adcx140_configure_gpo(adcx140);
1004 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
1005 ADCX140_MIC_BIAS_VAL_MSK |
1006 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
1008 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
1010 tx_high_z = device_property_read_bool(adcx140->dev, "ti,asi-tx-drive");
1012 ret = regmap_update_bits(adcx140->regmap, ADCX140_ASI_CFG0,
1013 ADCX140_TX_FILL, ADCX140_TX_FILL);
1015 dev_err(adcx140->dev, "Setting Tx drive failed %d\n", ret);
1020 adcx140_pwr_ctrl(adcx140, true);
1025 static int adcx140_set_bias_level(struct snd_soc_component *component,
1026 enum snd_soc_bias_level level)
1028 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
1031 case SND_SOC_BIAS_ON:
1032 case SND_SOC_BIAS_PREPARE:
1033 case SND_SOC_BIAS_STANDBY:
1034 adcx140_pwr_ctrl(adcx140, true);
1036 case SND_SOC_BIAS_OFF:
1037 adcx140_pwr_ctrl(adcx140, false);
1044 static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
1045 .probe = adcx140_codec_probe,
1046 .set_bias_level = adcx140_set_bias_level,
1047 .controls = adcx140_snd_controls,
1048 .num_controls = ARRAY_SIZE(adcx140_snd_controls),
1049 .dapm_widgets = adcx140_dapm_widgets,
1050 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
1051 .dapm_routes = adcx140_audio_map,
1052 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
1053 .suspend_bias_off = 1,
1055 .use_pmdown_time = 1,
1057 .non_legacy_dai_naming = 1,
1060 static struct snd_soc_dai_driver adcx140_dai_driver[] = {
1062 .name = "tlv320adcx140-codec",
1064 .stream_name = "Capture",
1066 .channels_max = ADCX140_MAX_CHANNELS,
1067 .rates = ADCX140_RATES,
1068 .formats = ADCX140_FORMATS,
1070 .ops = &adcx140_dai_ops,
1071 .symmetric_rate = 1,
1076 static const struct of_device_id tlv320adcx140_of_match[] = {
1077 { .compatible = "ti,tlv320adc3140" },
1078 { .compatible = "ti,tlv320adc5140" },
1079 { .compatible = "ti,tlv320adc6140" },
1082 MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
1085 static void adcx140_disable_regulator(void *arg)
1087 struct adcx140_priv *adcx140 = arg;
1089 regulator_disable(adcx140->supply_areg);
1092 static int adcx140_i2c_probe(struct i2c_client *i2c)
1094 struct adcx140_priv *adcx140;
1097 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
1101 adcx140->dev = &i2c->dev;
1103 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
1104 "reset", GPIOD_OUT_LOW);
1105 if (IS_ERR(adcx140->gpio_reset))
1106 dev_info(&i2c->dev, "Reset GPIO not defined\n");
1108 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
1110 if (IS_ERR(adcx140->supply_areg)) {
1111 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
1112 return -EPROBE_DEFER;
1114 adcx140->supply_areg = NULL;
1116 ret = regulator_enable(adcx140->supply_areg);
1118 dev_err(adcx140->dev, "Failed to enable areg\n");
1122 ret = devm_add_action_or_reset(&i2c->dev, adcx140_disable_regulator, adcx140);
1127 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1128 if (IS_ERR(adcx140->regmap)) {
1129 ret = PTR_ERR(adcx140->regmap);
1130 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1135 i2c_set_clientdata(i2c, adcx140);
1137 return devm_snd_soc_register_component(&i2c->dev,
1138 &soc_codec_driver_adcx140,
1139 adcx140_dai_driver, 1);
1142 static const struct i2c_device_id adcx140_i2c_id[] = {
1143 { "tlv320adc3140", 0 },
1144 { "tlv320adc5140", 1 },
1145 { "tlv320adc6140", 2 },
1148 MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
1150 static struct i2c_driver adcx140_i2c_driver = {
1152 .name = "tlv320adcx140-codec",
1153 .of_match_table = of_match_ptr(tlv320adcx140_of_match),
1155 .probe_new = adcx140_i2c_probe,
1156 .id_table = adcx140_i2c_id,
1158 module_i2c_driver(adcx140_i2c_driver);
1160 MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1161 MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1162 MODULE_LICENSE("GPL v2");