sound/soc/codecs/rt5514.c

   1 /*
   2  * rt5514.c  --  RT5514 ALSA SoC audio codec driver
   3  *
   4  * Copyright 2015 Realtek Semiconductor Corp.
   5  * Author: Oder Chiou <oder_chiou@realtek.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/fs.h>
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/delay.h>
  17 #include <linux/pm.h>
  18 #include <linux/regmap.h>
  19 #include <linux/i2c.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/firmware.h>
  22 #include <linux/gpio.h>
  23 #include <sound/core.h>
  24 #include <sound/pcm.h>
  25 #include <sound/pcm_params.h>
  26 #include <sound/soc.h>
  27 #include <sound/soc-dapm.h>
  28 #include <sound/initval.h>
  29 #include <sound/tlv.h>
  30
  31 #include "rl6231.h"
  32 #include "rt5514.h"
  33 #if defined(CONFIG_SND_SOC_RT5514_SPI)
  34 #include "rt5514-spi.h"
  35 #endif
  36
  37 static const struct reg_sequence rt5514_i2c_patch[] = {
  38         {0x1800101c, 0x00000000},
  39         {0x18001100, 0x0000031f},
  40         {0x18001104, 0x00000007},
  41         {0x18001108, 0x00000000},
  42         {0x1800110c, 0x00000000},
  43         {0x18001110, 0x00000000},
  44         {0x18001114, 0x00000001},
  45         {0x18001118, 0x00000000},
  46         {0x18002f08, 0x00000006},
  47         {0x18002f00, 0x00055149},
  48         {0x18002f00, 0x0005514b},
  49         {0x18002f00, 0x00055149},
  50         {0xfafafafa, 0x00000001},
  51         {0x18002f10, 0x00000001},
  52         {0x18002f10, 0x00000000},
  53         {0x18002f10, 0x00000001},
  54         {0xfafafafa, 0x00000001},
  55         {0x18002000, 0x000010ec},
  56         {0xfafafafa, 0x00000000},
  57 };
  58
  59 static const struct reg_sequence rt5514_patch[] = {
  60         {RT5514_DIG_IO_CTRL,            0x00000040},
  61         {RT5514_CLK_CTRL1,              0x38020041},
  62         {RT5514_SRC_CTRL,               0x44000eee},
  63         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  64         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
  65 };
  66
  67 static const struct reg_default rt5514_reg[] = {
  68         {RT5514_RESET,                  0x00000000},
  69         {RT5514_PWR_ANA1,               0x00808880},
  70         {RT5514_PWR_ANA2,               0x00220000},
  71         {RT5514_I2S_CTRL1,              0x00000330},
  72         {RT5514_I2S_CTRL2,              0x20000000},
  73         {RT5514_VAD_CTRL6,              0xc00007d2},
  74         {RT5514_EXT_VAD_CTRL,           0x80000080},
  75         {RT5514_DIG_IO_CTRL,            0x00000040},
  76         {RT5514_PAD_CTRL1,              0x00804000},
  77         {RT5514_DMIC_DATA_CTRL,         0x00000005},
  78         {RT5514_DIG_SOURCE_CTRL,        0x00000002},
  79         {RT5514_SRC_CTRL,               0x44000eee},
  80         {RT5514_DOWNFILTER2_CTRL1,      0x0000882f},
  81         {RT5514_PLL_SOURCE_CTRL,        0x00000004},
  82         {RT5514_CLK_CTRL1,              0x38020041},
  83         {RT5514_CLK_CTRL2,              0x00000000},
  84         {RT5514_PLL3_CALIB_CTRL1,       0x00400200},
  85         {RT5514_PLL3_CALIB_CTRL5,       0x40220012},
  86         {RT5514_DELAY_BUF_CTRL1,        0x7fff006a},
  87         {RT5514_DELAY_BUF_CTRL3,        0x00000000},
  88         {RT5514_DOWNFILTER0_CTRL1,      0x00020c2f},
  89         {RT5514_DOWNFILTER0_CTRL2,      0x00020c2f},
  90         {RT5514_DOWNFILTER0_CTRL3,      0x00000362},
  91         {RT5514_DOWNFILTER1_CTRL1,      0x00020c2f},
  92         {RT5514_DOWNFILTER1_CTRL2,      0x00020c2f},
  93         {RT5514_DOWNFILTER1_CTRL3,      0x00000362},
  94         {RT5514_ANA_CTRL_LDO10,         0x00028604},
  95         {RT5514_ANA_CTRL_LDO18_16,      0x02000345},
  96         {RT5514_ANA_CTRL_ADC12,         0x0000a2a8},
  97         {RT5514_ANA_CTRL_ADC21,         0x00001180},
  98         {RT5514_ANA_CTRL_ADC22,         0x0000aaa8},
  99         {RT5514_ANA_CTRL_ADC23,         0x00151427},
 100         {RT5514_ANA_CTRL_MICBST,        0x00002000},
 101         {RT5514_ANA_CTRL_ADCFED,        0x00000800},
 102         {RT5514_ANA_CTRL_INBUF,         0x00000143},
 103         {RT5514_ANA_CTRL_VREF,          0x00008d50},
 104         {RT5514_ANA_CTRL_PLL3,          0x0000000e},
 105         {RT5514_ANA_CTRL_PLL1_1,        0x00000000},
 106         {RT5514_ANA_CTRL_PLL1_2,        0x00030220},
 107         {RT5514_DMIC_LP_CTRL,           0x00000000},
 108         {RT5514_MISC_CTRL_DSP,          0x00000000},
 109         {RT5514_DSP_CTRL1,              0x00055149},
 110         {RT5514_DSP_CTRL3,              0x00000006},
 111         {RT5514_DSP_CTRL4,              0x00000001},
 112         {RT5514_VENDOR_ID1,             0x00000001},
 113         {RT5514_VENDOR_ID2,             0x10ec5514},
 114 };
 115
 116 static void rt5514_enable_dsp_prepare(struct rt5514_priv *rt5514)
 117 {
 118         /* Reset */
 119         regmap_write(rt5514->i2c_regmap, 0x18002000, 0x000010ec);
 120         /* LDO_I_limit */
 121         regmap_write(rt5514->i2c_regmap, 0x18002200, 0x00028604);
 122         /* I2C bypass enable */
 123         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000001);
 124         /* mini-core reset */
 125         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x0005514b);
 126         regmap_write(rt5514->i2c_regmap, 0x18002f00, 0x00055149);
 127         /* I2C bypass disable */
 128         regmap_write(rt5514->i2c_regmap, 0xfafafafa, 0x00000000);
 129         /* PIN config */
 130         regmap_write(rt5514->i2c_regmap, 0x18002070, 0x00000040);
 131         /* PLL3(QN)=RCOSC*(10+2) */
 132         regmap_write(rt5514->i2c_regmap, 0x18002240, 0x0000000a);
 133         /* PLL3 source=RCOSC, fsi=rt_clk */
 134         regmap_write(rt5514->i2c_regmap, 0x18002100, 0x0000000b);
 135         /* Power on RCOSC, pll3 */
 136         regmap_write(rt5514->i2c_regmap, 0x18002004, 0x00808b81);
 137         /* DSP clk source = pll3, ENABLE DSP clk */
 138         regmap_write(rt5514->i2c_regmap, 0x18002f08, 0x00000005);
 139         /* Enable DSP clk auto switch */
 140         regmap_write(rt5514->i2c_regmap, 0x18001114, 0x00000001);
 141         /* Reduce DSP power */
 142         regmap_write(rt5514->i2c_regmap, 0x18001118, 0x00000001);
 143 }
 144
 145 static bool rt5514_volatile_register(struct device *dev, unsigned int reg)
 146 {
 147         switch (reg) {
 148         case RT5514_VENDOR_ID1:
 149         case RT5514_VENDOR_ID2:
 150                 return true;
 151
 152         default:
 153                 return false;
 154         }
 155 }
 156
 157 static bool rt5514_readable_register(struct device *dev, unsigned int reg)
 158 {
 159         switch (reg) {
 160         case RT5514_RESET:
 161         case RT5514_PWR_ANA1:
 162         case RT5514_PWR_ANA2:
 163         case RT5514_I2S_CTRL1:
 164         case RT5514_I2S_CTRL2:
 165         case RT5514_VAD_CTRL6:
 166         case RT5514_EXT_VAD_CTRL:
 167         case RT5514_DIG_IO_CTRL:
 168         case RT5514_PAD_CTRL1:
 169         case RT5514_DMIC_DATA_CTRL:
 170         case RT5514_DIG_SOURCE_CTRL:
 171         case RT5514_SRC_CTRL:
 172         case RT5514_DOWNFILTER2_CTRL1:
 173         case RT5514_PLL_SOURCE_CTRL:
 174         case RT5514_CLK_CTRL1:
 175         case RT5514_CLK_CTRL2:
 176         case RT5514_PLL3_CALIB_CTRL1:
 177         case RT5514_PLL3_CALIB_CTRL5:
 178         case RT5514_DELAY_BUF_CTRL1:
 179         case RT5514_DELAY_BUF_CTRL3:
 180         case RT5514_DOWNFILTER0_CTRL1:
 181         case RT5514_DOWNFILTER0_CTRL2:
 182         case RT5514_DOWNFILTER0_CTRL3:
 183         case RT5514_DOWNFILTER1_CTRL1:
 184         case RT5514_DOWNFILTER1_CTRL2:
 185         case RT5514_DOWNFILTER1_CTRL3:
 186         case RT5514_ANA_CTRL_LDO10:
 187         case RT5514_ANA_CTRL_LDO18_16:
 188         case RT5514_ANA_CTRL_ADC12:
 189         case RT5514_ANA_CTRL_ADC21:
 190         case RT5514_ANA_CTRL_ADC22:
 191         case RT5514_ANA_CTRL_ADC23:
 192         case RT5514_ANA_CTRL_MICBST:
 193         case RT5514_ANA_CTRL_ADCFED:
 194         case RT5514_ANA_CTRL_INBUF:
 195         case RT5514_ANA_CTRL_VREF:
 196         case RT5514_ANA_CTRL_PLL3:
 197         case RT5514_ANA_CTRL_PLL1_1:
 198         case RT5514_ANA_CTRL_PLL1_2:
 199         case RT5514_DMIC_LP_CTRL:
 200         case RT5514_MISC_CTRL_DSP:
 201         case RT5514_DSP_CTRL1:
 202         case RT5514_DSP_CTRL3:
 203         case RT5514_DSP_CTRL4:
 204         case RT5514_VENDOR_ID1:
 205         case RT5514_VENDOR_ID2:
 206                 return true;
 207
 208         default:
 209                 return false;
 210         }
 211 }
 212
 213 static bool rt5514_i2c_readable_register(struct device *dev,
 214         unsigned int reg)
 215 {
 216         switch (reg) {
 217         case RT5514_DSP_MAPPING | RT5514_RESET:
 218         case RT5514_DSP_MAPPING | RT5514_PWR_ANA1:
 219         case RT5514_DSP_MAPPING | RT5514_PWR_ANA2:
 220         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL1:
 221         case RT5514_DSP_MAPPING | RT5514_I2S_CTRL2:
 222         case RT5514_DSP_MAPPING | RT5514_VAD_CTRL6:
 223         case RT5514_DSP_MAPPING | RT5514_EXT_VAD_CTRL:
 224         case RT5514_DSP_MAPPING | RT5514_DIG_IO_CTRL:
 225         case RT5514_DSP_MAPPING | RT5514_PAD_CTRL1:
 226         case RT5514_DSP_MAPPING | RT5514_DMIC_DATA_CTRL:
 227         case RT5514_DSP_MAPPING | RT5514_DIG_SOURCE_CTRL:
 228         case RT5514_DSP_MAPPING | RT5514_SRC_CTRL:
 229         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER2_CTRL1:
 230         case RT5514_DSP_MAPPING | RT5514_PLL_SOURCE_CTRL:
 231         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL1:
 232         case RT5514_DSP_MAPPING | RT5514_CLK_CTRL2:
 233         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL1:
 234         case RT5514_DSP_MAPPING | RT5514_PLL3_CALIB_CTRL5:
 235         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL1:
 236         case RT5514_DSP_MAPPING | RT5514_DELAY_BUF_CTRL3:
 237         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL1:
 238         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL2:
 239         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER0_CTRL3:
 240         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL1:
 241         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL2:
 242         case RT5514_DSP_MAPPING | RT5514_DOWNFILTER1_CTRL3:
 243         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO10:
 244         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_LDO18_16:
 245         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC12:
 246         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC21:
 247         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC22:
 248         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADC23:
 249         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_MICBST:
 250         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_ADCFED:
 251         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_INBUF:
 252         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_VREF:
 253         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL3:
 254         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_1:
 255         case RT5514_DSP_MAPPING | RT5514_ANA_CTRL_PLL1_2:
 256         case RT5514_DSP_MAPPING | RT5514_DMIC_LP_CTRL:
 257         case RT5514_DSP_MAPPING | RT5514_MISC_CTRL_DSP:
 258         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL1:
 259         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL3:
 260         case RT5514_DSP_MAPPING | RT5514_DSP_CTRL4:
 261         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID1:
 262         case RT5514_DSP_MAPPING | RT5514_VENDOR_ID2:
 263                 return true;
 264
 265         default:
 266                 return false;
 267         }
 268 }
 269
 270 /* {-3, 0, +3, +4.5, +7.5, +9.5, +12, +14, +17} dB */
 271 static const DECLARE_TLV_DB_RANGE(bst_tlv,
 272         0, 2, TLV_DB_SCALE_ITEM(-300, 300, 0),
 273         3, 3, TLV_DB_SCALE_ITEM(450, 0, 0),
 274         4, 4, TLV_DB_SCALE_ITEM(750, 0, 0),
 275         5, 5, TLV_DB_SCALE_ITEM(950, 0, 0),
 276         6, 6, TLV_DB_SCALE_ITEM(1200, 0, 0),
 277         7, 7, TLV_DB_SCALE_ITEM(1400, 0, 0),
 278         8, 8, TLV_DB_SCALE_ITEM(1700, 0, 0)
 279 );
 280
 281 static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
 282
 283 static int rt5514_dsp_voice_wake_up_get(struct snd_kcontrol *kcontrol,
 284                 struct snd_ctl_elem_value *ucontrol)
 285 {
 286         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 287         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 288
 289         ucontrol->value.integer.value[0] = rt5514->dsp_enabled;
 290
 291         return 0;
 292 }
 293
 294 static int rt5514_dsp_voice_wake_up_put(struct snd_kcontrol *kcontrol,
 295                 struct snd_ctl_elem_value *ucontrol)
 296 {
 297         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 298         struct rt5514_priv *rt5514 = snd_soc_component_get_drvdata(component);
 299         struct snd_soc_codec *codec = rt5514->codec;
 300         const struct firmware *fw = NULL;
 301
 302         if (ucontrol->value.integer.value[0] == rt5514->dsp_enabled)
 303                 return 0;
 304
 305         if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 306                 rt5514->dsp_enabled = ucontrol->value.integer.value[0];
 307
 308                 if (rt5514->dsp_enabled) {
 309                         rt5514_enable_dsp_prepare(rt5514);
 310
 311                         request_firmware(&fw, RT5514_FIRMWARE1, codec->dev);
 312                         if (fw) {
 313 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 314                                 rt5514_spi_burst_write(0x4ff60000, fw->data,
 315                                         ((fw->size/8)+1)*8);
 316 #else
 317                                 dev_err(codec->dev, "There is no SPI driver for"
 318                                         " loading the firmware\n");
 319 #endif
 320                                 release_firmware(fw);
 321                                 fw = NULL;
 322                         }
 323
 324                         request_firmware(&fw, RT5514_FIRMWARE2, codec->dev);
 325                         if (fw) {
 326 #if defined(CONFIG_SND_SOC_RT5514_SPI)
 327                                 rt5514_spi_burst_write(0x4ffc0000, fw->data,
 328                                         ((fw->size/8)+1)*8);
 329 #else
 330                                 dev_err(codec->dev, "There is no SPI driver for"
 331                                         " loading the firmware\n");
 332 #endif
 333                                 release_firmware(fw);
 334                                 fw = NULL;
 335                         }
 336
 337                         /* DSP run */
 338                         regmap_write(rt5514->i2c_regmap, 0x18002f00,
 339                                 0x00055148);
 340                 } else {
 341                         regmap_multi_reg_write(rt5514->i2c_regmap,
 342                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 343                         regcache_mark_dirty(rt5514->regmap);
 344                         regcache_sync(rt5514->regmap);
 345                 }
 346         }
 347
 348         return 0;
 349 }
 350
 351 static const struct snd_kcontrol_new rt5514_snd_controls[] = {
 352         SOC_DOUBLE_TLV("MIC Boost Volume", RT5514_ANA_CTRL_MICBST,
 353                 RT5514_SEL_BSTL_SFT, RT5514_SEL_BSTR_SFT, 8, 0, bst_tlv),
 354         SOC_DOUBLE_R_TLV("ADC1 Capture Volume", RT5514_DOWNFILTER0_CTRL1,
 355                 RT5514_DOWNFILTER0_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 356                 adc_vol_tlv),
 357         SOC_DOUBLE_R_TLV("ADC2 Capture Volume", RT5514_DOWNFILTER1_CTRL1,
 358                 RT5514_DOWNFILTER1_CTRL2, RT5514_AD_GAIN_SFT, 63, 0,
 359                 adc_vol_tlv),
 360         SOC_SINGLE_EXT("DSP Voice Wake Up", SND_SOC_NOPM, 0, 1, 0,
 361                 rt5514_dsp_voice_wake_up_get, rt5514_dsp_voice_wake_up_put),
 362 };
 363
 364 /* ADC Mixer*/
 365 static const struct snd_kcontrol_new rt5514_sto1_adc_l_mix[] = {
 366         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
 367                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 368         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL1,
 369                 RT5514_AD_AD_MIX_BIT, 1, 1),
 370 };
 371
 372 static const struct snd_kcontrol_new rt5514_sto1_adc_r_mix[] = {
 373         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
 374                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 375         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER0_CTRL2,
 376                 RT5514_AD_AD_MIX_BIT, 1, 1),
 377 };
 378
 379 static const struct snd_kcontrol_new rt5514_sto2_adc_l_mix[] = {
 380         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
 381                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 382         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL1,
 383                 RT5514_AD_AD_MIX_BIT, 1, 1),
 384 };
 385
 386 static const struct snd_kcontrol_new rt5514_sto2_adc_r_mix[] = {
 387         SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
 388                 RT5514_AD_DMIC_MIX_BIT, 1, 1),
 389         SOC_DAPM_SINGLE("ADC Switch", RT5514_DOWNFILTER1_CTRL2,
 390                 RT5514_AD_AD_MIX_BIT, 1, 1),
 391 };
 392
 393 /* DMIC Source */
 394 static const char * const rt5514_dmic_src[] = {
 395         "DMIC1", "DMIC2"
 396 };
 397
 398 static const SOC_ENUM_SINGLE_DECL(
 399         rt5514_stereo1_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 400         RT5514_AD0_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 401
 402 static const struct snd_kcontrol_new rt5514_sto1_dmic_mux =
 403         SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
 404
 405 static const SOC_ENUM_SINGLE_DECL(
 406         rt5514_stereo2_dmic_enum, RT5514_DIG_SOURCE_CTRL,
 407         RT5514_AD1_DMIC_INPUT_SEL_SFT, rt5514_dmic_src);
 408
 409 static const struct snd_kcontrol_new rt5514_sto2_dmic_mux =
 410         SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
 411
 412 /**
 413  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
 414  *
 415  * @rate: base clock rate.
 416  *
 417  * Choose divider parameter that gives the highest possible DMIC frequency in
 418  * 1MHz - 3MHz range.
 419  */
 420 static int rt5514_calc_dmic_clk(struct snd_soc_codec *codec, int rate)
 421 {
 422         int div[] = {2, 3, 4, 8, 12, 16, 24, 32};
 423         int i;
 424
 425         if (rate < 1000000 * div[0]) {
 426                 pr_warn("Base clock rate %d is too low\n", rate);
 427                 return -EINVAL;
 428         }
 429
 430         for (i = 0; i < ARRAY_SIZE(div); i++) {
 431                 /* find divider that gives DMIC frequency below 3.072MHz */
 432                 if (3072000 * div[i] >= rate)
 433                         return i;
 434         }
 435
 436         dev_warn(codec->dev, "Base clock rate %d is too high\n", rate);
 437         return -EINVAL;
 438 }
 439
 440 static int rt5514_set_dmic_clk(struct snd_soc_dapm_widget *w,
 441         struct snd_kcontrol *kcontrol, int event)
 442 {
 443         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 444         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 445         int idx;
 446
 447         idx = rt5514_calc_dmic_clk(codec, rt5514->sysclk);
 448         if (idx < 0)
 449                 dev_err(codec->dev, "Failed to set DMIC clock\n");
 450         else
 451                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL1,
 452                         RT5514_CLK_DMIC_OUT_SEL_MASK,
 453                         idx << RT5514_CLK_DMIC_OUT_SEL_SFT);
 454
 455         if (rt5514->pdata.dmic_init_delay)
 456                 msleep(rt5514->pdata.dmic_init_delay);
 457
 458         return idx;
 459 }
 460
 461 static int rt5514_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
 462                          struct snd_soc_dapm_widget *sink)
 463 {
 464         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(source->dapm);
 465         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 466
 467         if (rt5514->sysclk_src == RT5514_SCLK_S_PLL1)
 468                 return 1;
 469         else
 470                 return 0;
 471 }
 472
 473 static int rt5514_pre_event(struct snd_soc_dapm_widget *w,
 474         struct snd_kcontrol *kcontrol, int event)
 475 {
 476         struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 477         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 478
 479         switch (event) {
 480         case SND_SOC_DAPM_PRE_PMU:
 481                 /**
 482                  * If the DSP is enabled in start of recording, the DSP
 483                  * should be disabled, and sync back to normal recording
 484                  * settings to make sure recording properly.
 485                 */
 486                 if (rt5514->dsp_enabled) {
 487                         rt5514->dsp_enabled = 0;
 488                         regmap_multi_reg_write(rt5514->i2c_regmap,
 489                                 rt5514_i2c_patch, ARRAY_SIZE(rt5514_i2c_patch));
 490                         regcache_mark_dirty(rt5514->regmap);
 491                         regcache_sync(rt5514->regmap);
 492                 }
 493                 break;
 494
 495         default:
 496                 return 0;
 497         }
 498
 499         return 0;
 500 }
 501
 502 static const struct snd_soc_dapm_widget rt5514_dapm_widgets[] = {
 503         /* Input Lines */
 504         SND_SOC_DAPM_INPUT("DMIC1L"),
 505         SND_SOC_DAPM_INPUT("DMIC1R"),
 506         SND_SOC_DAPM_INPUT("DMIC2L"),
 507         SND_SOC_DAPM_INPUT("DMIC2R"),
 508
 509         SND_SOC_DAPM_INPUT("AMICL"),
 510         SND_SOC_DAPM_INPUT("AMICR"),
 511
 512         SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
 513         SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
 514
 515         SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
 516                 rt5514_set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
 517
 518         SND_SOC_DAPM_SUPPLY("ADC CLK", RT5514_CLK_CTRL1,
 519                 RT5514_CLK_AD_ANA1_EN_BIT, 0, NULL, 0),
 520
 521         SND_SOC_DAPM_SUPPLY("LDO18 IN", RT5514_PWR_ANA1,
 522                 RT5514_POW_LDO18_IN_BIT, 0, NULL, 0),
 523         SND_SOC_DAPM_SUPPLY("LDO18 ADC", RT5514_PWR_ANA1,
 524                 RT5514_POW_LDO18_ADC_BIT, 0, NULL, 0),
 525         SND_SOC_DAPM_SUPPLY("LDO21", RT5514_PWR_ANA1, RT5514_POW_LDO21_BIT, 0,
 526                 NULL, 0),
 527         SND_SOC_DAPM_SUPPLY("BG LDO18 IN", RT5514_PWR_ANA1,
 528                 RT5514_POW_BG_LDO18_IN_BIT, 0, NULL, 0),
 529         SND_SOC_DAPM_SUPPLY("BG LDO21", RT5514_PWR_ANA1,
 530                 RT5514_POW_BG_LDO21_BIT, 0, NULL, 0),
 531         SND_SOC_DAPM_SUPPLY("BG MBIAS", RT5514_PWR_ANA2,
 532                 RT5514_POW_BG_MBIAS_BIT, 0, NULL, 0),
 533         SND_SOC_DAPM_SUPPLY("MBIAS", RT5514_PWR_ANA2, RT5514_POW_MBIAS_BIT, 0,
 534                 NULL, 0),
 535         SND_SOC_DAPM_SUPPLY("VREF2", RT5514_PWR_ANA2, RT5514_POW_VREF2_BIT, 0,
 536                 NULL, 0),
 537         SND_SOC_DAPM_SUPPLY("VREF1", RT5514_PWR_ANA2, RT5514_POW_VREF1_BIT, 0,
 538                 NULL, 0),
 539         SND_SOC_DAPM_SUPPLY("ADC Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 540
 541
 542         SND_SOC_DAPM_SUPPLY("LDO16L", RT5514_PWR_ANA2, RT5514_POWL_LDO16_BIT, 0,
 543                 NULL, 0),
 544         SND_SOC_DAPM_SUPPLY("ADC1L", RT5514_PWR_ANA2, RT5514_POW_ADC1_L_BIT, 0,
 545                 NULL, 0),
 546         SND_SOC_DAPM_SUPPLY("BSTL2", RT5514_PWR_ANA2, RT5514_POW2_BSTL_BIT, 0,
 547                 NULL, 0),
 548         SND_SOC_DAPM_SUPPLY("BSTL", RT5514_PWR_ANA2, RT5514_POW_BSTL_BIT, 0,
 549                 NULL, 0),
 550         SND_SOC_DAPM_SUPPLY("ADCFEDL", RT5514_PWR_ANA2, RT5514_POW_ADCFEDL_BIT,
 551                 0, NULL, 0),
 552         SND_SOC_DAPM_SUPPLY("ADCL Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 553
 554         SND_SOC_DAPM_SUPPLY("LDO16R", RT5514_PWR_ANA2, RT5514_POWR_LDO16_BIT, 0,
 555                 NULL, 0),
 556         SND_SOC_DAPM_SUPPLY("ADC1R", RT5514_PWR_ANA2, RT5514_POW_ADC1_R_BIT, 0,
 557                 NULL, 0),
 558         SND_SOC_DAPM_SUPPLY("BSTR2", RT5514_PWR_ANA2, RT5514_POW2_BSTR_BIT, 0,
 559                 NULL, 0),
 560         SND_SOC_DAPM_SUPPLY("BSTR", RT5514_PWR_ANA2, RT5514_POW_BSTR_BIT, 0,
 561                 NULL, 0),
 562         SND_SOC_DAPM_SUPPLY("ADCFEDR", RT5514_PWR_ANA2, RT5514_POW_ADCFEDR_BIT,
 563                 0, NULL, 0),
 564         SND_SOC_DAPM_SUPPLY("ADCR Power", SND_SOC_NOPM, 0, 0, NULL, 0),
 565
 566         SND_SOC_DAPM_SUPPLY("PLL1 LDO ENABLE", RT5514_ANA_CTRL_PLL1_2,
 567                 RT5514_EN_LDO_PLL1_BIT, 0, NULL, 0),
 568         SND_SOC_DAPM_SUPPLY("PLL1 LDO", RT5514_PWR_ANA2,
 569                 RT5514_POW_PLL1_LDO_BIT, 0, NULL, 0),
 570         SND_SOC_DAPM_SUPPLY("PLL1", RT5514_PWR_ANA2, RT5514_POW_PLL1_BIT, 0,
 571                 NULL, 0),
 572
 573         /* ADC Mux */
 574         SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
 575                                 &rt5514_sto1_dmic_mux),
 576         SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
 577                                 &rt5514_sto2_dmic_mux),
 578
 579         /* ADC Mixer */
 580         SND_SOC_DAPM_SUPPLY("adc stereo1 filter", RT5514_CLK_CTRL1,
 581                 RT5514_CLK_AD0_EN_BIT, 0, NULL, 0),
 582         SND_SOC_DAPM_SUPPLY("adc stereo2 filter", RT5514_CLK_CTRL1,
 583                 RT5514_CLK_AD1_EN_BIT, 0, NULL, 0),
 584
 585         SND_SOC_DAPM_MIXER("Sto1 ADC MIXL", SND_SOC_NOPM, 0, 0,
 586                 rt5514_sto1_adc_l_mix, ARRAY_SIZE(rt5514_sto1_adc_l_mix)),
 587         SND_SOC_DAPM_MIXER("Sto1 ADC MIXR", SND_SOC_NOPM, 0, 0,
 588                 rt5514_sto1_adc_r_mix, ARRAY_SIZE(rt5514_sto1_adc_r_mix)),
 589         SND_SOC_DAPM_MIXER("Sto2 ADC MIXL", SND_SOC_NOPM, 0, 0,
 590                 rt5514_sto2_adc_l_mix, ARRAY_SIZE(rt5514_sto2_adc_l_mix)),
 591         SND_SOC_DAPM_MIXER("Sto2 ADC MIXR", SND_SOC_NOPM, 0, 0,
 592                 rt5514_sto2_adc_r_mix, ARRAY_SIZE(rt5514_sto2_adc_r_mix)),
 593
 594         SND_SOC_DAPM_ADC("Stereo1 ADC MIXL", NULL, RT5514_DOWNFILTER0_CTRL1,
 595                 RT5514_AD_AD_MUTE_BIT, 1),
 596         SND_SOC_DAPM_ADC("Stereo1 ADC MIXR", NULL, RT5514_DOWNFILTER0_CTRL2,
 597                 RT5514_AD_AD_MUTE_BIT, 1),
 598         SND_SOC_DAPM_ADC("Stereo2 ADC MIXL", NULL, RT5514_DOWNFILTER1_CTRL1,
 599                 RT5514_AD_AD_MUTE_BIT, 1),
 600         SND_SOC_DAPM_ADC("Stereo2 ADC MIXR", NULL, RT5514_DOWNFILTER1_CTRL2,
 601                 RT5514_AD_AD_MUTE_BIT, 1),
 602
 603         /* ADC PGA */
 604         SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 605         SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
 606
 607         /* Audio Interface */
 608         SND_SOC_DAPM_AIF_OUT("AIF1TX", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
 609
 610         SND_SOC_DAPM_PRE("DAPM Pre", rt5514_pre_event),
 611 };
 612
 613 static const struct snd_soc_dapm_route rt5514_dapm_routes[] = {
 614         { "DMIC1", NULL, "DMIC1L" },
 615         { "DMIC1", NULL, "DMIC1R" },
 616         { "DMIC2", NULL, "DMIC2L" },
 617         { "DMIC2", NULL, "DMIC2R" },
 618
 619         { "DMIC1L", NULL, "DMIC CLK" },
 620         { "DMIC1R", NULL, "DMIC CLK" },
 621         { "DMIC2L", NULL, "DMIC CLK" },
 622         { "DMIC2R", NULL, "DMIC CLK" },
 623
 624         { "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
 625         { "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
 626
 627         { "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
 628         { "Sto1 ADC MIXL", "ADC Switch", "AMICL" },
 629         { "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
 630         { "Sto1 ADC MIXR", "ADC Switch", "AMICR" },
 631
 632         { "ADC Power", NULL, "LDO18 IN" },
 633         { "ADC Power", NULL, "LDO18 ADC" },
 634         { "ADC Power", NULL, "LDO21" },
 635         { "ADC Power", NULL, "BG LDO18 IN" },
 636         { "ADC Power", NULL, "BG LDO21" },
 637         { "ADC Power", NULL, "BG MBIAS" },
 638         { "ADC Power", NULL, "MBIAS" },
 639         { "ADC Power", NULL, "VREF2" },
 640         { "ADC Power", NULL, "VREF1" },
 641
 642         { "ADCL Power", NULL, "LDO16L" },
 643         { "ADCL Power", NULL, "ADC1L" },
 644         { "ADCL Power", NULL, "BSTL2" },
 645         { "ADCL Power", NULL, "BSTL" },
 646         { "ADCL Power", NULL, "ADCFEDL" },
 647
 648         { "ADCR Power", NULL, "LDO16R" },
 649         { "ADCR Power", NULL, "ADC1R" },
 650         { "ADCR Power", NULL, "BSTR2" },
 651         { "ADCR Power", NULL, "BSTR" },
 652         { "ADCR Power", NULL, "ADCFEDR" },
 653
 654         { "AMICL", NULL, "ADC CLK" },
 655         { "AMICL", NULL, "ADC Power" },
 656         { "AMICL", NULL, "ADCL Power" },
 657         { "AMICR", NULL, "ADC CLK" },
 658         { "AMICR", NULL, "ADC Power" },
 659         { "AMICR", NULL, "ADCR Power" },
 660
 661         { "PLL1 LDO", NULL, "PLL1 LDO ENABLE" },
 662         { "PLL1", NULL, "PLL1 LDO" },
 663
 664         { "Stereo1 ADC MIXL", NULL, "Sto1 ADC MIXL" },
 665         { "Stereo1 ADC MIXR", NULL, "Sto1 ADC MIXR" },
 666
 667         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL" },
 668         { "Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR" },
 669         { "Stereo1 ADC MIX", NULL, "adc stereo1 filter" },
 670         { "adc stereo1 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 671
 672         { "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
 673         { "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
 674
 675         { "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
 676         { "Sto2 ADC MIXL", "ADC Switch", "AMICL" },
 677         { "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
 678         { "Sto2 ADC MIXR", "ADC Switch", "AMICR" },
 679
 680         { "Stereo2 ADC MIXL", NULL, "Sto2 ADC MIXL" },
 681         { "Stereo2 ADC MIXR", NULL, "Sto2 ADC MIXR" },
 682
 683         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL" },
 684         { "Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR" },
 685         { "Stereo2 ADC MIX", NULL, "adc stereo2 filter" },
 686         { "adc stereo2 filter", NULL, "PLL1", rt5514_is_sys_clk_from_pll },
 687
 688         { "AIF1TX", NULL, "Stereo1 ADC MIX"},
 689         { "AIF1TX", NULL, "Stereo2 ADC MIX"},
 690 };
 691
 692 static int rt5514_hw_params(struct snd_pcm_substream *substream,
 693         struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 694 {
 695         struct snd_soc_codec *codec = dai->codec;
 696         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 697         int pre_div, bclk_ms, frame_size;
 698         unsigned int val_len = 0;
 699
 700         rt5514->lrck = params_rate(params);
 701         pre_div = rl6231_get_clk_info(rt5514->sysclk, rt5514->lrck);
 702         if (pre_div < 0) {
 703                 dev_err(codec->dev, "Unsupported clock setting\n");
 704                 return -EINVAL;
 705         }
 706
 707         frame_size = snd_soc_params_to_frame_size(params);
 708         if (frame_size < 0) {
 709                 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
 710                 return -EINVAL;
 711         }
 712
 713         bclk_ms = frame_size > 32;
 714         rt5514->bclk = rt5514->lrck * (32 << bclk_ms);
 715
 716         dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
 717                 rt5514->bclk, rt5514->lrck);
 718         dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
 719                                 bclk_ms, pre_div, dai->id);
 720
 721         switch (params_format(params)) {
 722         case SNDRV_PCM_FORMAT_S16_LE:
 723                 break;
 724         case SNDRV_PCM_FORMAT_S20_3LE:
 725                 val_len = RT5514_I2S_DL_20;
 726                 break;
 727         case SNDRV_PCM_FORMAT_S24_LE:
 728                 val_len = RT5514_I2S_DL_24;
 729                 break;
 730         case SNDRV_PCM_FORMAT_S8:
 731                 val_len = RT5514_I2S_DL_8;
 732                 break;
 733         default:
 734                 return -EINVAL;
 735         }
 736
 737         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_I2S_DL_MASK,
 738                 val_len);
 739         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 740                 RT5514_CLK_SYS_DIV_OUT_MASK | RT5514_SEL_ADC_OSR_MASK,
 741                 pre_div << RT5514_CLK_SYS_DIV_OUT_SFT |
 742                 pre_div << RT5514_SEL_ADC_OSR_SFT);
 743
 744         return 0;
 745 }
 746
 747 static int rt5514_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 748 {
 749         struct snd_soc_codec *codec = dai->codec;
 750         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 751         unsigned int reg_val = 0;
 752
 753         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 754         case SND_SOC_DAIFMT_NB_NF:
 755                 break;
 756
 757         case SND_SOC_DAIFMT_NB_IF:
 758                 reg_val |= RT5514_I2S_LR_INV;
 759                 break;
 760
 761         case SND_SOC_DAIFMT_IB_NF:
 762                 reg_val |= RT5514_I2S_BP_INV;
 763                 break;
 764
 765         case SND_SOC_DAIFMT_IB_IF:
 766                 reg_val |= RT5514_I2S_BP_INV | RT5514_I2S_LR_INV;
 767                 break;
 768
 769         default:
 770                 return -EINVAL;
 771         }
 772
 773         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 774         case SND_SOC_DAIFMT_I2S:
 775                 break;
 776
 777         case SND_SOC_DAIFMT_LEFT_J:
 778                 reg_val |= RT5514_I2S_DF_LEFT;
 779                 break;
 780
 781         case SND_SOC_DAIFMT_DSP_A:
 782                 reg_val |= RT5514_I2S_DF_PCM_A;
 783                 break;
 784
 785         case SND_SOC_DAIFMT_DSP_B:
 786                 reg_val |= RT5514_I2S_DF_PCM_B;
 787                 break;
 788
 789         default:
 790                 return -EINVAL;
 791         }
 792
 793         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1,
 794                 RT5514_I2S_DF_MASK | RT5514_I2S_BP_MASK | RT5514_I2S_LR_MASK,
 795                 reg_val);
 796
 797         return 0;
 798 }
 799
 800 static int rt5514_set_dai_sysclk(struct snd_soc_dai *dai,
 801                 int clk_id, unsigned int freq, int dir)
 802 {
 803         struct snd_soc_codec *codec = dai->codec;
 804         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 805         unsigned int reg_val = 0;
 806
 807         if (freq == rt5514->sysclk && clk_id == rt5514->sysclk_src)
 808                 return 0;
 809
 810         switch (clk_id) {
 811         case RT5514_SCLK_S_MCLK:
 812                 reg_val |= RT5514_CLK_SYS_PRE_SEL_MCLK;
 813                 break;
 814
 815         case RT5514_SCLK_S_PLL1:
 816                 reg_val |= RT5514_CLK_SYS_PRE_SEL_PLL;
 817                 break;
 818
 819         default:
 820                 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
 821                 return -EINVAL;
 822         }
 823
 824         regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 825                 RT5514_CLK_SYS_PRE_SEL_MASK, reg_val);
 826
 827         rt5514->sysclk = freq;
 828         rt5514->sysclk_src = clk_id;
 829
 830         dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
 831
 832         return 0;
 833 }
 834
 835 static int rt5514_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
 836                         unsigned int freq_in, unsigned int freq_out)
 837 {
 838         struct snd_soc_codec *codec = dai->codec;
 839         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 840         struct rl6231_pll_code pll_code;
 841         int ret;
 842
 843         if (!freq_in || !freq_out) {
 844                 dev_dbg(codec->dev, "PLL disabled\n");
 845
 846                 rt5514->pll_in = 0;
 847                 rt5514->pll_out = 0;
 848                 regmap_update_bits(rt5514->regmap, RT5514_CLK_CTRL2,
 849                         RT5514_CLK_SYS_PRE_SEL_MASK,
 850                         RT5514_CLK_SYS_PRE_SEL_MCLK);
 851
 852                 return 0;
 853         }
 854
 855         if (source == rt5514->pll_src && freq_in == rt5514->pll_in &&
 856             freq_out == rt5514->pll_out)
 857                 return 0;
 858
 859         switch (source) {
 860         case RT5514_PLL1_S_MCLK:
 861                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 862                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_MCLK);
 863                 break;
 864
 865         case RT5514_PLL1_S_BCLK:
 866                 regmap_update_bits(rt5514->regmap, RT5514_PLL_SOURCE_CTRL,
 867                         RT5514_PLL_1_SEL_MASK, RT5514_PLL_1_SEL_SCLK);
 868                 break;
 869
 870         default:
 871                 dev_err(codec->dev, "Unknown PLL source %d\n", source);
 872                 return -EINVAL;
 873         }
 874
 875         ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
 876         if (ret < 0) {
 877                 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
 878                 return ret;
 879         }
 880
 881         dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
 882                 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
 883                 pll_code.n_code, pll_code.k_code);
 884
 885         regmap_write(rt5514->regmap, RT5514_ANA_CTRL_PLL1_1,
 886                 pll_code.k_code << RT5514_PLL_K_SFT |
 887                 pll_code.n_code << RT5514_PLL_N_SFT |
 888                 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5514_PLL_M_SFT);
 889         regmap_update_bits(rt5514->regmap, RT5514_ANA_CTRL_PLL1_2,
 890                 RT5514_PLL_M_BP, pll_code.m_bp << RT5514_PLL_M_BP_SFT);
 891
 892         rt5514->pll_in = freq_in;
 893         rt5514->pll_out = freq_out;
 894         rt5514->pll_src = source;
 895
 896         return 0;
 897 }
 898
 899 static int rt5514_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
 900                         unsigned int rx_mask, int slots, int slot_width)
 901 {
 902         struct snd_soc_codec *codec = dai->codec;
 903         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 904         unsigned int val = 0;
 905
 906         if (rx_mask || tx_mask)
 907                 val |= RT5514_TDM_MODE;
 908
 909         if (slots == 4)
 910                 val |= RT5514_TDMSLOT_SEL_RX_4CH | RT5514_TDMSLOT_SEL_TX_4CH;
 911
 912
 913         switch (slot_width) {
 914         case 20:
 915                 val |= RT5514_CH_LEN_RX_20 | RT5514_CH_LEN_TX_20;
 916                 break;
 917
 918         case 24:
 919                 val |= RT5514_CH_LEN_RX_24 | RT5514_CH_LEN_TX_24;
 920                 break;
 921
 922         case 32:
 923                 val |= RT5514_CH_LEN_RX_32 | RT5514_CH_LEN_TX_32;
 924                 break;
 925
 926         case 16:
 927         default:
 928                 break;
 929         }
 930
 931         regmap_update_bits(rt5514->regmap, RT5514_I2S_CTRL1, RT5514_TDM_MODE |
 932                 RT5514_TDMSLOT_SEL_RX_MASK | RT5514_TDMSLOT_SEL_TX_MASK |
 933                 RT5514_CH_LEN_RX_MASK | RT5514_CH_LEN_TX_MASK, val);
 934
 935         return 0;
 936 }
 937
 938 static int rt5514_set_bias_level(struct snd_soc_codec *codec,
 939                         enum snd_soc_bias_level level)
 940 {
 941         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 942         int ret;
 943
 944         switch (level) {
 945         case SND_SOC_BIAS_PREPARE:
 946                 if (IS_ERR(rt5514->mclk))
 947                         break;
 948
 949                 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_ON) {
 950                         clk_disable_unprepare(rt5514->mclk);
 951                 } else {
 952                         ret = clk_prepare_enable(rt5514->mclk);
 953                         if (ret)
 954                                 return ret;
 955                 }
 956                 break;
 957
 958         default:
 959                 break;
 960         }
 961
 962         return 0;
 963 }
 964
 965 static int rt5514_probe(struct snd_soc_codec *codec)
 966 {
 967         struct rt5514_priv *rt5514 = snd_soc_codec_get_drvdata(codec);
 968
 969         rt5514->mclk = devm_clk_get(codec->dev, "mclk");
 970         if (PTR_ERR(rt5514->mclk) == -EPROBE_DEFER)
 971                 return -EPROBE_DEFER;
 972
 973         rt5514->codec = codec;
 974
 975         return 0;
 976 }
 977
 978 static int rt5514_i2c_read(void *context, unsigned int reg, unsigned int *val)
 979 {
 980         struct i2c_client *client = context;
 981         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
 982
 983         regmap_read(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
 984
 985         return 0;
 986 }
 987
 988 static int rt5514_i2c_write(void *context, unsigned int reg, unsigned int val)
 989 {
 990         struct i2c_client *client = context;
 991         struct rt5514_priv *rt5514 = i2c_get_clientdata(client);
 992
 993         regmap_write(rt5514->i2c_regmap, reg | RT5514_DSP_MAPPING, val);
 994
 995         return 0;
 996 }
 997
 998 #define RT5514_STEREO_RATES SNDRV_PCM_RATE_8000_192000
 999 #define RT5514_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1000                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
1001
1002 struct snd_soc_dai_ops rt5514_aif_dai_ops = {
1003         .hw_params = rt5514_hw_params,
1004         .set_fmt = rt5514_set_dai_fmt,
1005         .set_sysclk = rt5514_set_dai_sysclk,
1006         .set_pll = rt5514_set_dai_pll,
1007         .set_tdm_slot = rt5514_set_tdm_slot,
1008 };
1009
1010 struct snd_soc_dai_driver rt5514_dai[] = {
1011         {
1012                 .name = "rt5514-aif1",
1013                 .id = 0,
1014                 .capture = {
1015                         .stream_name = "AIF1 Capture",
1016                         .channels_min = 1,
1017                         .channels_max = 4,
1018                         .rates = RT5514_STEREO_RATES,
1019                         .formats = RT5514_FORMATS,
1020                 },
1021                 .ops = &rt5514_aif_dai_ops,
1022         }
1023 };
1024
1025 static struct snd_soc_codec_driver soc_codec_dev_rt5514 = {
1026         .probe = rt5514_probe,
1027         .idle_bias_off = true,
1028         .set_bias_level = rt5514_set_bias_level,
1029         .component_driver = {
1030                 .controls               = rt5514_snd_controls,
1031                 .num_controls           = ARRAY_SIZE(rt5514_snd_controls),
1032                 .dapm_widgets           = rt5514_dapm_widgets,
1033                 .num_dapm_widgets       = ARRAY_SIZE(rt5514_dapm_widgets),
1034                 .dapm_routes            = rt5514_dapm_routes,
1035                 .num_dapm_routes        = ARRAY_SIZE(rt5514_dapm_routes),
1036         },
1037 };
1038
1039 static const struct regmap_config rt5514_i2c_regmap = {
1040         .name = "i2c",
1041         .reg_bits = 32,
1042         .val_bits = 32,
1043
1044         .readable_reg = rt5514_i2c_readable_register,
1045
1046         .cache_type = REGCACHE_NONE,
1047 };
1048
1049 static const struct regmap_config rt5514_regmap = {
1050         .reg_bits = 16,
1051         .val_bits = 32,
1052
1053         .max_register = RT5514_VENDOR_ID2,
1054         .volatile_reg = rt5514_volatile_register,
1055         .readable_reg = rt5514_readable_register,
1056         .reg_read = rt5514_i2c_read,
1057         .reg_write = rt5514_i2c_write,
1058
1059         .cache_type = REGCACHE_RBTREE,
1060         .reg_defaults = rt5514_reg,
1061         .num_reg_defaults = ARRAY_SIZE(rt5514_reg),
1062         .use_single_rw = true,
1063 };
1064
1065 static const struct i2c_device_id rt5514_i2c_id[] = {
1066         { "rt5514", 0 },
1067         { }
1068 };
1069 MODULE_DEVICE_TABLE(i2c, rt5514_i2c_id);
1070
1071 #if defined(CONFIG_OF)
1072 static const struct of_device_id rt5514_of_match[] = {
1073         { .compatible = "realtek,rt5514", },
1074         {},
1075 };
1076 MODULE_DEVICE_TABLE(of, rt5514_of_match);
1077 #endif
1078
1079 static int rt5514_parse_dt(struct rt5514_priv *rt5514, struct device *dev)
1080 {
1081         device_property_read_u32(dev, "realtek,dmic-init-delay-ms",
1082                 &rt5514->pdata.dmic_init_delay);
1083
1084         return 0;
1085 }
1086
1087 static int rt5514_i2c_probe(struct i2c_client *i2c,
1088                     const struct i2c_device_id *id)
1089 {
1090         struct rt5514_platform_data *pdata = dev_get_platdata(&i2c->dev);
1091         struct rt5514_priv *rt5514;
1092         int ret;
1093         unsigned int val;
1094
1095         rt5514 = devm_kzalloc(&i2c->dev, sizeof(struct rt5514_priv),
1096                                 GFP_KERNEL);
1097         if (rt5514 == NULL)
1098                 return -ENOMEM;
1099
1100         i2c_set_clientdata(i2c, rt5514);
1101
1102         if (pdata)
1103                 rt5514->pdata = *pdata;
1104         else if (i2c->dev.of_node)
1105                 rt5514_parse_dt(rt5514, &i2c->dev);
1106
1107         rt5514->i2c_regmap = devm_regmap_init_i2c(i2c, &rt5514_i2c_regmap);
1108         if (IS_ERR(rt5514->i2c_regmap)) {
1109                 ret = PTR_ERR(rt5514->i2c_regmap);
1110                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1111                         ret);
1112                 return ret;
1113         }
1114
1115         rt5514->regmap = devm_regmap_init(&i2c->dev, NULL, i2c, &rt5514_regmap);
1116         if (IS_ERR(rt5514->regmap)) {
1117                 ret = PTR_ERR(rt5514->regmap);
1118                 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1119                         ret);
1120                 return ret;
1121         }
1122
1123         regmap_read(rt5514->regmap, RT5514_VENDOR_ID2, &val);
1124         if (val != RT5514_DEVICE_ID) {
1125                 dev_err(&i2c->dev,
1126                         "Device with ID register %x is not rt5514\n", val);
1127                 return -ENODEV;
1128         }
1129
1130         ret = regmap_multi_reg_write(rt5514->i2c_regmap, rt5514_i2c_patch,
1131                                     ARRAY_SIZE(rt5514_i2c_patch));
1132         if (ret != 0)
1133                 dev_warn(&i2c->dev, "Failed to apply i2c_regmap patch: %d\n",
1134                         ret);
1135
1136         ret = regmap_register_patch(rt5514->regmap, rt5514_patch,
1137                                     ARRAY_SIZE(rt5514_patch));
1138         if (ret != 0)
1139                 dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);
1140
1141         return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5514,
1142                         rt5514_dai, ARRAY_SIZE(rt5514_dai));
1143 }
1144
1145 static int rt5514_i2c_remove(struct i2c_client *i2c)
1146 {
1147         snd_soc_unregister_codec(&i2c->dev);
1148
1149         return 0;
1150 }
1151
1152 struct i2c_driver rt5514_i2c_driver = {
1153         .driver = {
1154                 .name = "rt5514",
1155                 .of_match_table = of_match_ptr(rt5514_of_match),
1156         },
1157         .probe = rt5514_i2c_probe,
1158         .remove   = rt5514_i2c_remove,
1159         .id_table = rt5514_i2c_id,
1160 };
1161 module_i2c_driver(rt5514_i2c_driver);
1162
1163 MODULE_DESCRIPTION("ASoC RT5514 driver");
1164 MODULE_AUTHOR("Oder Chiou <oder_chiou@realtek.com>");
1165 MODULE_LICENSE("GPL v2");