1 // SPDX-License-Identifier: GPL-2.0-only
3 // rt1019.c -- RT1019 ALSA SoC audio amplifier driver
4 // Author: Jack Yu <jack.yu@realtek.com>
6 // Copyright(c) 2021 Realtek Semiconductor Corp.
10 #include <linux/acpi.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/delay.h>
17 #include <linux/regmap.h>
18 #include <linux/i2c.h>
19 #include <linux/platform_device.h>
20 #include <linux/firmware.h>
21 #include <linux/gpio.h>
22 #include <sound/core.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/soc-dapm.h>
27 #include <sound/initval.h>
28 #include <sound/tlv.h>
33 static const struct reg_default rt1019_reg[] = {
197 static bool rt1019_volatile_register(struct device *dev, unsigned int reg)
200 case RT1019_PWR_STRP_1:
201 case RT1019_PWR_STRP_2:
202 case RT1019_SIL_DET_GAT:
203 case RT1019_PHASE_SYNC:
204 case RT1019_STAT_MACH_2:
205 case RT1019_FS_DET_1:
206 case RT1019_FS_DET_2:
207 case RT1019_FS_DET_3:
208 case RT1019_FS_DET_4:
209 case RT1019_FS_DET_5:
210 case RT1019_FS_DET_6:
211 case RT1019_FS_DET_7:
212 case RT1019_ANA_READ:
214 case RT1019_CUSTOM_ID:
215 case RT1019_VEND_ID_1:
216 case RT1019_VEND_ID_2:
217 case RT1019_DEV_ID_1:
218 case RT1019_DEV_ID_2:
219 case RT1019_CAL_TOP_3:
220 case RT1019_CAL_TOP_7:
221 case RT1019_CAL_TOP_17:
222 case RT1019_CAL_TOP_18:
223 case RT1019_CAL_TOP_19:
224 case RT1019_CAL_TOP_20:
225 case RT1019_CAL_TOP_21:
226 case RT1019_CAL_TOP_22:
227 case RT1019_MDRE_CTRL_2:
228 case RT1019_MDRE_CTRL_3:
229 case RT1019_MDRE_CTRL_4:
230 case RT1019_SIL_DET_2:
231 case RT1019_PWM_DC_DET_1:
234 case RT1019_SPKDRC_7:
235 case RT1019_HALF_FREQ_7:
236 case RT1019_CUR_CTRL_11:
237 case RT1019_CUR_CTRL_12:
238 case RT1019_CUR_CTRL_13:
246 static bool rt1019_readable_register(struct device *dev, unsigned int reg)
250 case RT1019_PAD_DRV_1:
251 case RT1019_PAD_DRV_2:
252 case RT1019_PAD_PULL_1:
253 case RT1019_PAD_PULL_2:
254 case RT1019_PAD_PULL_3:
255 case RT1019_I2C_CTRL_1:
256 case RT1019_I2C_CTRL_2:
257 case RT1019_I2C_CTRL_3:
258 case RT1019_IDS_CTRL:
259 case RT1019_ASEL_CTRL:
260 case RT1019_PLL_RESET:
261 case RT1019_PWR_STRP_1:
262 case RT1019_PWR_STRP_2:
263 case RT1019_BEEP_TONE:
264 case RT1019_SIL_DET_GAT:
265 case RT1019_CLASSD_TIME:
266 case RT1019_CLASSD_OCP:
267 case RT1019_PHASE_SYNC:
268 case RT1019_STAT_MACH_1:
269 case RT1019_STAT_MACH_2:
270 case RT1019_EFF_CTRL:
271 case RT1019_FS_DET_1:
272 case RT1019_FS_DET_2:
273 case RT1019_FS_DET_3:
274 case RT1019_FS_DET_4:
275 case RT1019_FS_DET_5:
276 case RT1019_FS_DET_6:
277 case RT1019_FS_DET_7:
278 case RT1019_ANA_CTRL:
283 case RT1019_ANA_READ:
285 case RT1019_CUSTOM_ID:
286 case RT1019_VEND_ID_1:
287 case RT1019_VEND_ID_2:
288 case RT1019_DEV_ID_1:
289 case RT1019_DEV_ID_2:
290 case RT1019_TEST_PAD:
291 case RT1019_SDB_CTRL:
292 case RT1019_TEST_CTRL_1:
293 case RT1019_TEST_CTRL_2:
294 case RT1019_TEST_CTRL_3:
295 case RT1019_SCAN_MODE:
296 case RT1019_CLK_TREE_1:
297 case RT1019_CLK_TREE_2:
298 case RT1019_CLK_TREE_3:
299 case RT1019_CLK_TREE_4:
300 case RT1019_CLK_TREE_5:
301 case RT1019_CLK_TREE_6:
302 case RT1019_CLK_TREE_7:
303 case RT1019_CLK_TREE_8:
304 case RT1019_CLK_TREE_9:
310 case RT1019_BIAS_CUR_1:
311 case RT1019_BIAS_CUR_2:
312 case RT1019_BIAS_CUR_3:
313 case RT1019_BIAS_CUR_4:
314 case RT1019_CHOP_CLK_DAC:
315 case RT1019_CHOP_CLK_ADC:
316 case RT1019_LDO_CTRL_1:
317 case RT1019_LDO_CTRL_2:
318 case RT1019_PM_ANA_1:
319 case RT1019_PM_ANA_2:
320 case RT1019_PM_ANA_3:
324 case RT1019_PLL_INT_1:
325 case RT1019_PLL_INT_3:
327 case RT1019_CLD_OUT_1:
328 case RT1019_CLD_OUT_2:
329 case RT1019_CLD_OUT_3:
330 case RT1019_CLD_OUT_4:
331 case RT1019_CLD_OUT_5:
332 case RT1019_CLD_OUT_6:
333 case RT1019_CLS_INT_REG_1:
334 case RT1019_CLS_INT_REG_2:
335 case RT1019_CLS_INT_REG_3:
336 case RT1019_CLS_INT_REG_4:
337 case RT1019_CLS_INT_REG_5:
338 case RT1019_CLS_INT_REG_6:
339 case RT1019_CLS_INT_REG_7:
340 case RT1019_CLS_INT_REG_8:
341 case RT1019_CLS_INT_REG_9:
342 case RT1019_CLS_INT_REG_10:
353 case RT1019_DMIX_MONO_1:
354 case RT1019_DMIX_MONO_2:
355 case RT1019_CAL_TOP_1:
356 case RT1019_CAL_TOP_2:
357 case RT1019_CAL_TOP_3:
358 case RT1019_CAL_TOP_4:
359 case RT1019_CAL_TOP_5:
360 case RT1019_CAL_TOP_6:
361 case RT1019_CAL_TOP_7:
362 case RT1019_CAL_TOP_8:
363 case RT1019_CAL_TOP_9:
364 case RT1019_CAL_TOP_10:
365 case RT1019_CAL_TOP_11:
366 case RT1019_CAL_TOP_12:
367 case RT1019_CAL_TOP_13:
368 case RT1019_CAL_TOP_14:
369 case RT1019_CAL_TOP_15:
370 case RT1019_CAL_TOP_16:
371 case RT1019_CAL_TOP_17:
372 case RT1019_CAL_TOP_18:
373 case RT1019_CAL_TOP_19:
374 case RT1019_CAL_TOP_20:
375 case RT1019_CAL_TOP_21:
376 case RT1019_CAL_TOP_22:
377 case RT1019_MDRE_CTRL_1:
378 case RT1019_MDRE_CTRL_2:
379 case RT1019_MDRE_CTRL_3:
380 case RT1019_MDRE_CTRL_4:
381 case RT1019_MDRE_CTRL_5:
382 case RT1019_MDRE_CTRL_6:
383 case RT1019_MDRE_CTRL_7:
384 case RT1019_MDRE_CTRL_8:
385 case RT1019_MDRE_CTRL_9:
386 case RT1019_MDRE_CTRL_10:
387 case RT1019_SCC_CTRL_1:
388 case RT1019_SCC_CTRL_2:
389 case RT1019_SCC_CTRL_3:
390 case RT1019_SCC_DUMMY:
391 case RT1019_SIL_DET_1:
392 case RT1019_SIL_DET_2:
393 case RT1019_PWM_DC_DET_1:
394 case RT1019_PWM_DC_DET_2:
395 case RT1019_PWM_DC_DET_3:
396 case RT1019_PWM_DC_DET_4:
408 case RT1019_SPKDRC_1:
409 case RT1019_SPKDRC_2:
410 case RT1019_SPKDRC_3:
411 case RT1019_SPKDRC_4:
412 case RT1019_SPKDRC_5:
413 case RT1019_SPKDRC_6:
414 case RT1019_SPKDRC_7:
415 case RT1019_HALF_FREQ_1:
416 case RT1019_HALF_FREQ_2:
417 case RT1019_HALF_FREQ_3:
418 case RT1019_HALF_FREQ_4:
419 case RT1019_HALF_FREQ_5:
420 case RT1019_HALF_FREQ_6:
421 case RT1019_HALF_FREQ_7:
422 case RT1019_CUR_CTRL_1:
423 case RT1019_CUR_CTRL_2:
424 case RT1019_CUR_CTRL_3:
425 case RT1019_CUR_CTRL_4:
426 case RT1019_CUR_CTRL_5:
427 case RT1019_CUR_CTRL_6:
428 case RT1019_CUR_CTRL_7:
429 case RT1019_CUR_CTRL_8:
430 case RT1019_CUR_CTRL_9:
431 case RT1019_CUR_CTRL_10:
432 case RT1019_CUR_CTRL_11:
433 case RT1019_CUR_CTRL_12:
434 case RT1019_CUR_CTRL_13:
441 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
443 static const char * const rt1019_din_source_select[] = {
446 "Left + Right average",
449 static SOC_ENUM_SINGLE_DECL(rt1019_mono_lr_sel, RT1019_IDS_CTRL, 0,
450 rt1019_din_source_select);
452 static const struct snd_kcontrol_new rt1019_snd_controls[] = {
453 SOC_SINGLE_TLV("DAC Playback Volume", RT1019_DMIX_MONO_1, 0,
454 127, 0, dac_vol_tlv),
455 SOC_ENUM("Mono LR Select", rt1019_mono_lr_sel),
458 static int r1019_dac_event(struct snd_soc_dapm_widget *w,
459 struct snd_kcontrol *kcontrol, int event)
461 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
464 case SND_SOC_DAPM_PRE_PMU:
465 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xb);
467 case SND_SOC_DAPM_POST_PMD:
468 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
477 static const struct snd_soc_dapm_widget rt1019_dapm_widgets[] = {
478 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
479 SND_SOC_DAPM_DAC_E("DAC", NULL, SND_SOC_NOPM, 0, 0,
480 r1019_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
481 SND_SOC_DAPM_OUTPUT("SPO"),
484 static const struct snd_soc_dapm_route rt1019_dapm_routes[] = {
485 { "DAC", NULL, "AIFRX" },
486 { "SPO", NULL, "DAC" },
489 static int rt1019_hw_params(struct snd_pcm_substream *substream,
490 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
492 struct snd_soc_component *component = dai->component;
493 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
494 int pre_div, bclk_ms, frame_size;
495 unsigned int val_len = 0, sys_div_da_filter = 0;
496 unsigned int sys_dac_osr = 0, sys_fifo_clk = 0;
497 unsigned int sys_clk_cal = 0, sys_asrc_in = 0;
499 rt1019->lrck = params_rate(params);
500 pre_div = rl6231_get_clk_info(rt1019->sysclk, rt1019->lrck);
502 dev_err(component->dev, "Unsupported clock setting\n");
506 frame_size = snd_soc_params_to_frame_size(params);
507 if (frame_size < 0) {
508 dev_err(component->dev, "Unsupported frame size: %d\n", frame_size);
512 bclk_ms = frame_size > 32;
513 rt1019->bclk = rt1019->lrck * (32 << bclk_ms);
515 dev_dbg(dai->dev, "bclk is %dHz and lrck is %dHz\n",
516 rt1019->bclk, rt1019->lrck);
517 dev_dbg(dai->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
518 bclk_ms, pre_div, dai->id);
522 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV1;
523 sys_dac_osr = RT1019_SYS_DA_OSR_DIV1;
524 sys_asrc_in = RT1019_ASRC_256FS_DIV1;
525 sys_fifo_clk = RT1019_SEL_FIFO_DIV1;
526 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV1;
529 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV2;
530 sys_dac_osr = RT1019_SYS_DA_OSR_DIV2;
531 sys_asrc_in = RT1019_ASRC_256FS_DIV2;
532 sys_fifo_clk = RT1019_SEL_FIFO_DIV2;
533 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV2;
536 sys_div_da_filter = RT1019_SYS_DIV_DA_FIL_DIV4;
537 sys_dac_osr = RT1019_SYS_DA_OSR_DIV4;
538 sys_asrc_in = RT1019_ASRC_256FS_DIV4;
539 sys_fifo_clk = RT1019_SEL_FIFO_DIV4;
540 sys_clk_cal = RT1019_SEL_CLK_CAL_DIV4;
546 switch (params_width(params)) {
550 val_len = RT1019_I2S_DL_20;
553 val_len = RT1019_I2S_DL_24;
556 val_len = RT1019_I2S_DL_32;
559 val_len = RT1019_I2S_DL_8;
565 snd_soc_component_update_bits(component, RT1019_TDM_2, RT1019_I2S_DL_MASK,
567 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
568 RT1019_SEL_FIFO_MASK, sys_fifo_clk);
569 snd_soc_component_update_bits(component, RT1019_CLK_TREE_2,
570 RT1019_SYS_DIV_DA_FIL_MASK | RT1019_SYS_DA_OSR_MASK |
571 RT1019_ASRC_256FS_MASK, sys_div_da_filter | sys_dac_osr |
573 snd_soc_component_update_bits(component, RT1019_CLK_TREE_3,
574 RT1019_SEL_CLK_CAL_MASK, sys_clk_cal);
579 static int rt1019_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
581 struct snd_soc_component *component = dai->component;
582 unsigned int reg_val = 0, reg_val2 = 0;
584 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
585 case SND_SOC_DAIFMT_NB_NF:
587 case SND_SOC_DAIFMT_IB_NF:
588 reg_val2 |= RT1019_TDM_BCLK_INV;
594 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
595 case SND_SOC_DAIFMT_I2S:
598 case SND_SOC_DAIFMT_LEFT_J:
599 reg_val |= RT1019_I2S_DF_LEFT;
602 case SND_SOC_DAIFMT_DSP_A:
603 reg_val |= RT1019_I2S_DF_PCM_A_R;
606 case SND_SOC_DAIFMT_DSP_B:
607 reg_val |= RT1019_I2S_DF_PCM_B_R;
614 snd_soc_component_update_bits(component, RT1019_TDM_2,
615 RT1019_I2S_DF_MASK, reg_val);
616 snd_soc_component_update_bits(component, RT1019_TDM_1,
617 RT1019_TDM_BCLK_MASK, reg_val2);
622 static int rt1019_set_dai_sysclk(struct snd_soc_dai *dai,
623 int clk_id, unsigned int freq, int dir)
625 struct snd_soc_component *component = dai->component;
626 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
627 unsigned int reg_val = 0;
629 if (freq == rt1019->sysclk && clk_id == rt1019->sysclk_src)
633 case RT1019_SCLK_S_BCLK:
634 reg_val |= RT1019_CLK_SYS_PRE_SEL_BCLK;
637 case RT1019_SCLK_S_PLL:
638 reg_val |= RT1019_CLK_SYS_PRE_SEL_PLL;
642 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
646 rt1019->sysclk = freq;
647 rt1019->sysclk_src = clk_id;
649 dev_dbg(dai->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
651 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
652 RT1019_CLK_SYS_PRE_SEL_MASK, reg_val);
657 static int rt1019_set_dai_pll(struct snd_soc_dai *dai, int pll_id, int source,
658 unsigned int freq_in, unsigned int freq_out)
660 struct snd_soc_component *component = dai->component;
661 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
662 struct rl6231_pll_code pll_code;
665 if (!freq_in || !freq_out) {
666 dev_dbg(component->dev, "PLL disabled\n");
672 if (source == rt1019->pll_src && freq_in == rt1019->pll_in &&
673 freq_out == rt1019->pll_out)
677 case RT1019_PLL_S_BCLK:
678 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
679 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_BCLK);
682 case RT1019_PLL_S_RC25M:
683 snd_soc_component_update_bits(component, RT1019_CLK_TREE_1,
684 RT1019_PLL_SRC_MASK, RT1019_PLL_SRC_SEL_RC);
688 dev_err(component->dev, "Unknown PLL source %d\n", source);
692 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
694 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
698 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
699 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
700 pll_code.n_code, pll_code.k_code);
702 snd_soc_component_update_bits(component, RT1019_PWR_STRP_2,
703 RT1019_AUTO_BITS_SEL_MASK | RT1019_AUTO_CLK_SEL_MASK,
704 RT1019_AUTO_BITS_SEL_MANU | RT1019_AUTO_CLK_SEL_MANU);
705 snd_soc_component_update_bits(component, RT1019_PLL_1,
706 RT1019_PLL_M_MASK | RT1019_PLL_M_BP_MASK | RT1019_PLL_Q_8_8_MASK,
707 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1019_PLL_M_SFT |
708 pll_code.m_bp << RT1019_PLL_M_BP_SFT |
709 ((pll_code.n_code >> 8) & RT1019_PLL_Q_8_8_MASK));
710 snd_soc_component_update_bits(component, RT1019_PLL_2,
711 RT1019_PLL_Q_7_0_MASK, pll_code.n_code & RT1019_PLL_Q_7_0_MASK);
712 snd_soc_component_update_bits(component, RT1019_PLL_3,
713 RT1019_PLL_K_MASK, pll_code.k_code);
715 rt1019->pll_in = freq_in;
716 rt1019->pll_out = freq_out;
717 rt1019->pll_src = source;
722 static int rt1019_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
723 unsigned int rx_mask, int slots, int slot_width)
725 struct snd_soc_component *component = dai->component;
726 unsigned int val = 0, rx_slotnum;
727 int ret = 0, first_bit;
731 val |= RT1019_I2S_TX_4CH;
734 val |= RT1019_I2S_TX_6CH;
737 val |= RT1019_I2S_TX_8CH;
745 switch (slot_width) {
747 val |= RT1019_I2S_DL_20;
750 val |= RT1019_I2S_DL_24;
753 val |= RT1019_I2S_DL_32;
756 val |= RT1019_I2S_DL_8;
764 /* Rx slot configuration */
765 rx_slotnum = hweight_long(rx_mask);
766 if (rx_slotnum != 1) {
768 dev_err(component->dev, "too many rx slots or zero slot\n");
771 /* This is an assumption that the system sends stereo audio to the
772 * amplifier typically. And the stereo audio is placed in slot 0/2/4/6
773 * as the starting slot. The users could select the channel from
774 * L/R/L+R by "Mono LR Select" control.
776 first_bit = __ffs(rx_mask);
782 snd_soc_component_update_bits(component,
784 RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
785 RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
786 (first_bit << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
787 ((first_bit + 1) << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
793 snd_soc_component_update_bits(component,
795 RT1019_TDM_I2S_TX_L_DAC1_1_MASK |
796 RT1019_TDM_I2S_TX_R_DAC1_1_MASK,
797 ((first_bit - 1) << RT1019_TDM_I2S_TX_L_DAC1_1_SFT) |
798 (first_bit << RT1019_TDM_I2S_TX_R_DAC1_1_SFT));
805 snd_soc_component_update_bits(component, RT1019_TDM_2,
806 RT1019_I2S_CH_TX_MASK | RT1019_I2S_DF_MASK, val);
812 static int rt1019_probe(struct snd_soc_component *component)
814 struct rt1019_priv *rt1019 = snd_soc_component_get_drvdata(component);
816 rt1019->component = component;
817 snd_soc_component_write(component, RT1019_SDB_CTRL, 0xa);
822 #define RT1019_STEREO_RATES SNDRV_PCM_RATE_8000_192000
823 #define RT1019_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
824 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
826 static struct snd_soc_dai_ops rt1019_aif_dai_ops = {
827 .hw_params = rt1019_hw_params,
828 .set_fmt = rt1019_set_dai_fmt,
829 .set_sysclk = rt1019_set_dai_sysclk,
830 .set_pll = rt1019_set_dai_pll,
831 .set_tdm_slot = rt1019_set_tdm_slot,
834 static struct snd_soc_dai_driver rt1019_dai[] = {
836 .name = "rt1019-aif",
839 .stream_name = "AIF Playback",
842 .rates = RT1019_STEREO_RATES,
843 .formats = RT1019_FORMATS,
845 .ops = &rt1019_aif_dai_ops,
849 static const struct snd_soc_component_driver soc_component_dev_rt1019 = {
850 .probe = rt1019_probe,
851 .controls = rt1019_snd_controls,
852 .num_controls = ARRAY_SIZE(rt1019_snd_controls),
853 .dapm_widgets = rt1019_dapm_widgets,
854 .num_dapm_widgets = ARRAY_SIZE(rt1019_dapm_widgets),
855 .dapm_routes = rt1019_dapm_routes,
856 .num_dapm_routes = ARRAY_SIZE(rt1019_dapm_routes),
859 static const struct regmap_config rt1019_regmap = {
862 .use_single_read = true,
863 .use_single_write = true,
864 .max_register = RT1019_CUR_CTRL_13,
865 .volatile_reg = rt1019_volatile_register,
866 .readable_reg = rt1019_readable_register,
867 .cache_type = REGCACHE_RBTREE,
868 .reg_defaults = rt1019_reg,
869 .num_reg_defaults = ARRAY_SIZE(rt1019_reg),
872 static const struct i2c_device_id rt1019_i2c_id[] = {
876 MODULE_DEVICE_TABLE(i2c, rt1019_i2c_id);
878 static const struct of_device_id rt1019_of_match[] = {
879 { .compatible = "realtek,rt1019", },
882 MODULE_DEVICE_TABLE(of, rt1019_of_match);
885 static const struct acpi_device_id rt1019_acpi_match[] = {
889 MODULE_DEVICE_TABLE(acpi, rt1019_acpi_match);
892 static int rt1019_i2c_probe(struct i2c_client *i2c,
893 const struct i2c_device_id *id)
895 struct rt1019_priv *rt1019;
897 unsigned int val, val2, dev_id;
899 rt1019 = devm_kzalloc(&i2c->dev, sizeof(struct rt1019_priv),
904 i2c_set_clientdata(i2c, rt1019);
906 rt1019->regmap = devm_regmap_init_i2c(i2c, &rt1019_regmap);
907 if (IS_ERR(rt1019->regmap)) {
908 ret = PTR_ERR(rt1019->regmap);
909 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
914 regmap_read(rt1019->regmap, RT1019_DEV_ID_1, &val);
915 regmap_read(rt1019->regmap, RT1019_DEV_ID_2, &val2);
916 dev_id = val << 8 | val2;
917 if (dev_id != RT1019_DEVICE_ID_VAL && dev_id != RT1019_DEVICE_ID_VAL2) {
919 "Device with ID register 0x%x is not rt1019\n", dev_id);
923 return devm_snd_soc_register_component(&i2c->dev,
924 &soc_component_dev_rt1019, rt1019_dai, ARRAY_SIZE(rt1019_dai));
927 static struct i2c_driver rt1019_i2c_driver = {
930 .of_match_table = of_match_ptr(rt1019_of_match),
931 .acpi_match_table = ACPI_PTR(rt1019_acpi_match),
933 .probe = rt1019_i2c_probe,
934 .id_table = rt1019_i2c_id,
936 module_i2c_driver(rt1019_i2c_driver);
938 MODULE_DESCRIPTION("ASoC RT1019 driver");
939 MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
940 MODULE_LICENSE("GPL v2");