2 * nau8822.h -- NAU8822 Soc Audio Codec driver
4 * Author: David Lin <ctlin0@nuvoton.com>
5 * Co-author: John Hsu <kchsu0@nuvoton.com>
6 * Co-author: Seven Li <wtli@nuvoton.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
16 #define NAU8822_REG_RESET 0x00
17 #define NAU8822_REG_POWER_MANAGEMENT_1 0x01
18 #define NAU8822_REG_POWER_MANAGEMENT_2 0x02
19 #define NAU8822_REG_POWER_MANAGEMENT_3 0x03
20 #define NAU8822_REG_AUDIO_INTERFACE 0x04
21 #define NAU8822_REG_COMPANDING_CONTROL 0x05
22 #define NAU8822_REG_CLOCKING 0x06
23 #define NAU8822_REG_ADDITIONAL_CONTROL 0x07
24 #define NAU8822_REG_GPIO_CONTROL 0x08
25 #define NAU8822_REG_JACK_DETECT_CONTROL_1 0x09
26 #define NAU8822_REG_DAC_CONTROL 0x0A
27 #define NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME 0x0B
28 #define NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME 0x0C
29 #define NAU8822_REG_JACK_DETECT_CONTROL_2 0x0D
30 #define NAU8822_REG_ADC_CONTROL 0x0E
31 #define NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME 0x0F
32 #define NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME 0x10
33 #define NAU8822_REG_EQ1 0x12
34 #define NAU8822_REG_EQ2 0x13
35 #define NAU8822_REG_EQ3 0x14
36 #define NAU8822_REG_EQ4 0x15
37 #define NAU8822_REG_EQ5 0x16
38 #define NAU8822_REG_DAC_LIMITER_1 0x18
39 #define NAU8822_REG_DAC_LIMITER_2 0x19
40 #define NAU8822_REG_NOTCH_FILTER_1 0x1B
41 #define NAU8822_REG_NOTCH_FILTER_2 0x1C
42 #define NAU8822_REG_NOTCH_FILTER_3 0x1D
43 #define NAU8822_REG_NOTCH_FILTER_4 0x1E
44 #define NAU8822_REG_ALC_CONTROL_1 0x20
45 #define NAU8822_REG_ALC_CONTROL_2 0x21
46 #define NAU8822_REG_ALC_CONTROL_3 0x22
47 #define NAU8822_REG_NOISE_GATE 0x23
48 #define NAU8822_REG_PLL_N 0x24
49 #define NAU8822_REG_PLL_K1 0x25
50 #define NAU8822_REG_PLL_K2 0x26
51 #define NAU8822_REG_PLL_K3 0x27
52 #define NAU8822_REG_3D_CONTROL 0x29
53 #define NAU8822_REG_RIGHT_SPEAKER_CONTROL 0x2B
54 #define NAU8822_REG_INPUT_CONTROL 0x2C
55 #define NAU8822_REG_LEFT_INP_PGA_CONTROL 0x2D
56 #define NAU8822_REG_RIGHT_INP_PGA_CONTROL 0x2E
57 #define NAU8822_REG_LEFT_ADC_BOOST_CONTROL 0x2F
58 #define NAU8822_REG_RIGHT_ADC_BOOST_CONTROL 0x30
59 #define NAU8822_REG_OUTPUT_CONTROL 0x31
60 #define NAU8822_REG_LEFT_MIXER_CONTROL 0x32
61 #define NAU8822_REG_RIGHT_MIXER_CONTROL 0x33
62 #define NAU8822_REG_LHP_VOLUME 0x34
63 #define NAU8822_REG_RHP_VOLUME 0x35
64 #define NAU8822_REG_LSPKOUT_VOLUME 0x36
65 #define NAU8822_REG_RSPKOUT_VOLUME 0x37
66 #define NAU8822_REG_AUX2_MIXER 0x38
67 #define NAU8822_REG_AUX1_MIXER 0x39
68 #define NAU8822_REG_POWER_MANAGEMENT_4 0x3A
69 #define NAU8822_REG_LEFT_TIME_SLOT 0x3B
70 #define NAU8822_REG_MISC 0x3C
71 #define NAU8822_REG_RIGHT_TIME_SLOT 0x3D
72 #define NAU8822_REG_DEVICE_REVISION 0x3E
73 #define NAU8822_REG_DEVICE_ID 0x3F
74 #define NAU8822_REG_DAC_DITHER 0x41
75 #define NAU8822_REG_ALC_ENHANCE_1 0x46
76 #define NAU8822_REG_ALC_ENHANCE_2 0x47
77 #define NAU8822_REG_192KHZ_SAMPLING 0x48
78 #define NAU8822_REG_MISC_CONTROL 0x49
79 #define NAU8822_REG_INPUT_TIEOFF 0x4A
80 #define NAU8822_REG_POWER_REDUCTION 0x4B
81 #define NAU8822_REG_AGC_PEAK2PEAK 0x4C
82 #define NAU8822_REG_AGC_PEAK_DETECT 0x4D
83 #define NAU8822_REG_AUTOMUTE_CONTROL 0x4E
84 #define NAU8822_REG_OUTPUT_TIEOFF 0x4F
85 #define NAU8822_REG_MAX_REGISTER NAU8822_REG_OUTPUT_TIEOFF
87 /* NAU8822_REG_POWER_MANAGEMENT_1 (0x1) */
88 #define NAU8822_REFIMP_MASK 0x3
89 #define NAU8822_REFIMP_80K 0x1
90 #define NAU8822_REFIMP_300K 0x2
91 #define NAU8822_REFIMP_3K 0x3
92 #define NAU8822_IOBUF_EN (0x1 << 2)
93 #define NAU8822_ABIAS_EN (0x1 << 3)
95 /* NAU8822_REG_AUDIO_INTERFACE (0x4) */
96 #define NAU8822_AIFMT_MASK (0x3 << 3)
97 #define NAU8822_WLEN_MASK (0x3 << 5)
98 #define NAU8822_WLEN_20 (0x1 << 5)
99 #define NAU8822_WLEN_24 (0x2 << 5)
100 #define NAU8822_WLEN_32 (0x3 << 5)
101 #define NAU8822_LRP_MASK (0x1 << 7)
102 #define NAU8822_BCLKP_MASK (0x1 << 8)
104 /* NAU8822_REG_COMPANDING_CONTROL (0x5) */
105 #define NAU8822_ADDAP_SFT 0
106 #define NAU8822_ADCCM_SFT 1
107 #define NAU8822_DACCM_SFT 3
109 /* NAU8822_REG_CLOCKING (0x6) */
110 #define NAU8822_CLKIOEN_MASK 0x1
111 #define NAU8822_MCLKSEL_SFT 5
112 #define NAU8822_MCLKSEL_MASK (0x7 << 5)
113 #define NAU8822_BCLKSEL_SFT 2
114 #define NAU8822_BCLKSEL_MASK (0x7 << 2)
115 #define NAU8822_CLKM_MASK (0x1 << 8)
116 #define NAU8822_CLKM_MCLK (0x0 << 8)
117 #define NAU8822_CLKM_PLL (0x1 << 8)
119 /* NAU8822_REG_ADDITIONAL_CONTROL (0x08) */
120 #define NAU8822_SMPLR_SFT 1
121 #define NAU8822_SMPLR_MASK (0x7 << 1)
122 #define NAU8822_SMPLR_48K (0x0 << 1)
123 #define NAU8822_SMPLR_32K (0x1 << 1)
124 #define NAU8822_SMPLR_24K (0x2 << 1)
125 #define NAU8822_SMPLR_16K (0x3 << 1)
126 #define NAU8822_SMPLR_12K (0x4 << 1)
127 #define NAU8822_SMPLR_8K (0x5 << 1)
129 /* NAU8822_REG_EQ1 (0x12) */
130 #define NAU8822_EQ1GC_SFT 0
131 #define NAU8822_EQ1CF_SFT 5
132 #define NAU8822_EQM_SFT 8
134 /* NAU8822_REG_EQ2 (0x13) */
135 #define NAU8822_EQ2GC_SFT 0
136 #define NAU8822_EQ2CF_SFT 5
137 #define NAU8822_EQ2BW_SFT 8
139 /* NAU8822_REG_EQ3 (0x14) */
140 #define NAU8822_EQ3GC_SFT 0
141 #define NAU8822_EQ3CF_SFT 5
142 #define NAU8822_EQ3BW_SFT 8
144 /* NAU8822_REG_EQ4 (0x15) */
145 #define NAU8822_EQ4GC_SFT 0
146 #define NAU8822_EQ4CF_SFT 5
147 #define NAU8822_EQ4BW_SFT 8
149 /* NAU8822_REG_EQ5 (0x16) */
150 #define NAU8822_EQ5GC_SFT 0
151 #define NAU8822_EQ5CF_SFT 5
153 /* NAU8822_REG_ALC_CONTROL_1 (0x20) */
154 #define NAU8822_ALCMINGAIN_SFT 0
155 #define NAU8822_ALCMXGAIN_SFT 3
156 #define NAU8822_ALCEN_SFT 7
158 /* NAU8822_REG_ALC_CONTROL_2 (0x21) */
159 #define NAU8822_ALCSL_SFT 0
160 #define NAU8822_ALCHT_SFT 4
162 /* NAU8822_REG_ALC_CONTROL_3 (0x22) */
163 #define NAU8822_ALCATK_SFT 0
164 #define NAU8822_ALCDCY_SFT 4
165 #define NAU8822_ALCM_SFT 8
167 /* NAU8822_REG_PLL_N (0x24) */
168 #define NAU8822_PLLMCLK_DIV2 (0x1 << 4)
169 #define NAU8822_PLLN_MASK 0xF
171 #define NAU8822_PLLK1_SFT 18
172 #define NAU8822_PLLK1_MASK 0x3F
174 /* NAU8822_REG_PLL_K2 (0x26) */
175 #define NAU8822_PLLK2_SFT 9
176 #define NAU8822_PLLK2_MASK 0x1FF
178 /* NAU8822_REG_PLL_K3 (0x27) */
179 #define NAU8822_PLLK3_MASK 0x1FF
181 /* System Clock Source */
194 /* Codec Private Data */
197 struct regmap *regmap;
199 struct nau8822_pll pll;
204 #endif /* __NAU8822_H__ */