2 * nau8822.c -- NAU8822 ALSA Soc Audio Codec driver
4 * Copyright 2017 Nuvoton Technology Corp.
6 * Author: David Lin <ctlin0@nuvoton.com>
7 * Co-author: John Hsu <kchsu0@nuvoton.com>
8 * Co-author: Seven Li <wtli@nuvoton.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
23 #include <linux/i2c.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
26 #include <sound/core.h>
27 #include <sound/pcm.h>
28 #include <sound/pcm_params.h>
29 #include <sound/soc.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <asm/div64.h>
35 #define NAU_PLL_FREQ_MAX 100000000
36 #define NAU_PLL_FREQ_MIN 90000000
37 #define NAU_PLL_REF_MAX 33000000
38 #define NAU_PLL_REF_MIN 8000000
39 #define NAU_PLL_OPTOP_MIN 6
41 static const int nau8822_mclk_scaler[] = { 10, 15, 20, 30, 40, 60, 80, 120 };
43 static const struct reg_default nau8822_reg_defaults[] = {
44 { NAU8822_REG_POWER_MANAGEMENT_1, 0x0000 },
45 { NAU8822_REG_POWER_MANAGEMENT_2, 0x0000 },
46 { NAU8822_REG_POWER_MANAGEMENT_3, 0x0000 },
47 { NAU8822_REG_AUDIO_INTERFACE, 0x0050 },
48 { NAU8822_REG_COMPANDING_CONTROL, 0x0000 },
49 { NAU8822_REG_CLOCKING, 0x0140 },
50 { NAU8822_REG_ADDITIONAL_CONTROL, 0x0000 },
51 { NAU8822_REG_GPIO_CONTROL, 0x0000 },
52 { NAU8822_REG_JACK_DETECT_CONTROL_1, 0x0000 },
53 { NAU8822_REG_DAC_CONTROL, 0x0000 },
54 { NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME, 0x00ff },
55 { NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0x00ff },
56 { NAU8822_REG_JACK_DETECT_CONTROL_2, 0x0000 },
57 { NAU8822_REG_ADC_CONTROL, 0x0100 },
58 { NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME, 0x00ff },
59 { NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0x00ff },
60 { NAU8822_REG_EQ1, 0x012c },
61 { NAU8822_REG_EQ2, 0x002c },
62 { NAU8822_REG_EQ3, 0x002c },
63 { NAU8822_REG_EQ4, 0x002c },
64 { NAU8822_REG_EQ5, 0x002c },
65 { NAU8822_REG_DAC_LIMITER_1, 0x0032 },
66 { NAU8822_REG_DAC_LIMITER_2, 0x0000 },
67 { NAU8822_REG_NOTCH_FILTER_1, 0x0000 },
68 { NAU8822_REG_NOTCH_FILTER_2, 0x0000 },
69 { NAU8822_REG_NOTCH_FILTER_3, 0x0000 },
70 { NAU8822_REG_NOTCH_FILTER_4, 0x0000 },
71 { NAU8822_REG_ALC_CONTROL_1, 0x0038 },
72 { NAU8822_REG_ALC_CONTROL_2, 0x000b },
73 { NAU8822_REG_ALC_CONTROL_3, 0x0032 },
74 { NAU8822_REG_NOISE_GATE, 0x0010 },
75 { NAU8822_REG_PLL_N, 0x0008 },
76 { NAU8822_REG_PLL_K1, 0x000c },
77 { NAU8822_REG_PLL_K2, 0x0093 },
78 { NAU8822_REG_PLL_K3, 0x00e9 },
79 { NAU8822_REG_3D_CONTROL, 0x0000 },
80 { NAU8822_REG_RIGHT_SPEAKER_CONTROL, 0x0000 },
81 { NAU8822_REG_INPUT_CONTROL, 0x0033 },
82 { NAU8822_REG_LEFT_INP_PGA_CONTROL, 0x0010 },
83 { NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0x0010 },
84 { NAU8822_REG_LEFT_ADC_BOOST_CONTROL, 0x0100 },
85 { NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0x0100 },
86 { NAU8822_REG_OUTPUT_CONTROL, 0x0002 },
87 { NAU8822_REG_LEFT_MIXER_CONTROL, 0x0001 },
88 { NAU8822_REG_RIGHT_MIXER_CONTROL, 0x0001 },
89 { NAU8822_REG_LHP_VOLUME, 0x0039 },
90 { NAU8822_REG_RHP_VOLUME, 0x0039 },
91 { NAU8822_REG_LSPKOUT_VOLUME, 0x0039 },
92 { NAU8822_REG_RSPKOUT_VOLUME, 0x0039 },
93 { NAU8822_REG_AUX2_MIXER, 0x0001 },
94 { NAU8822_REG_AUX1_MIXER, 0x0001 },
95 { NAU8822_REG_POWER_MANAGEMENT_4, 0x0000 },
96 { NAU8822_REG_LEFT_TIME_SLOT, 0x0000 },
97 { NAU8822_REG_MISC, 0x0020 },
98 { NAU8822_REG_RIGHT_TIME_SLOT, 0x0000 },
99 { NAU8822_REG_DEVICE_REVISION, 0x007f },
100 { NAU8822_REG_DEVICE_ID, 0x001a },
101 { NAU8822_REG_DAC_DITHER, 0x0114 },
102 { NAU8822_REG_ALC_ENHANCE_1, 0x0000 },
103 { NAU8822_REG_ALC_ENHANCE_2, 0x0000 },
104 { NAU8822_REG_192KHZ_SAMPLING, 0x0008 },
105 { NAU8822_REG_MISC_CONTROL, 0x0000 },
106 { NAU8822_REG_INPUT_TIEOFF, 0x0000 },
107 { NAU8822_REG_POWER_REDUCTION, 0x0000 },
108 { NAU8822_REG_AGC_PEAK2PEAK, 0x0000 },
109 { NAU8822_REG_AGC_PEAK_DETECT, 0x0000 },
110 { NAU8822_REG_AUTOMUTE_CONTROL, 0x0000 },
111 { NAU8822_REG_OUTPUT_TIEOFF, 0x0000 },
114 static bool nau8822_readable_reg(struct device *dev, unsigned int reg)
117 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
118 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
119 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
120 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
121 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
122 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
123 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
124 case NAU8822_REG_3D_CONTROL:
125 case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
126 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
127 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
128 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
129 case NAU8822_REG_DAC_DITHER:
130 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
131 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
138 static bool nau8822_writeable_reg(struct device *dev, unsigned int reg)
141 case NAU8822_REG_RESET ... NAU8822_REG_JACK_DETECT_CONTROL_1:
142 case NAU8822_REG_DAC_CONTROL ... NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME:
143 case NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME:
144 case NAU8822_REG_EQ1 ... NAU8822_REG_EQ5:
145 case NAU8822_REG_DAC_LIMITER_1 ... NAU8822_REG_DAC_LIMITER_2:
146 case NAU8822_REG_NOTCH_FILTER_1 ... NAU8822_REG_NOTCH_FILTER_4:
147 case NAU8822_REG_ALC_CONTROL_1 ...NAU8822_REG_PLL_K3:
148 case NAU8822_REG_3D_CONTROL:
149 case NAU8822_REG_RIGHT_SPEAKER_CONTROL:
150 case NAU8822_REG_INPUT_CONTROL ... NAU8822_REG_LEFT_ADC_BOOST_CONTROL:
151 case NAU8822_REG_RIGHT_ADC_BOOST_CONTROL ... NAU8822_REG_AUX1_MIXER:
152 case NAU8822_REG_POWER_MANAGEMENT_4 ... NAU8822_REG_DEVICE_ID:
153 case NAU8822_REG_DAC_DITHER:
154 case NAU8822_REG_ALC_ENHANCE_1 ... NAU8822_REG_MISC_CONTROL:
155 case NAU8822_REG_INPUT_TIEOFF ... NAU8822_REG_OUTPUT_TIEOFF:
162 static bool nau8822_volatile(struct device *dev, unsigned int reg)
165 case NAU8822_REG_RESET:
166 case NAU8822_REG_DEVICE_REVISION:
167 case NAU8822_REG_DEVICE_ID:
168 case NAU8822_REG_AGC_PEAK2PEAK:
169 case NAU8822_REG_AGC_PEAK_DETECT:
170 case NAU8822_REG_AUTOMUTE_CONTROL:
177 /* The EQ parameters get function is to get the 5 band equalizer control.
178 * The regmap raw read can't work here because regmap doesn't provide
179 * value format for value width of 9 bits. Therefore, the driver reads data
180 * from cache and makes value format according to the endianness of
181 * bytes type control element.
183 static int nau8822_eq_get(struct snd_kcontrol *kcontrol,
184 struct snd_ctl_elem_value *ucontrol)
186 struct snd_soc_component *component =
187 snd_soc_kcontrol_component(kcontrol);
188 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
192 val = (u16 *)ucontrol->value.bytes.data;
193 reg = NAU8822_REG_EQ1;
194 for (i = 0; i < params->max / sizeof(u16); i++) {
195 reg_val = snd_soc_component_read32(component, reg + i);
196 /* conversion of 16-bit integers between native CPU format
197 * and big endian format
199 reg_val = cpu_to_be16(reg_val);
200 memcpy(val + i, ®_val, sizeof(reg_val));
206 /* The EQ parameters put function is to make configuration of 5 band equalizer
207 * control. These configuration includes central frequency, equalizer gain,
208 * cut-off frequency, bandwidth control, and equalizer path.
209 * The regmap raw write can't work here because regmap doesn't provide
210 * register and value format for register with address 7 bits and value 9 bits.
211 * Therefore, the driver makes value format according to the endianness of
212 * bytes type control element and writes data to codec.
214 static int nau8822_eq_put(struct snd_kcontrol *kcontrol,
215 struct snd_ctl_elem_value *ucontrol)
217 struct snd_soc_component *component =
218 snd_soc_kcontrol_component(kcontrol);
219 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
224 data = kmemdup(ucontrol->value.bytes.data,
225 params->max, GFP_KERNEL | GFP_DMA);
230 reg = NAU8822_REG_EQ1;
231 for (i = 0; i < params->max / sizeof(u16); i++) {
232 /* conversion of 16-bit integers between native CPU format
233 * and big endian format
235 value = be16_to_cpu(*(val + i));
236 ret = snd_soc_component_write(component, reg + i, value);
238 dev_err(component->dev,
239 "EQ configuration fail, register: %x ret: %d\n",
250 static const char * const nau8822_companding[] = {
251 "Off", "NC", "u-law", "A-law"};
253 static const struct soc_enum nau8822_companding_adc_enum =
254 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_ADCCM_SFT,
255 ARRAY_SIZE(nau8822_companding), nau8822_companding);
257 static const struct soc_enum nau8822_companding_dac_enum =
258 SOC_ENUM_SINGLE(NAU8822_REG_COMPANDING_CONTROL, NAU8822_DACCM_SFT,
259 ARRAY_SIZE(nau8822_companding), nau8822_companding);
261 static const char * const nau8822_eqmode[] = {"Capture", "Playback"};
263 static const struct soc_enum nau8822_eqmode_enum =
264 SOC_ENUM_SINGLE(NAU8822_REG_EQ1, NAU8822_EQM_SFT,
265 ARRAY_SIZE(nau8822_eqmode), nau8822_eqmode);
267 static const char * const nau8822_alc1[] = {"Off", "Right", "Left", "Both"};
268 static const char * const nau8822_alc3[] = {"Normal", "Limiter"};
270 static const struct soc_enum nau8822_alc_enable_enum =
271 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_1, NAU8822_ALCEN_SFT,
272 ARRAY_SIZE(nau8822_alc1), nau8822_alc1);
274 static const struct soc_enum nau8822_alc_mode_enum =
275 SOC_ENUM_SINGLE(NAU8822_REG_ALC_CONTROL_3, NAU8822_ALCM_SFT,
276 ARRAY_SIZE(nau8822_alc3), nau8822_alc3);
278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
279 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
280 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
281 static const DECLARE_TLV_DB_SCALE(pga_boost_tlv, 0, 2000, 0);
282 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
283 static const DECLARE_TLV_DB_SCALE(limiter_tlv, 0, 100, 0);
285 static const struct snd_kcontrol_new nau8822_snd_controls[] = {
286 SOC_ENUM("ADC Companding", nau8822_companding_adc_enum),
287 SOC_ENUM("DAC Companding", nau8822_companding_dac_enum),
289 SOC_ENUM("EQ Function", nau8822_eqmode_enum),
290 SND_SOC_BYTES_EXT("EQ Parameters", 10,
291 nau8822_eq_get, nau8822_eq_put),
293 SOC_DOUBLE("DAC Inversion Switch",
294 NAU8822_REG_DAC_CONTROL, 0, 1, 1, 0),
295 SOC_DOUBLE_R_TLV("PCM Volume",
296 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
297 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
299 SOC_SINGLE("High Pass Filter Switch",
300 NAU8822_REG_ADC_CONTROL, 8, 1, 0),
301 SOC_SINGLE("High Pass Cut Off",
302 NAU8822_REG_ADC_CONTROL, 4, 7, 0),
304 SOC_DOUBLE("ADC Inversion Switch",
305 NAU8822_REG_ADC_CONTROL, 0, 1, 1, 0),
306 SOC_DOUBLE_R_TLV("ADC Volume",
307 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
308 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME, 0, 255, 0, digital_tlv),
310 SOC_SINGLE("DAC Limiter Switch",
311 NAU8822_REG_DAC_LIMITER_1, 8, 1, 0),
312 SOC_SINGLE("DAC Limiter Decay",
313 NAU8822_REG_DAC_LIMITER_1, 4, 15, 0),
314 SOC_SINGLE("DAC Limiter Attack",
315 NAU8822_REG_DAC_LIMITER_1, 0, 15, 0),
316 SOC_SINGLE("DAC Limiter Threshold",
317 NAU8822_REG_DAC_LIMITER_2, 4, 7, 0),
318 SOC_SINGLE_TLV("DAC Limiter Volume",
319 NAU8822_REG_DAC_LIMITER_2, 0, 12, 0, limiter_tlv),
321 SOC_ENUM("ALC Mode", nau8822_alc_mode_enum),
322 SOC_ENUM("ALC Enable Switch", nau8822_alc_enable_enum),
323 SOC_SINGLE("ALC Min Gain",
324 NAU8822_REG_ALC_CONTROL_1, 0, 7, 0),
325 SOC_SINGLE("ALC Max Gain",
326 NAU8822_REG_ALC_CONTROL_1, 3, 7, 0),
327 SOC_SINGLE("ALC Hold",
328 NAU8822_REG_ALC_CONTROL_2, 4, 10, 0),
329 SOC_SINGLE("ALC Target",
330 NAU8822_REG_ALC_CONTROL_2, 0, 15, 0),
331 SOC_SINGLE("ALC Decay",
332 NAU8822_REG_ALC_CONTROL_3, 4, 10, 0),
333 SOC_SINGLE("ALC Attack",
334 NAU8822_REG_ALC_CONTROL_3, 0, 10, 0),
335 SOC_SINGLE("ALC Noise Gate Switch",
336 NAU8822_REG_NOISE_GATE, 3, 1, 0),
337 SOC_SINGLE("ALC Noise Gate Threshold",
338 NAU8822_REG_NOISE_GATE, 0, 7, 0),
340 SOC_DOUBLE_R("PGA ZC Switch",
341 NAU8822_REG_LEFT_INP_PGA_CONTROL,
342 NAU8822_REG_RIGHT_INP_PGA_CONTROL,
344 SOC_DOUBLE_R_TLV("PGA Volume",
345 NAU8822_REG_LEFT_INP_PGA_CONTROL,
346 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 0, 63, 0, inpga_tlv),
348 SOC_DOUBLE_R("Headphone ZC Switch",
349 NAU8822_REG_LHP_VOLUME,
350 NAU8822_REG_RHP_VOLUME, 7, 1, 0),
351 SOC_DOUBLE_R("Headphone Playback Switch",
352 NAU8822_REG_LHP_VOLUME,
353 NAU8822_REG_RHP_VOLUME, 6, 1, 1),
354 SOC_DOUBLE_R_TLV("Headphone Volume",
355 NAU8822_REG_LHP_VOLUME,
356 NAU8822_REG_RHP_VOLUME, 0, 63, 0, spk_tlv),
358 SOC_DOUBLE_R("Speaker ZC Switch",
359 NAU8822_REG_LSPKOUT_VOLUME,
360 NAU8822_REG_RSPKOUT_VOLUME, 7, 1, 0),
361 SOC_DOUBLE_R("Speaker Playback Switch",
362 NAU8822_REG_LSPKOUT_VOLUME,
363 NAU8822_REG_RSPKOUT_VOLUME, 6, 1, 1),
364 SOC_DOUBLE_R_TLV("Speaker Volume",
365 NAU8822_REG_LSPKOUT_VOLUME,
366 NAU8822_REG_RSPKOUT_VOLUME, 0, 63, 0, spk_tlv),
368 SOC_DOUBLE_R("AUXOUT Playback Switch",
369 NAU8822_REG_AUX2_MIXER,
370 NAU8822_REG_AUX1_MIXER, 6, 1, 1),
372 SOC_DOUBLE_R_TLV("PGA Boost Volume",
373 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
374 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 8, 1, 0, pga_boost_tlv),
375 SOC_DOUBLE_R_TLV("L2/R2 Boost Volume",
376 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
377 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 4, 7, 0, boost_tlv),
378 SOC_DOUBLE_R_TLV("Aux Boost Volume",
379 NAU8822_REG_LEFT_ADC_BOOST_CONTROL,
380 NAU8822_REG_RIGHT_ADC_BOOST_CONTROL, 0, 7, 0, boost_tlv),
382 SOC_SINGLE("DAC 128x Oversampling Switch",
383 NAU8822_REG_DAC_CONTROL, 5, 1, 0),
384 SOC_SINGLE("ADC 128x Oversampling Switch",
385 NAU8822_REG_ADC_CONTROL, 5, 1, 0),
388 /* LMAIN and RMAIN Mixer */
389 static const struct snd_kcontrol_new nau8822_left_out_mixer[] = {
390 SOC_DAPM_SINGLE("LINMIX Switch",
391 NAU8822_REG_LEFT_MIXER_CONTROL, 1, 1, 0),
392 SOC_DAPM_SINGLE("LAUX Switch",
393 NAU8822_REG_LEFT_MIXER_CONTROL, 5, 1, 0),
394 SOC_DAPM_SINGLE("LDAC Switch",
395 NAU8822_REG_LEFT_MIXER_CONTROL, 0, 1, 0),
396 SOC_DAPM_SINGLE("RDAC Switch",
397 NAU8822_REG_OUTPUT_CONTROL, 5, 1, 0),
400 static const struct snd_kcontrol_new nau8822_right_out_mixer[] = {
401 SOC_DAPM_SINGLE("RINMIX Switch",
402 NAU8822_REG_RIGHT_MIXER_CONTROL, 1, 1, 0),
403 SOC_DAPM_SINGLE("RAUX Switch",
404 NAU8822_REG_RIGHT_MIXER_CONTROL, 5, 1, 0),
405 SOC_DAPM_SINGLE("RDAC Switch",
406 NAU8822_REG_RIGHT_MIXER_CONTROL, 0, 1, 0),
407 SOC_DAPM_SINGLE("LDAC Switch",
408 NAU8822_REG_OUTPUT_CONTROL, 6, 1, 0),
411 /* AUX1 and AUX2 Mixer */
412 static const struct snd_kcontrol_new nau8822_auxout1_mixer[] = {
413 SOC_DAPM_SINGLE("RDAC Switch", NAU8822_REG_AUX1_MIXER, 0, 1, 0),
414 SOC_DAPM_SINGLE("RMIX Switch", NAU8822_REG_AUX1_MIXER, 1, 1, 0),
415 SOC_DAPM_SINGLE("RINMIX Switch", NAU8822_REG_AUX1_MIXER, 2, 1, 0),
416 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX1_MIXER, 3, 1, 0),
417 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX1_MIXER, 4, 1, 0),
420 static const struct snd_kcontrol_new nau8822_auxout2_mixer[] = {
421 SOC_DAPM_SINGLE("LDAC Switch", NAU8822_REG_AUX2_MIXER, 0, 1, 0),
422 SOC_DAPM_SINGLE("LMIX Switch", NAU8822_REG_AUX2_MIXER, 1, 1, 0),
423 SOC_DAPM_SINGLE("LINMIX Switch", NAU8822_REG_AUX2_MIXER, 2, 1, 0),
424 SOC_DAPM_SINGLE("AUX1MIX Output Switch",
425 NAU8822_REG_AUX2_MIXER, 3, 1, 0),
429 static const struct snd_kcontrol_new nau8822_left_input_mixer[] = {
430 SOC_DAPM_SINGLE("L2 Switch", NAU8822_REG_INPUT_CONTROL, 2, 1, 0),
431 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 1, 1, 0),
432 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 0, 1, 0),
434 static const struct snd_kcontrol_new nau8822_right_input_mixer[] = {
435 SOC_DAPM_SINGLE("R2 Switch", NAU8822_REG_INPUT_CONTROL, 6, 1, 0),
436 SOC_DAPM_SINGLE("MicN Switch", NAU8822_REG_INPUT_CONTROL, 5, 1, 0),
437 SOC_DAPM_SINGLE("MicP Switch", NAU8822_REG_INPUT_CONTROL, 4, 1, 0),
440 /* Loopback Switch */
441 static const struct snd_kcontrol_new nau8822_loopback =
442 SOC_DAPM_SINGLE("Switch", NAU8822_REG_COMPANDING_CONTROL,
443 NAU8822_ADDAP_SFT, 1, 0);
445 static int check_mclk_select_pll(struct snd_soc_dapm_widget *source,
446 struct snd_soc_dapm_widget *sink)
448 struct snd_soc_component *component =
449 snd_soc_dapm_to_component(source->dapm);
452 value = snd_soc_component_read32(component, NAU8822_REG_CLOCKING);
454 return (value & NAU8822_CLKM_MASK);
457 static const struct snd_soc_dapm_widget nau8822_dapm_widgets[] = {
458 SND_SOC_DAPM_DAC("Left DAC", "Left HiFi Playback",
459 NAU8822_REG_POWER_MANAGEMENT_3, 0, 0),
460 SND_SOC_DAPM_DAC("Right DAC", "Right HiFi Playback",
461 NAU8822_REG_POWER_MANAGEMENT_3, 1, 0),
462 SND_SOC_DAPM_ADC("Left ADC", "Left HiFi Capture",
463 NAU8822_REG_POWER_MANAGEMENT_2, 0, 0),
464 SND_SOC_DAPM_ADC("Right ADC", "Right HiFi Capture",
465 NAU8822_REG_POWER_MANAGEMENT_2, 1, 0),
467 SOC_MIXER_ARRAY("Left Output Mixer",
468 NAU8822_REG_POWER_MANAGEMENT_3, 2, 0, nau8822_left_out_mixer),
469 SOC_MIXER_ARRAY("Right Output Mixer",
470 NAU8822_REG_POWER_MANAGEMENT_3, 3, 0, nau8822_right_out_mixer),
471 SOC_MIXER_ARRAY("AUX1 Output Mixer",
472 NAU8822_REG_POWER_MANAGEMENT_1, 7, 0, nau8822_auxout1_mixer),
473 SOC_MIXER_ARRAY("AUX2 Output Mixer",
474 NAU8822_REG_POWER_MANAGEMENT_1, 6, 0, nau8822_auxout2_mixer),
476 SOC_MIXER_ARRAY("Left Input Mixer",
477 NAU8822_REG_POWER_MANAGEMENT_2,
478 2, 0, nau8822_left_input_mixer),
479 SOC_MIXER_ARRAY("Right Input Mixer",
480 NAU8822_REG_POWER_MANAGEMENT_2,
481 3, 0, nau8822_right_input_mixer),
483 SND_SOC_DAPM_PGA("Left Boost Mixer",
484 NAU8822_REG_POWER_MANAGEMENT_2, 4, 0, NULL, 0),
485 SND_SOC_DAPM_PGA("Right Boost Mixer",
486 NAU8822_REG_POWER_MANAGEMENT_2, 5, 0, NULL, 0),
488 SND_SOC_DAPM_PGA("Left Capture PGA",
489 NAU8822_REG_LEFT_INP_PGA_CONTROL, 6, 1, NULL, 0),
490 SND_SOC_DAPM_PGA("Right Capture PGA",
491 NAU8822_REG_RIGHT_INP_PGA_CONTROL, 6, 1, NULL, 0),
493 SND_SOC_DAPM_PGA("Left Headphone Out",
494 NAU8822_REG_POWER_MANAGEMENT_2, 7, 0, NULL, 0),
495 SND_SOC_DAPM_PGA("Right Headphone Out",
496 NAU8822_REG_POWER_MANAGEMENT_2, 8, 0, NULL, 0),
498 SND_SOC_DAPM_PGA("Left Speaker Out",
499 NAU8822_REG_POWER_MANAGEMENT_3, 6, 0, NULL, 0),
500 SND_SOC_DAPM_PGA("Right Speaker Out",
501 NAU8822_REG_POWER_MANAGEMENT_3, 5, 0, NULL, 0),
503 SND_SOC_DAPM_PGA("AUX1 Out",
504 NAU8822_REG_POWER_MANAGEMENT_3, 8, 0, NULL, 0),
505 SND_SOC_DAPM_PGA("AUX2 Out",
506 NAU8822_REG_POWER_MANAGEMENT_3, 7, 0, NULL, 0),
508 SND_SOC_DAPM_SUPPLY("Mic Bias",
509 NAU8822_REG_POWER_MANAGEMENT_1, 4, 0, NULL, 0),
510 SND_SOC_DAPM_SUPPLY("PLL",
511 NAU8822_REG_POWER_MANAGEMENT_1, 5, 0, NULL, 0),
513 SND_SOC_DAPM_SWITCH("Digital Loopback", SND_SOC_NOPM, 0, 0,
516 SND_SOC_DAPM_INPUT("LMICN"),
517 SND_SOC_DAPM_INPUT("LMICP"),
518 SND_SOC_DAPM_INPUT("RMICN"),
519 SND_SOC_DAPM_INPUT("RMICP"),
520 SND_SOC_DAPM_INPUT("LAUX"),
521 SND_SOC_DAPM_INPUT("RAUX"),
522 SND_SOC_DAPM_INPUT("L2"),
523 SND_SOC_DAPM_INPUT("R2"),
524 SND_SOC_DAPM_OUTPUT("LHP"),
525 SND_SOC_DAPM_OUTPUT("RHP"),
526 SND_SOC_DAPM_OUTPUT("LSPK"),
527 SND_SOC_DAPM_OUTPUT("RSPK"),
528 SND_SOC_DAPM_OUTPUT("AUXOUT1"),
529 SND_SOC_DAPM_OUTPUT("AUXOUT2"),
532 static const struct snd_soc_dapm_route nau8822_dapm_routes[] = {
533 {"Right DAC", NULL, "PLL", check_mclk_select_pll},
534 {"Left DAC", NULL, "PLL", check_mclk_select_pll},
536 /* LMAIN and RMAIN Mixer */
537 {"Right Output Mixer", "LDAC Switch", "Left DAC"},
538 {"Right Output Mixer", "RDAC Switch", "Right DAC"},
539 {"Right Output Mixer", "RAUX Switch", "RAUX"},
540 {"Right Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
542 {"Left Output Mixer", "LDAC Switch", "Left DAC"},
543 {"Left Output Mixer", "RDAC Switch", "Right DAC"},
544 {"Left Output Mixer", "LAUX Switch", "LAUX"},
545 {"Left Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
547 /* AUX1 and AUX2 Mixer */
548 {"AUX1 Output Mixer", "RDAC Switch", "Right DAC"},
549 {"AUX1 Output Mixer", "RMIX Switch", "Right Output Mixer"},
550 {"AUX1 Output Mixer", "RINMIX Switch", "Right Boost Mixer"},
551 {"AUX1 Output Mixer", "LDAC Switch", "Left DAC"},
552 {"AUX1 Output Mixer", "LMIX Switch", "Left Output Mixer"},
554 {"AUX2 Output Mixer", "LDAC Switch", "Left DAC"},
555 {"AUX2 Output Mixer", "LMIX Switch", "Left Output Mixer"},
556 {"AUX2 Output Mixer", "LINMIX Switch", "Left Boost Mixer"},
557 {"AUX2 Output Mixer", "AUX1MIX Output Switch", "AUX1 Output Mixer"},
560 {"Right Headphone Out", NULL, "Right Output Mixer"},
561 {"RHP", NULL, "Right Headphone Out"},
563 {"Left Headphone Out", NULL, "Left Output Mixer"},
564 {"LHP", NULL, "Left Headphone Out"},
566 {"Right Speaker Out", NULL, "Right Output Mixer"},
567 {"RSPK", NULL, "Right Speaker Out"},
569 {"Left Speaker Out", NULL, "Left Output Mixer"},
570 {"LSPK", NULL, "Left Speaker Out"},
572 {"AUX1 Out", NULL, "AUX1 Output Mixer"},
573 {"AUX2 Out", NULL, "AUX2 Output Mixer"},
574 {"AUXOUT1", NULL, "AUX1 Out"},
575 {"AUXOUT2", NULL, "AUX2 Out"},
578 {"Right ADC", NULL, "PLL", check_mclk_select_pll},
579 {"Left ADC", NULL, "PLL", check_mclk_select_pll},
581 {"Right ADC", NULL, "Right Boost Mixer"},
583 {"Right Boost Mixer", NULL, "RAUX"},
584 {"Right Boost Mixer", NULL, "Right Capture PGA"},
585 {"Right Boost Mixer", NULL, "R2"},
587 {"Left ADC", NULL, "Left Boost Mixer"},
589 {"Left Boost Mixer", NULL, "LAUX"},
590 {"Left Boost Mixer", NULL, "Left Capture PGA"},
591 {"Left Boost Mixer", NULL, "L2"},
594 {"Right Capture PGA", NULL, "Right Input Mixer"},
595 {"Left Capture PGA", NULL, "Left Input Mixer"},
597 /* Enable Microphone Power */
598 {"Right Capture PGA", NULL, "Mic Bias"},
599 {"Left Capture PGA", NULL, "Mic Bias"},
601 {"Right Input Mixer", "R2 Switch", "R2"},
602 {"Right Input Mixer", "MicN Switch", "RMICN"},
603 {"Right Input Mixer", "MicP Switch", "RMICP"},
605 {"Left Input Mixer", "L2 Switch", "L2"},
606 {"Left Input Mixer", "MicN Switch", "LMICN"},
607 {"Left Input Mixer", "MicP Switch", "LMICP"},
609 /* Digital Loopback */
610 {"Digital Loopback", "Switch", "Left ADC"},
611 {"Digital Loopback", "Switch", "Right ADC"},
612 {"Left DAC", NULL, "Digital Loopback"},
613 {"Right DAC", NULL, "Digital Loopback"},
616 static int nau8822_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
617 unsigned int freq, int dir)
619 struct snd_soc_component *component = dai->component;
620 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
622 nau8822->div_id = clk_id;
623 nau8822->sysclk = freq;
624 dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
625 clk_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
630 static int nau8822_calc_pll(unsigned int pll_in, unsigned int fs,
631 struct nau8822_pll *pll_param)
633 u64 f2, f2_max, pll_ratio;
636 if (pll_in > NAU_PLL_REF_MAX || pll_in < NAU_PLL_REF_MIN)
639 scal_sel = ARRAY_SIZE(nau8822_mclk_scaler);
641 for (i = 0; i < scal_sel; i++) {
642 f2 = 256 * fs * 4 * nau8822_mclk_scaler[i] / 10;
643 if (f2 > NAU_PLL_FREQ_MIN && f2 < NAU_PLL_FREQ_MAX &&
650 if (ARRAY_SIZE(nau8822_mclk_scaler) == scal_sel)
652 pll_param->mclk_scaler = scal_sel;
655 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
656 * input; round up the 24+4bit.
658 pll_ratio = div_u64(f2 << 28, pll_in);
659 pll_param->pre_factor = 0;
660 if (((pll_ratio >> 28) & 0xF) < NAU_PLL_OPTOP_MIN) {
662 pll_param->pre_factor = 1;
664 pll_param->pll_int = (pll_ratio >> 28) & 0xF;
665 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
670 static int nau8822_config_clkdiv(struct snd_soc_dai *dai, int div, int rate)
672 struct snd_soc_component *component = dai->component;
673 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
674 struct nau8822_pll *pll = &nau8822->pll;
677 switch (nau8822->div_id) {
678 case NAU8822_CLK_MCLK:
679 /* Configure the master clock prescaler div to make system
680 * clock to approximate the internal master clock (IMCLK);
681 * and large or equal to IMCLK.
685 for (i = 1; i < ARRAY_SIZE(nau8822_mclk_scaler); i++) {
686 sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
691 dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
694 /* master clock from MCLK and disable PLL */
695 snd_soc_component_update_bits(component,
696 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
697 (div << NAU8822_MCLKSEL_SFT));
698 snd_soc_component_update_bits(component,
699 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
703 case NAU8822_CLK_PLL:
704 /* master clock from PLL and enable PLL */
705 if (pll->mclk_scaler != div) {
706 dev_err(component->dev,
707 "master clock prescaler not meet PLL parameters\n");
710 snd_soc_component_update_bits(component,
711 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
712 (div << NAU8822_MCLKSEL_SFT));
713 snd_soc_component_update_bits(component,
714 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK,
725 static int nau8822_set_pll(struct snd_soc_dai *dai, int pll_id, int source,
726 unsigned int freq_in, unsigned int freq_out)
728 struct snd_soc_component *component = dai->component;
729 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
730 struct nau8822_pll *pll_param = &nau8822->pll;
735 ret = nau8822_calc_pll(freq_in, fs, pll_param);
737 dev_err(component->dev, "Unsupported input clock %d\n",
742 dev_info(component->dev,
743 "pll_int=%x pll_frac=%x mclk_scaler=%x pre_factor=%x\n",
744 pll_param->pll_int, pll_param->pll_frac,
745 pll_param->mclk_scaler, pll_param->pre_factor);
747 snd_soc_component_update_bits(component,
748 NAU8822_REG_PLL_N, NAU8822_PLLMCLK_DIV2 | NAU8822_PLLN_MASK,
749 (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
751 snd_soc_component_write(component,
752 NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
754 snd_soc_component_write(component,
755 NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
757 snd_soc_component_write(component,
758 NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
759 snd_soc_component_update_bits(component,
760 NAU8822_REG_CLOCKING, NAU8822_MCLKSEL_MASK,
761 pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
762 snd_soc_component_update_bits(component,
763 NAU8822_REG_CLOCKING, NAU8822_CLKM_MASK, NAU8822_CLKM_PLL);
768 static int nau8822_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
770 struct snd_soc_component *component = dai->component;
771 u16 ctrl1_val = 0, ctrl2_val = 0;
773 dev_dbg(component->dev, "%s\n", __func__);
775 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
776 case SND_SOC_DAIFMT_CBM_CFM:
779 case SND_SOC_DAIFMT_CBS_CFS:
786 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
787 case SND_SOC_DAIFMT_I2S:
790 case SND_SOC_DAIFMT_RIGHT_J:
792 case SND_SOC_DAIFMT_LEFT_J:
795 case SND_SOC_DAIFMT_DSP_A:
802 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
803 case SND_SOC_DAIFMT_NB_NF:
805 case SND_SOC_DAIFMT_IB_IF:
808 case SND_SOC_DAIFMT_IB_NF:
811 case SND_SOC_DAIFMT_NB_IF:
818 snd_soc_component_update_bits(component,
819 NAU8822_REG_AUDIO_INTERFACE,
820 NAU8822_AIFMT_MASK | NAU8822_LRP_MASK | NAU8822_BCLKP_MASK,
822 snd_soc_component_update_bits(component,
823 NAU8822_REG_CLOCKING, NAU8822_CLKIOEN_MASK, ctrl2_val);
828 static int nau8822_hw_params(struct snd_pcm_substream *substream,
829 struct snd_pcm_hw_params *params,
830 struct snd_soc_dai *dai)
832 struct snd_soc_component *component = dai->component;
833 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
834 int val_len = 0, val_rate = 0;
836 switch (params_format(params)) {
837 case SNDRV_PCM_FORMAT_S16_LE:
839 case SNDRV_PCM_FORMAT_S20_3LE:
840 val_len |= NAU8822_WLEN_20;
842 case SNDRV_PCM_FORMAT_S24_LE:
843 val_len |= NAU8822_WLEN_24;
845 case SNDRV_PCM_FORMAT_S32_LE:
846 val_len |= NAU8822_WLEN_32;
852 switch (params_rate(params)) {
854 val_rate |= NAU8822_SMPLR_8K;
857 val_rate |= NAU8822_SMPLR_12K;
860 val_rate |= NAU8822_SMPLR_16K;
863 val_rate |= NAU8822_SMPLR_24K;
866 val_rate |= NAU8822_SMPLR_32K;
875 snd_soc_component_update_bits(component,
876 NAU8822_REG_AUDIO_INTERFACE, NAU8822_WLEN_MASK, val_len);
877 snd_soc_component_update_bits(component,
878 NAU8822_REG_ADDITIONAL_CONTROL, NAU8822_SMPLR_MASK, val_rate);
880 /* If the master clock is from MCLK, provide the runtime FS for driver
881 * to get the master clock prescaler configuration.
883 if (nau8822->div_id == NAU8822_CLK_MCLK)
884 nau8822_config_clkdiv(dai, 0, params_rate(params));
889 static int nau8822_mute(struct snd_soc_dai *dai, int mute)
891 struct snd_soc_component *component = dai->component;
893 dev_dbg(component->dev, "%s: %d\n", __func__, mute);
896 snd_soc_component_update_bits(component,
897 NAU8822_REG_DAC_CONTROL, 0x40, 0x40);
899 snd_soc_component_update_bits(component,
900 NAU8822_REG_DAC_CONTROL, 0x40, 0);
905 static int nau8822_set_bias_level(struct snd_soc_component *component,
906 enum snd_soc_bias_level level)
909 case SND_SOC_BIAS_ON:
910 case SND_SOC_BIAS_PREPARE:
911 snd_soc_component_update_bits(component,
912 NAU8822_REG_POWER_MANAGEMENT_1,
913 NAU8822_REFIMP_MASK, NAU8822_REFIMP_80K);
916 case SND_SOC_BIAS_STANDBY:
917 snd_soc_component_update_bits(component,
918 NAU8822_REG_POWER_MANAGEMENT_1,
919 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN,
920 NAU8822_IOBUF_EN | NAU8822_ABIAS_EN);
922 if (snd_soc_component_get_bias_level(component) ==
924 snd_soc_component_update_bits(component,
925 NAU8822_REG_POWER_MANAGEMENT_1,
926 NAU8822_REFIMP_MASK, NAU8822_REFIMP_3K);
929 snd_soc_component_update_bits(component,
930 NAU8822_REG_POWER_MANAGEMENT_1,
931 NAU8822_REFIMP_MASK, NAU8822_REFIMP_300K);
934 case SND_SOC_BIAS_OFF:
935 snd_soc_component_write(component,
936 NAU8822_REG_POWER_MANAGEMENT_1, 0);
937 snd_soc_component_write(component,
938 NAU8822_REG_POWER_MANAGEMENT_2, 0);
939 snd_soc_component_write(component,
940 NAU8822_REG_POWER_MANAGEMENT_3, 0);
944 dev_dbg(component->dev, "%s: %d\n", __func__, level);
949 #define NAU8822_RATES (SNDRV_PCM_RATE_8000_48000)
951 #define NAU8822_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
952 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
954 static const struct snd_soc_dai_ops nau8822_dai_ops = {
955 .hw_params = nau8822_hw_params,
956 .digital_mute = nau8822_mute,
957 .set_fmt = nau8822_set_dai_fmt,
958 .set_sysclk = nau8822_set_dai_sysclk,
959 .set_pll = nau8822_set_pll,
962 static struct snd_soc_dai_driver nau8822_dai = {
963 .name = "nau8822-hifi",
965 .stream_name = "Playback",
968 .rates = NAU8822_RATES,
969 .formats = NAU8822_FORMATS,
972 .stream_name = "Capture",
975 .rates = NAU8822_RATES,
976 .formats = NAU8822_FORMATS,
978 .ops = &nau8822_dai_ops,
979 .symmetric_rates = 1,
982 static int nau8822_suspend(struct snd_soc_component *component)
984 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
986 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
988 regcache_mark_dirty(nau8822->regmap);
993 static int nau8822_resume(struct snd_soc_component *component)
995 struct nau8822 *nau8822 = snd_soc_component_get_drvdata(component);
997 regcache_sync(nau8822->regmap);
999 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1005 * These registers contain an "update" bit - bit 8. This means, for example,
1006 * that one can write new DAC digital volume for both channels, but only when
1007 * the update bit is set, will also the volume be updated - simultaneously for
1010 static const int update_reg[] = {
1011 NAU8822_REG_LEFT_DAC_DIGITAL_VOLUME,
1012 NAU8822_REG_RIGHT_DAC_DIGITAL_VOLUME,
1013 NAU8822_REG_LEFT_ADC_DIGITAL_VOLUME,
1014 NAU8822_REG_RIGHT_ADC_DIGITAL_VOLUME,
1015 NAU8822_REG_LEFT_INP_PGA_CONTROL,
1016 NAU8822_REG_RIGHT_INP_PGA_CONTROL,
1017 NAU8822_REG_LHP_VOLUME,
1018 NAU8822_REG_RHP_VOLUME,
1019 NAU8822_REG_LSPKOUT_VOLUME,
1020 NAU8822_REG_RSPKOUT_VOLUME,
1023 static int nau8822_probe(struct snd_soc_component *component)
1028 * Set the update bit in all registers, that have one. This way all
1029 * writes to those registers will also cause the update bit to be
1032 for (i = 0; i < ARRAY_SIZE(update_reg); i++)
1033 snd_soc_component_update_bits(component,
1034 update_reg[i], 0x100, 0x100);
1039 static const struct snd_soc_component_driver soc_component_dev_nau8822 = {
1040 .probe = nau8822_probe,
1041 .suspend = nau8822_suspend,
1042 .resume = nau8822_resume,
1043 .set_bias_level = nau8822_set_bias_level,
1044 .controls = nau8822_snd_controls,
1045 .num_controls = ARRAY_SIZE(nau8822_snd_controls),
1046 .dapm_widgets = nau8822_dapm_widgets,
1047 .num_dapm_widgets = ARRAY_SIZE(nau8822_dapm_widgets),
1048 .dapm_routes = nau8822_dapm_routes,
1049 .num_dapm_routes = ARRAY_SIZE(nau8822_dapm_routes),
1051 .use_pmdown_time = 1,
1053 .non_legacy_dai_naming = 1,
1056 static const struct regmap_config nau8822_regmap_config = {
1060 .max_register = NAU8822_REG_MAX_REGISTER,
1061 .volatile_reg = nau8822_volatile,
1063 .readable_reg = nau8822_readable_reg,
1064 .writeable_reg = nau8822_writeable_reg,
1066 .cache_type = REGCACHE_RBTREE,
1067 .reg_defaults = nau8822_reg_defaults,
1068 .num_reg_defaults = ARRAY_SIZE(nau8822_reg_defaults),
1071 static int nau8822_i2c_probe(struct i2c_client *i2c,
1072 const struct i2c_device_id *id)
1074 struct device *dev = &i2c->dev;
1075 struct nau8822 *nau8822 = dev_get_platdata(dev);
1079 nau8822 = devm_kzalloc(dev, sizeof(*nau8822), GFP_KERNEL);
1080 if (nau8822 == NULL)
1083 i2c_set_clientdata(i2c, nau8822);
1085 nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
1086 if (IS_ERR(nau8822->regmap)) {
1087 ret = PTR_ERR(nau8822->regmap);
1088 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1093 /* Reset the codec */
1094 ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
1096 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1100 ret = devm_snd_soc_register_component(dev, &soc_component_dev_nau8822,
1103 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);
1110 static const struct i2c_device_id nau8822_i2c_id[] = {
1114 MODULE_DEVICE_TABLE(i2c, nau8822_i2c_id);
1117 static const struct of_device_id nau8822_of_match[] = {
1118 { .compatible = "nuvoton,nau8822", },
1121 MODULE_DEVICE_TABLE(of, nau8822_of_match);
1124 static struct i2c_driver nau8822_i2c_driver = {
1127 .of_match_table = of_match_ptr(nau8822_of_match),
1129 .probe = nau8822_i2c_probe,
1130 .id_table = nau8822_i2c_id,
1132 module_i2c_driver(nau8822_i2c_driver);
1134 MODULE_DESCRIPTION("ASoC NAU8822 codec driver");
1135 MODULE_AUTHOR("David Lin <ctlin0@nuvoton.com>");
1136 MODULE_LICENSE("GPL v2");