1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver
5 // Copyright 2021 Nuvoton Technology Corp.
6 // Author: John Hsu <kchsu0@nuvoton.com>
7 // Co-author: Seven Lee <wtli@nuvoton.com>
10 #include <linux/acpi.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/i2c.h>
16 #include <linux/module.h>
17 #include <linux/math64.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/initval.h>
22 #include <sound/jack.h>
23 #include <sound/pcm.h>
24 #include <sound/pcm_params.h>
25 #include <sound/soc.h>
26 #include <sound/tlv.h>
29 #define NAU8821_JD_ACTIVE_HIGH BIT(0)
31 static int nau8821_quirk;
32 static int quirk_override = -1;
33 module_param_named(quirk, quirk_override, uint, 0444);
34 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
36 #define NAU_FREF_MAX 13500000
37 #define NAU_FVCO_MAX 100000000
38 #define NAU_FVCO_MIN 90000000
40 #define NAU8821_BUTTON SND_JACK_BTN_0
42 /* the maximum frequency of CLK_ADC and CLK_DAC */
43 #define CLK_DA_AD_MAX 6144000
45 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
46 int clk_id, unsigned int freq);
47 static bool nau8821_is_jack_inserted(struct regmap *regmap);
57 struct nau8821_fll_attr {
62 /* scaling for mclk from sysclk_src output */
63 static const struct nau8821_fll_attr mclk_src_scaling[] = {
79 /* ratio for input clk freq */
80 static const struct nau8821_fll_attr fll_ratio[] = {
90 static const struct nau8821_fll_attr fll_pre_scalar[] = {
97 /* over sampling rate */
98 struct nau8821_osr_attr {
100 unsigned int clk_src;
103 static const struct nau8821_osr_attr osr_dac_sel[] = {
104 { 64, 2 }, /* OSR 64, SRC 1/4 */
105 { 256, 0 }, /* OSR 256, SRC 1 */
106 { 128, 1 }, /* OSR 128, SRC 1/2 */
108 { 32, 3 }, /* OSR 32, SRC 1/8 */
111 static const struct nau8821_osr_attr osr_adc_sel[] = {
112 { 32, 3 }, /* OSR 32, SRC 1/8 */
113 { 64, 2 }, /* OSR 64, SRC 1/4 */
114 { 128, 1 }, /* OSR 128, SRC 1/2 */
115 { 256, 0 }, /* OSR 256, SRC 1 */
118 struct nau8821_dmic_speed {
123 static const struct nau8821_dmic_speed dmic_speed_sel[] = {
124 { 0, 0x0 }, /*SPEED 1, SRC 1 */
125 { 1, 0x1 }, /*SPEED 2, SRC 1/2 */
126 { 2, 0x2 }, /*SPEED 4, SRC 1/4 */
127 { 3, 0x3 }, /*SPEED 8, SRC 1/8 */
130 static const struct reg_default nau8821_reg_defaults[] = {
131 { NAU8821_R01_ENA_CTRL, 0x00ff },
132 { NAU8821_R03_CLK_DIVIDER, 0x0050 },
133 { NAU8821_R04_FLL1, 0x0 },
134 { NAU8821_R05_FLL2, 0x00bc },
135 { NAU8821_R06_FLL3, 0x0008 },
136 { NAU8821_R07_FLL4, 0x0010 },
137 { NAU8821_R08_FLL5, 0x4000 },
138 { NAU8821_R09_FLL6, 0x6900 },
139 { NAU8821_R0A_FLL7, 0x0031 },
140 { NAU8821_R0B_FLL8, 0x26e9 },
141 { NAU8821_R0D_JACK_DET_CTRL, 0x0 },
142 { NAU8821_R0F_INTERRUPT_MASK, 0x0 },
143 { NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff },
144 { NAU8821_R13_DMIC_CTRL, 0x0 },
145 { NAU8821_R1A_GPIO12_CTRL, 0x0 },
146 { NAU8821_R1B_TDM_CTRL, 0x0 },
147 { NAU8821_R1C_I2S_PCM_CTRL1, 0x000a },
148 { NAU8821_R1D_I2S_PCM_CTRL2, 0x8010 },
149 { NAU8821_R1E_LEFT_TIME_SLOT, 0x0 },
150 { NAU8821_R1F_RIGHT_TIME_SLOT, 0x0 },
151 { NAU8821_R21_BIQ0_COF1, 0x0 },
152 { NAU8821_R22_BIQ0_COF2, 0x0 },
153 { NAU8821_R23_BIQ0_COF3, 0x0 },
154 { NAU8821_R24_BIQ0_COF4, 0x0 },
155 { NAU8821_R25_BIQ0_COF5, 0x0 },
156 { NAU8821_R26_BIQ0_COF6, 0x0 },
157 { NAU8821_R27_BIQ0_COF7, 0x0 },
158 { NAU8821_R28_BIQ0_COF8, 0x0 },
159 { NAU8821_R29_BIQ0_COF9, 0x0 },
160 { NAU8821_R2A_BIQ0_COF10, 0x0 },
161 { NAU8821_R2B_ADC_RATE, 0x0002 },
162 { NAU8821_R2C_DAC_CTRL1, 0x0082 },
163 { NAU8821_R2D_DAC_CTRL2, 0x0 },
164 { NAU8821_R2F_DAC_DGAIN_CTRL, 0x0 },
165 { NAU8821_R30_ADC_DGAIN_CTRL, 0x0 },
166 { NAU8821_R31_MUTE_CTRL, 0x0 },
167 { NAU8821_R32_HSVOL_CTRL, 0x0 },
168 { NAU8821_R34_DACR_CTRL, 0xcfcf },
169 { NAU8821_R35_ADC_DGAIN_CTRL1, 0xcfcf },
170 { NAU8821_R36_ADC_DRC_KNEE_IP12, 0x1486 },
171 { NAU8821_R37_ADC_DRC_KNEE_IP34, 0x0f12 },
172 { NAU8821_R38_ADC_DRC_SLOPES, 0x25ff },
173 { NAU8821_R39_ADC_DRC_ATKDCY, 0x3457 },
174 { NAU8821_R3A_DAC_DRC_KNEE_IP12, 0x1486 },
175 { NAU8821_R3B_DAC_DRC_KNEE_IP34, 0x0f12 },
176 { NAU8821_R3C_DAC_DRC_SLOPES, 0x25f9 },
177 { NAU8821_R3D_DAC_DRC_ATKDCY, 0x3457 },
178 { NAU8821_R41_BIQ1_COF1, 0x0 },
179 { NAU8821_R42_BIQ1_COF2, 0x0 },
180 { NAU8821_R43_BIQ1_COF3, 0x0 },
181 { NAU8821_R44_BIQ1_COF4, 0x0 },
182 { NAU8821_R45_BIQ1_COF5, 0x0 },
183 { NAU8821_R46_BIQ1_COF6, 0x0 },
184 { NAU8821_R47_BIQ1_COF7, 0x0 },
185 { NAU8821_R48_BIQ1_COF8, 0x0 },
186 { NAU8821_R49_BIQ1_COF9, 0x0 },
187 { NAU8821_R4A_BIQ1_COF10, 0x0 },
188 { NAU8821_R4B_CLASSG_CTRL, 0x0 },
189 { NAU8821_R4C_IMM_MODE_CTRL, 0x0 },
190 { NAU8821_R4D_IMM_RMS_L, 0x0 },
191 { NAU8821_R53_OTPDOUT_1, 0xaad8 },
192 { NAU8821_R54_OTPDOUT_2, 0x0002 },
193 { NAU8821_R55_MISC_CTRL, 0x0 },
194 { NAU8821_R66_BIAS_ADJ, 0x0 },
195 { NAU8821_R68_TRIM_SETTINGS, 0x0 },
196 { NAU8821_R69_ANALOG_CONTROL_1, 0x0 },
197 { NAU8821_R6A_ANALOG_CONTROL_2, 0x0 },
198 { NAU8821_R6B_PGA_MUTE, 0x0 },
199 { NAU8821_R71_ANALOG_ADC_1, 0x0011 },
200 { NAU8821_R72_ANALOG_ADC_2, 0x0020 },
201 { NAU8821_R73_RDAC, 0x0008 },
202 { NAU8821_R74_MIC_BIAS, 0x0006 },
203 { NAU8821_R76_BOOST, 0x0 },
204 { NAU8821_R77_FEPGA, 0x0 },
205 { NAU8821_R7E_PGA_GAIN, 0x0 },
206 { NAU8821_R7F_POWER_UP_CONTROL, 0x0 },
207 { NAU8821_R80_CHARGE_PUMP, 0x0 },
210 static bool nau8821_readable_reg(struct device *dev, unsigned int reg)
213 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
214 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
215 case NAU8821_R0D_JACK_DET_CTRL:
216 case NAU8821_R0F_INTERRUPT_MASK ... NAU8821_R13_DMIC_CTRL:
217 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
218 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
219 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
220 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
221 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4F_FUSE_CTRL3:
222 case NAU8821_R51_FUSE_CTRL1:
223 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R55_MISC_CTRL:
224 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
225 case NAU8821_R66_BIAS_ADJ:
226 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
227 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
228 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
229 case NAU8821_R7E_PGA_GAIN ... NAU8821_R82_GENERAL_STATUS:
236 static bool nau8821_writeable_reg(struct device *dev, unsigned int reg)
239 case NAU8821_R00_RESET ... NAU8821_R01_ENA_CTRL:
240 case NAU8821_R03_CLK_DIVIDER ... NAU8821_R0B_FLL8:
241 case NAU8821_R0D_JACK_DET_CTRL:
242 case NAU8821_R0F_INTERRUPT_MASK:
243 case NAU8821_R11_INT_CLR_KEY_STATUS ... NAU8821_R13_DMIC_CTRL:
244 case NAU8821_R1A_GPIO12_CTRL ... NAU8821_R1F_RIGHT_TIME_SLOT:
245 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2D_DAC_CTRL2:
246 case NAU8821_R2F_DAC_DGAIN_CTRL ... NAU8821_R32_HSVOL_CTRL:
247 case NAU8821_R34_DACR_CTRL ... NAU8821_R3D_DAC_DRC_ATKDCY:
248 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4C_IMM_MODE_CTRL:
249 case NAU8821_R4E_FUSE_CTRL2 ... NAU8821_R4F_FUSE_CTRL3:
250 case NAU8821_R51_FUSE_CTRL1:
251 case NAU8821_R55_MISC_CTRL:
252 case NAU8821_R5A_SOFTWARE_RST:
253 case NAU8821_R66_BIAS_ADJ:
254 case NAU8821_R68_TRIM_SETTINGS ... NAU8821_R6B_PGA_MUTE:
255 case NAU8821_R71_ANALOG_ADC_1 ... NAU8821_R74_MIC_BIAS:
256 case NAU8821_R76_BOOST ... NAU8821_R77_FEPGA:
257 case NAU8821_R7E_PGA_GAIN ... NAU8821_R80_CHARGE_PUMP:
264 static bool nau8821_volatile_reg(struct device *dev, unsigned int reg)
267 case NAU8821_R00_RESET:
268 case NAU8821_R10_IRQ_STATUS ... NAU8821_R11_INT_CLR_KEY_STATUS:
269 case NAU8821_R21_BIQ0_COF1 ... NAU8821_R2A_BIQ0_COF10:
270 case NAU8821_R41_BIQ1_COF1 ... NAU8821_R4A_BIQ1_COF10:
271 case NAU8821_R4D_IMM_RMS_L:
272 case NAU8821_R53_OTPDOUT_1 ... NAU8821_R54_OTPDOUT_2:
273 case NAU8821_R58_I2C_DEVICE_ID ... NAU8821_R5A_SOFTWARE_RST:
274 case NAU8821_R81_CHARGE_PUMP_INPUT_READ ... NAU8821_R82_GENERAL_STATUS:
281 static int nau8821_biq_coeff_get(struct snd_kcontrol *kcontrol,
282 struct snd_ctl_elem_value *ucontrol)
284 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
285 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
287 if (!component->regmap)
290 regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
291 ucontrol->value.bytes.data, params->max);
296 static int nau8821_biq_coeff_put(struct snd_kcontrol *kcontrol,
297 struct snd_ctl_elem_value *ucontrol)
299 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
300 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
303 if (!component->regmap)
306 data = kmemdup(ucontrol->value.bytes.data,
307 params->max, GFP_KERNEL | GFP_DMA);
311 regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
319 static const char * const nau8821_adc_decimation[] = {
320 "32", "64", "128", "256" };
322 static const struct soc_enum nau8821_adc_decimation_enum =
323 SOC_ENUM_SINGLE(NAU8821_R2B_ADC_RATE, NAU8821_ADC_SYNC_DOWN_SFT,
324 ARRAY_SIZE(nau8821_adc_decimation), nau8821_adc_decimation);
326 static const char * const nau8821_dac_oversampl[] = {
327 "64", "256", "128", "", "32" };
329 static const struct soc_enum nau8821_dac_oversampl_enum =
330 SOC_ENUM_SINGLE(NAU8821_R2C_DAC_CTRL1, NAU8821_DAC_OVERSAMPLE_SFT,
331 ARRAY_SIZE(nau8821_dac_oversampl), nau8821_dac_oversampl);
333 static const char * const nau8821_adc_drc_noise_gate[] = {
334 "1:1", "2:1", "4:1", "8:1" };
336 static const struct soc_enum nau8821_adc_drc_noise_gate_enum =
337 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_NG_SLP_ADC_SFT,
338 ARRAY_SIZE(nau8821_adc_drc_noise_gate),
339 nau8821_adc_drc_noise_gate);
341 static const char * const nau8821_adc_drc_expansion_slope[] = {
342 "1:1", "2:1", "4:1" };
344 static const struct soc_enum nau8821_adc_drc_expansion_slope_enum =
345 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES, NAU8821_DRC_EXP_SLP_ADC_SFT,
346 ARRAY_SIZE(nau8821_adc_drc_expansion_slope),
347 nau8821_adc_drc_expansion_slope);
349 static const char * const nau8821_adc_drc_lower_region[] = {
350 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
352 static const struct soc_enum nau8821_adc_drc_lower_region_enum =
353 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
354 NAU8821_DRC_CMP2_SLP_ADC_SFT,
355 ARRAY_SIZE(nau8821_adc_drc_lower_region),
356 nau8821_adc_drc_lower_region);
358 static const char * const nau8821_higher_region[] = {
359 "0", "1:2", "1:4", "1:8", "1:16", "", "", "1:1" };
361 static const struct soc_enum nau8821_higher_region_enum =
362 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
363 NAU8821_DRC_CMP1_SLP_ADC_SFT,
364 ARRAY_SIZE(nau8821_higher_region),
365 nau8821_higher_region);
367 static const char * const nau8821_limiter_slope[] = {
368 "0", "1:2", "1:4", "1:8", "1:16", "1:32", "1:64", "1:1" };
370 static const struct soc_enum nau8821_limiter_slope_enum =
371 SOC_ENUM_SINGLE(NAU8821_R38_ADC_DRC_SLOPES,
372 NAU8821_DRC_LMT_SLP_ADC_SFT, ARRAY_SIZE(nau8821_limiter_slope),
373 nau8821_limiter_slope);
375 static const char * const nau8821_detection_attack_time[] = {
376 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
379 static const struct soc_enum nau8821_detection_attack_time_enum =
380 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
381 NAU8821_DRC_PK_COEF1_ADC_SFT,
382 ARRAY_SIZE(nau8821_detection_attack_time),
383 nau8821_detection_attack_time);
385 static const char * const nau8821_detection_release_time[] = {
386 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
387 "8191Ts", "", "16383Ts" };
389 static const struct soc_enum nau8821_detection_release_time_enum =
390 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY,
391 NAU8821_DRC_PK_COEF2_ADC_SFT,
392 ARRAY_SIZE(nau8821_detection_release_time),
393 nau8821_detection_release_time);
395 static const char * const nau8821_attack_time[] = {
396 "Ts", "3Ts", "7Ts", "15Ts", "31Ts", "63Ts", "127Ts", "255Ts",
397 "511Ts", "1023Ts", "2047Ts", "4095Ts", "8191Ts" };
399 static const struct soc_enum nau8821_attack_time_enum =
400 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_ATK_ADC_SFT,
401 ARRAY_SIZE(nau8821_attack_time), nau8821_attack_time);
403 static const char * const nau8821_decay_time[] = {
404 "63Ts", "127Ts", "255Ts", "511Ts", "1023Ts", "2047Ts", "4095Ts",
405 "8191Ts", "16383Ts", "32757Ts", "65535Ts" };
407 static const struct soc_enum nau8821_decay_time_enum =
408 SOC_ENUM_SINGLE(NAU8821_R39_ADC_DRC_ATKDCY, NAU8821_DRC_DCY_ADC_SFT,
409 ARRAY_SIZE(nau8821_decay_time), nau8821_decay_time);
411 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
412 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
413 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
414 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
415 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
416 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
417 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500);
418 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800);
420 static const struct snd_kcontrol_new nau8821_controls[] = {
421 SOC_DOUBLE_TLV("Mic Volume", NAU8821_R35_ADC_DGAIN_CTRL1,
422 NAU8821_ADCL_CH_VOL_SFT, NAU8821_ADCR_CH_VOL_SFT,
423 0xff, 0, adc_vol_tlv),
424 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8821_R30_ADC_DGAIN_CTRL,
425 12, 8, 0x0f, 0, sidetone_vol_tlv),
426 SOC_DOUBLE_TLV("Headphone Volume", NAU8821_R32_HSVOL_CTRL,
427 NAU8821_HPL_VOL_SFT, NAU8821_HPR_VOL_SFT, 0x3, 1, hp_vol_tlv),
428 SOC_DOUBLE_TLV("Digital Playback Volume", NAU8821_R34_DACR_CTRL,
429 NAU8821_DACL_CH_VOL_SFT, NAU8821_DACR_CH_VOL_SFT,
430 0xcf, 0, playback_vol_tlv),
431 SOC_DOUBLE_TLV("Frontend PGA Volume", NAU8821_R7E_PGA_GAIN,
432 NAU8821_PGA_GAIN_L_SFT, NAU8821_PGA_GAIN_R_SFT,
433 37, 0, fepga_gain_tlv),
434 SOC_DOUBLE_TLV("Headphone Crosstalk Volume",
435 NAU8821_R2F_DAC_DGAIN_CTRL,
436 0, 8, 0xff, 0, crosstalk_vol_tlv),
437 SOC_SINGLE_TLV("ADC DRC KNEE4", NAU8821_R37_ADC_DRC_KNEE_IP34,
438 NAU8821_DRC_KNEE4_IP_ADC_SFT, 0x3f, 1, drc_knee4_tlv),
439 SOC_SINGLE_TLV("ADC DRC KNEE3", NAU8821_R37_ADC_DRC_KNEE_IP34,
440 NAU8821_DRC_KNEE3_IP_ADC_SFT, 0x3f, 1, drc_knee3_tlv),
442 SOC_ENUM("ADC DRC Noise Gate", nau8821_adc_drc_noise_gate_enum),
443 SOC_ENUM("ADC DRC Expansion Slope", nau8821_adc_drc_expansion_slope_enum),
444 SOC_ENUM("ADC DRC Lower Region", nau8821_adc_drc_lower_region_enum),
445 SOC_ENUM("ADC DRC Higher Region", nau8821_higher_region_enum),
446 SOC_ENUM("ADC DRC Limiter Slope", nau8821_limiter_slope_enum),
447 SOC_ENUM("ADC DRC Peak Detection Attack Time", nau8821_detection_attack_time_enum),
448 SOC_ENUM("ADC DRC Peak Detection Release Time", nau8821_detection_release_time_enum),
449 SOC_ENUM("ADC DRC Attack Time", nau8821_attack_time_enum),
450 SOC_ENUM("ADC DRC Decay Time", nau8821_decay_time_enum),
451 SOC_SINGLE("DRC Enable Switch", NAU8821_R36_ADC_DRC_KNEE_IP12,
452 NAU8821_DRC_ENA_ADC_SFT, 1, 0),
454 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
455 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
456 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
457 nau8821_biq_coeff_get, nau8821_biq_coeff_put),
458 SOC_SINGLE("ADC Phase Switch", NAU8821_R1B_TDM_CTRL,
459 NAU8821_ADCPHS_SFT, 1, 0),
462 static const struct snd_kcontrol_new nau8821_dmic_mode_switch =
463 SOC_DAPM_SINGLE("Switch", NAU8821_R13_DMIC_CTRL,
464 NAU8821_DMIC_EN_SFT, 1, 0);
466 static int dmic_clock_control(struct snd_soc_dapm_widget *w,
467 struct snd_kcontrol *k, int event)
469 struct snd_soc_component *component =
470 snd_soc_dapm_to_component(w->dapm);
471 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
472 int i, speed_selection = -1, clk_adc_src, clk_adc;
473 unsigned int clk_divider_r03;
475 /* The DMIC clock is gotten from adc clock divided by
476 * CLK_DMIC_SRC (1, 2, 4, 8). The clock has to be equal or
477 * less than nau8821->dmic_clk_threshold.
479 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
481 clk_adc_src = (clk_divider_r03 & NAU8821_CLK_ADC_SRC_MASK)
482 >> NAU8821_CLK_ADC_SRC_SFT;
483 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
485 for (i = 0 ; i < 4 ; i++)
486 if ((clk_adc >> dmic_speed_sel[i].param) <=
487 nau8821->dmic_clk_threshold) {
488 speed_selection = dmic_speed_sel[i].val;
494 dev_dbg(nau8821->dev,
495 "clk_adc=%d, dmic_clk_threshold = %d, param=%d, val = %d\n",
496 clk_adc, nau8821->dmic_clk_threshold,
497 dmic_speed_sel[i].param, dmic_speed_sel[i].val);
498 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
499 NAU8821_DMIC_SRC_MASK,
500 (speed_selection << NAU8821_DMIC_SRC_SFT));
505 static int nau8821_left_adc_event(struct snd_soc_dapm_widget *w,
506 struct snd_kcontrol *kcontrol, int event)
508 struct snd_soc_component *component =
509 snd_soc_dapm_to_component(w->dapm);
510 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
513 case SND_SOC_DAPM_POST_PMU:
515 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
516 NAU8821_EN_ADCL, NAU8821_EN_ADCL);
518 case SND_SOC_DAPM_POST_PMD:
519 regmap_update_bits(nau8821->regmap,
520 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCL, 0);
529 static int nau8821_right_adc_event(struct snd_soc_dapm_widget *w,
530 struct snd_kcontrol *kcontrol, int event)
532 struct snd_soc_component *component =
533 snd_soc_dapm_to_component(w->dapm);
534 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
537 case SND_SOC_DAPM_POST_PMU:
539 regmap_update_bits(nau8821->regmap, NAU8821_R01_ENA_CTRL,
540 NAU8821_EN_ADCR, NAU8821_EN_ADCR);
542 case SND_SOC_DAPM_POST_PMD:
543 regmap_update_bits(nau8821->regmap,
544 NAU8821_R01_ENA_CTRL, NAU8821_EN_ADCR, 0);
553 static int nau8821_pump_event(struct snd_soc_dapm_widget *w,
554 struct snd_kcontrol *kcontrol, int event)
556 struct snd_soc_component *component =
557 snd_soc_dapm_to_component(w->dapm);
558 struct nau8821 *nau8821 =
559 snd_soc_component_get_drvdata(component);
562 case SND_SOC_DAPM_POST_PMU:
563 /* Prevent startup click by letting charge pump to ramp up */
565 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
566 NAU8821_JAMNODCLOW, NAU8821_JAMNODCLOW);
568 case SND_SOC_DAPM_PRE_PMD:
569 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
570 NAU8821_JAMNODCLOW, 0);
579 static int nau8821_output_dac_event(struct snd_soc_dapm_widget *w,
580 struct snd_kcontrol *kcontrol, int event)
582 struct snd_soc_component *component =
583 snd_soc_dapm_to_component(w->dapm);
584 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
587 case SND_SOC_DAPM_PRE_PMU:
588 /* Disables the TESTDAC to let DAC signal pass through. */
589 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
590 NAU8821_BIAS_TESTDAC_EN, 0);
592 case SND_SOC_DAPM_POST_PMD:
593 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
594 NAU8821_BIAS_TESTDAC_EN, NAU8821_BIAS_TESTDAC_EN);
603 static int system_clock_control(struct snd_soc_dapm_widget *w,
604 struct snd_kcontrol *k, int event)
606 struct snd_soc_component *component =
607 snd_soc_dapm_to_component(w->dapm);
608 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
610 if (SND_SOC_DAPM_EVENT_OFF(event)) {
611 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
612 /* Set clock source to disable or internal clock before the
613 * playback or capture end. Codec needs clock for Jack
614 * detection and button press if jack inserted; otherwise,
615 * the clock should be closed.
617 if (nau8821_is_jack_inserted(nau8821->regmap)) {
618 nau8821_configure_sysclk(nau8821,
619 NAU8821_CLK_INTERNAL, 0);
621 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
627 static const struct snd_soc_dapm_widget nau8821_dapm_widgets[] = {
628 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
629 system_clock_control, SND_SOC_DAPM_POST_PMD),
630 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8821_R74_MIC_BIAS,
631 NAU8821_MICBIAS_POWERUP_SFT, 0, NULL, 0),
632 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
633 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
634 SND_SOC_DAPM_ADC("ADCL Power", NULL, NAU8821_R72_ANALOG_ADC_2,
635 NAU8821_POWERUP_ADCL_SFT, 0),
636 SND_SOC_DAPM_ADC("ADCR Power", NULL, NAU8821_R72_ANALOG_ADC_2,
637 NAU8821_POWERUP_ADCR_SFT, 0),
638 SND_SOC_DAPM_PGA_S("Frontend PGA L", 1, NAU8821_R7F_POWER_UP_CONTROL,
639 NAU8821_PUP_PGA_L_SFT, 0, NULL, 0),
640 SND_SOC_DAPM_PGA_S("Frontend PGA R", 1, NAU8821_R7F_POWER_UP_CONTROL,
641 NAU8821_PUP_PGA_R_SFT, 0, NULL, 0),
642 SND_SOC_DAPM_PGA_S("ADCL Digital path", 0, NAU8821_R01_ENA_CTRL,
643 NAU8821_EN_ADCL_SFT, 0, nau8821_left_adc_event,
644 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
645 SND_SOC_DAPM_PGA_S("ADCR Digital path", 0, NAU8821_R01_ENA_CTRL,
646 NAU8821_EN_ADCR_SFT, 0, nau8821_right_adc_event,
647 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
648 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
649 0, 0, &nau8821_dmic_mode_switch),
650 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8821_R1D_I2S_PCM_CTRL2,
651 NAU8821_I2S_TRISTATE_SFT, 1),
652 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
654 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8821_R73_RDAC,
655 NAU8821_DACL_EN_SFT, 0, NULL, 0),
656 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8821_R73_RDAC,
657 NAU8821_DACR_EN_SFT, 0, NULL, 0),
658 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8821_R73_RDAC,
659 NAU8821_DACL_CLK_EN_SFT, 0, NULL, 0),
660 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8821_R73_RDAC,
661 NAU8821_DACR_CLK_EN_SFT, 0, NULL, 0),
662 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8821_R01_ENA_CTRL,
663 NAU8821_EN_DACR_SFT, 0),
664 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8821_R01_ENA_CTRL,
665 NAU8821_EN_DACL_SFT, 0),
666 SND_SOC_DAPM_PGA_S("HP amp L", 0, NAU8821_R4B_CLASSG_CTRL,
667 NAU8821_CLASSG_LDAC_EN_SFT, 0, NULL, 0),
668 SND_SOC_DAPM_PGA_S("HP amp R", 0, NAU8821_R4B_CLASSG_CTRL,
669 NAU8821_CLASSG_RDAC_EN_SFT, 0, NULL, 0),
670 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8821_R80_CHARGE_PUMP,
671 NAU8821_CHANRGE_PUMP_EN_SFT, 0, nau8821_pump_event,
672 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
673 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
674 NAU8821_R7F_POWER_UP_CONTROL,
675 NAU8821_PUP_INTEG_R_SFT, 0, NULL, 0),
676 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
677 NAU8821_R7F_POWER_UP_CONTROL,
678 NAU8821_PUP_INTEG_L_SFT, 0, NULL, 0),
679 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
680 NAU8821_R7F_POWER_UP_CONTROL,
681 NAU8821_PUP_DRV_INSTG_R_SFT, 0, NULL, 0),
682 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
683 NAU8821_R7F_POWER_UP_CONTROL,
684 NAU8821_PUP_DRV_INSTG_L_SFT, 0, NULL, 0),
685 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
686 NAU8821_R7F_POWER_UP_CONTROL,
687 NAU8821_PUP_MAIN_DRV_R_SFT, 0, NULL, 0),
688 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
689 NAU8821_R7F_POWER_UP_CONTROL,
690 NAU8821_PUP_MAIN_DRV_L_SFT, 0, NULL, 0),
691 SND_SOC_DAPM_PGA_S("Output DACL", 7,
692 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACL_SFT,
693 0, nau8821_output_dac_event,
694 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
695 SND_SOC_DAPM_PGA_S("Output DACR", 7,
696 NAU8821_R80_CHARGE_PUMP, NAU8821_POWER_DOWN_DACR_SFT,
697 0, nau8821_output_dac_event,
698 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
700 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
701 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
702 NAU8821_R0D_JACK_DET_CTRL,
703 NAU8821_SPKR_DWN1L_SFT, 0, NULL, 0),
704 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
705 NAU8821_R0D_JACK_DET_CTRL,
706 NAU8821_SPKR_DWN1R_SFT, 0, NULL, 0),
708 /* High current HPOL/R boost driver */
709 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
710 NAU8821_R76_BOOST, NAU8821_HP_BOOST_DIS_SFT, 1, NULL, 0),
711 SND_SOC_DAPM_PGA("Class G", NAU8821_R4B_CLASSG_CTRL,
712 NAU8821_CLASSG_EN_SFT, 0, NULL, 0),
714 SND_SOC_DAPM_INPUT("MICL"),
715 SND_SOC_DAPM_INPUT("MICR"),
716 SND_SOC_DAPM_INPUT("DMIC"),
717 SND_SOC_DAPM_OUTPUT("HPOL"),
718 SND_SOC_DAPM_OUTPUT("HPOR"),
721 static const struct snd_soc_dapm_route nau8821_dapm_routes[] = {
722 {"DMIC Enable", "Switch", "DMIC"},
723 {"DMIC Enable", NULL, "DMIC Clock"},
725 {"Frontend PGA L", NULL, "MICL"},
726 {"Frontend PGA R", NULL, "MICR"},
727 {"Frontend PGA L", NULL, "MICBIAS"},
728 {"Frontend PGA R", NULL, "MICBIAS"},
730 {"ADCL Power", NULL, "Frontend PGA L"},
731 {"ADCR Power", NULL, "Frontend PGA R"},
733 {"ADCL Digital path", NULL, "ADCL Power"},
734 {"ADCR Digital path", NULL, "ADCR Power"},
735 {"ADCL Digital path", NULL, "DMIC Enable"},
736 {"ADCR Digital path", NULL, "DMIC Enable"},
738 {"AIFTX", NULL, "ADCL Digital path"},
739 {"AIFTX", NULL, "ADCR Digital path"},
741 {"AIFTX", NULL, "System Clock"},
742 {"AIFRX", NULL, "System Clock"},
744 {"DDACL", NULL, "AIFRX"},
745 {"DDACR", NULL, "AIFRX"},
747 {"HP amp L", NULL, "DDACL"},
748 {"HP amp R", NULL, "DDACR"},
750 {"Charge Pump", NULL, "HP amp L"},
751 {"Charge Pump", NULL, "HP amp R"},
753 {"ADACL", NULL, "Charge Pump"},
754 {"ADACR", NULL, "Charge Pump"},
755 {"ADACL Clock", NULL, "ADACL"},
756 {"ADACR Clock", NULL, "ADACR"},
758 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
759 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
760 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
761 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
762 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
763 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
764 {"Output DACL", NULL, "Output Driver L Stage 3"},
765 {"Output DACR", NULL, "Output Driver R Stage 3"},
767 {"HPOL Pulldown", NULL, "Output DACL"},
768 {"HPOR Pulldown", NULL, "Output DACR"},
769 {"HP Boost Driver", NULL, "HPOL Pulldown"},
770 {"HP Boost Driver", NULL, "HPOR Pulldown"},
772 {"Class G", NULL, "HP Boost Driver"},
773 {"HPOL", NULL, "Class G"},
774 {"HPOR", NULL, "Class G"},
777 static const struct nau8821_osr_attr *
778 nau8821_get_osr(struct nau8821 *nau8821, int stream)
782 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
783 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
784 osr &= NAU8821_DAC_OVERSAMPLE_MASK;
785 if (osr >= ARRAY_SIZE(osr_dac_sel))
787 return &osr_dac_sel[osr];
789 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
790 osr &= NAU8821_ADC_SYNC_DOWN_MASK;
791 if (osr >= ARRAY_SIZE(osr_adc_sel))
793 return &osr_adc_sel[osr];
797 static int nau8821_dai_startup(struct snd_pcm_substream *substream,
798 struct snd_soc_dai *dai)
800 struct snd_soc_component *component = dai->component;
801 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
802 const struct nau8821_osr_attr *osr;
804 osr = nau8821_get_osr(nau8821, substream->stream);
805 if (!osr || !osr->osr)
808 return snd_pcm_hw_constraint_minmax(substream->runtime,
809 SNDRV_PCM_HW_PARAM_RATE,
810 0, CLK_DA_AD_MAX / osr->osr);
813 static int nau8821_hw_params(struct snd_pcm_substream *substream,
814 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
816 struct snd_soc_component *component = dai->component;
817 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
818 unsigned int val_len = 0, ctrl_val, bclk_fs, clk_div;
819 const struct nau8821_osr_attr *osr;
821 nau8821->fs = params_rate(params);
822 /* CLK_DAC or CLK_ADC = OSR * FS
823 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
824 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
825 * values must be selected such that the maximum frequency is less
828 osr = nau8821_get_osr(nau8821, substream->stream);
829 if (!osr || !osr->osr)
831 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
833 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
834 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
835 NAU8821_CLK_DAC_SRC_MASK,
836 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
838 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
839 NAU8821_CLK_ADC_SRC_MASK,
840 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
842 /* make BCLK and LRC divde configuration if the codec as master. */
843 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
844 if (ctrl_val & NAU8821_I2S_MS_MASTER) {
845 /* get the bclk and fs ratio */
846 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
849 else if (bclk_fs <= 64)
851 else if (bclk_fs <= 128)
856 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
857 NAU8821_I2S_LRC_DIV_MASK | NAU8821_I2S_BLK_DIV_MASK,
858 (clk_div << NAU8821_I2S_LRC_DIV_SFT) | clk_div);
861 switch (params_width(params)) {
863 val_len |= NAU8821_I2S_DL_16;
866 val_len |= NAU8821_I2S_DL_20;
869 val_len |= NAU8821_I2S_DL_24;
872 val_len |= NAU8821_I2S_DL_32;
878 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
879 NAU8821_I2S_DL_MASK, val_len);
884 static int nau8821_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
886 struct snd_soc_component *component = codec_dai->component;
887 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
888 unsigned int ctrl1_val = 0, ctrl2_val = 0;
890 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
891 case SND_SOC_DAIFMT_CBP_CFP:
892 ctrl2_val |= NAU8821_I2S_MS_MASTER;
894 case SND_SOC_DAIFMT_CBC_CFC:
900 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
901 case SND_SOC_DAIFMT_NB_NF:
903 case SND_SOC_DAIFMT_IB_NF:
904 ctrl1_val |= NAU8821_I2S_BP_INV;
910 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
911 case SND_SOC_DAIFMT_I2S:
912 ctrl1_val |= NAU8821_I2S_DF_I2S;
914 case SND_SOC_DAIFMT_LEFT_J:
915 ctrl1_val |= NAU8821_I2S_DF_LEFT;
917 case SND_SOC_DAIFMT_RIGHT_J:
918 ctrl1_val |= NAU8821_I2S_DF_RIGTH;
920 case SND_SOC_DAIFMT_DSP_A:
921 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
923 case SND_SOC_DAIFMT_DSP_B:
924 ctrl1_val |= NAU8821_I2S_DF_PCM_AB;
925 ctrl1_val |= NAU8821_I2S_PCMB_EN;
931 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
932 NAU8821_I2S_DL_MASK | NAU8821_I2S_DF_MASK |
933 NAU8821_I2S_BP_MASK | NAU8821_I2S_PCMB_MASK, ctrl1_val);
934 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
935 NAU8821_I2S_MS_MASK, ctrl2_val);
940 static int nau8821_digital_mute(struct snd_soc_dai *dai, int mute,
943 struct snd_soc_component *component = dai->component;
944 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
945 unsigned int val = 0;
948 val = NAU8821_DAC_SOFT_MUTE;
950 return regmap_update_bits(nau8821->regmap,
951 NAU8821_R31_MUTE_CTRL, NAU8821_DAC_SOFT_MUTE, val);
954 static const struct snd_soc_dai_ops nau8821_dai_ops = {
955 .startup = nau8821_dai_startup,
956 .hw_params = nau8821_hw_params,
957 .set_fmt = nau8821_set_dai_fmt,
958 .mute_stream = nau8821_digital_mute,
959 .no_capture_mute = 1,
962 #define NAU8821_RATES SNDRV_PCM_RATE_8000_192000
963 #define NAU8821_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
964 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
966 static struct snd_soc_dai_driver nau8821_dai = {
967 .name = NUVOTON_CODEC_DAI,
969 .stream_name = "Playback",
972 .rates = NAU8821_RATES,
973 .formats = NAU8821_FORMATS,
976 .stream_name = "Capture",
979 .rates = NAU8821_RATES,
980 .formats = NAU8821_FORMATS,
982 .ops = &nau8821_dai_ops,
986 static bool nau8821_is_jack_inserted(struct regmap *regmap)
988 bool active_high, is_high;
991 regmap_read(regmap, NAU8821_R0D_JACK_DET_CTRL, &jkdet);
992 active_high = jkdet & NAU8821_JACK_POLARITY;
993 regmap_read(regmap, NAU8821_R82_GENERAL_STATUS, &status);
994 is_high = status & NAU8821_GPIO2_IN;
995 /* return jack connection status according to jack insertion logic
996 * active high or active low.
998 return active_high == is_high;
1001 static void nau8821_int_status_clear_all(struct regmap *regmap)
1003 int active_irq, clear_irq, i;
1005 /* Reset the intrruption status from rightmost bit if the corres-
1006 * ponding irq event occurs.
1008 regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq);
1009 for (i = 0; i < NAU8821_REG_DATA_LEN; i++) {
1010 clear_irq = (0x1 << i);
1011 if (active_irq & clear_irq)
1012 regmap_write(regmap,
1013 NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1017 static void nau8821_eject_jack(struct nau8821 *nau8821)
1019 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1020 struct regmap *regmap = nau8821->regmap;
1021 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1023 /* Detach 2kOhm Resistors from MICBIAS to MICGND */
1024 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1025 NAU8821_MICBIAS_JKR2, 0);
1026 /* HPL/HPR short to ground */
1027 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1028 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1029 snd_soc_component_disable_pin(component, "MICBIAS");
1030 snd_soc_dapm_sync(dapm);
1032 /* Clear all interruption status */
1033 nau8821_int_status_clear_all(regmap);
1035 /* Enable the insertion interruption, disable the ejection inter-
1036 * ruption, and then bypass de-bounce circuit.
1038 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1039 NAU8821_IRQ_EJECT_DIS | NAU8821_IRQ_INSERT_DIS,
1040 NAU8821_IRQ_EJECT_DIS);
1041 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1042 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1043 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1044 NAU8821_IRQ_EJECT_EN);
1046 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1047 NAU8821_JACK_DET_DB_BYPASS, NAU8821_JACK_DET_DB_BYPASS);
1049 /* Close clock for jack type detection at manual mode */
1050 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
1051 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1053 /* Recover to normal channel input */
1054 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1055 NAU8821_ADC_R_SRC_EN, 0);
1056 if (nau8821->key_enable) {
1057 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1058 NAU8821_IRQ_KEY_RELEASE_EN |
1059 NAU8821_IRQ_KEY_PRESS_EN,
1060 NAU8821_IRQ_KEY_RELEASE_EN |
1061 NAU8821_IRQ_KEY_PRESS_EN);
1062 regmap_update_bits(regmap,
1063 NAU8821_R12_INTERRUPT_DIS_CTRL,
1064 NAU8821_IRQ_KEY_RELEASE_DIS |
1065 NAU8821_IRQ_KEY_PRESS_DIS,
1066 NAU8821_IRQ_KEY_RELEASE_DIS |
1067 NAU8821_IRQ_KEY_PRESS_DIS);
1072 static void nau8821_jdet_work(struct work_struct *work)
1074 struct nau8821 *nau8821 =
1075 container_of(work, struct nau8821, jdet_work);
1076 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1077 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1078 struct regmap *regmap = nau8821->regmap;
1079 int jack_status_reg, mic_detected, event = 0, event_mask = 0;
1081 snd_soc_component_force_enable_pin(component, "MICBIAS");
1082 snd_soc_dapm_sync(dapm);
1085 regmap_read(regmap, NAU8821_R58_I2C_DEVICE_ID, &jack_status_reg);
1086 mic_detected = !(jack_status_reg & NAU8821_KEYDET);
1088 dev_dbg(nau8821->dev, "Headset connected\n");
1089 event |= SND_JACK_HEADSET;
1091 /* 2kOhm Resistor from MICBIAS to MICGND1 */
1092 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1093 NAU8821_MICBIAS_JKR2, NAU8821_MICBIAS_JKR2);
1094 /* Latch Right Channel Analog data
1095 * input into the Right Channel Filter
1097 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1098 NAU8821_ADC_R_SRC_EN, NAU8821_ADC_R_SRC_EN);
1099 if (nau8821->key_enable) {
1100 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1101 NAU8821_IRQ_KEY_RELEASE_EN |
1102 NAU8821_IRQ_KEY_PRESS_EN, 0);
1103 regmap_update_bits(regmap,
1104 NAU8821_R12_INTERRUPT_DIS_CTRL,
1105 NAU8821_IRQ_KEY_RELEASE_DIS |
1106 NAU8821_IRQ_KEY_PRESS_DIS, 0);
1109 dev_dbg(nau8821->dev, "Headphone connected\n");
1110 event |= SND_JACK_HEADPHONE;
1111 snd_soc_component_disable_pin(component, "MICBIAS");
1112 snd_soc_dapm_sync(dapm);
1114 event_mask |= SND_JACK_HEADSET;
1115 snd_soc_jack_report(nau8821->jack, event, event_mask);
1118 /* Enable interruptions with internal clock. */
1119 static void nau8821_setup_inserted_irq(struct nau8821 *nau8821)
1121 struct regmap *regmap = nau8821->regmap;
1123 /* Enable internal VCO needed for interruptions */
1124 if (nau8821->dapm->bias_level < SND_SOC_BIAS_PREPARE)
1125 nau8821_configure_sysclk(nau8821, NAU8821_CLK_INTERNAL, 0);
1127 /* Chip needs one FSCLK cycle in order to generate interruptions,
1128 * as we cannot guarantee one will be provided by the system. Turning
1129 * master mode on then off enables us to generate that FSCLK cycle
1130 * with a minimum of contention on the clock bus.
1132 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1133 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_MASTER);
1134 regmap_update_bits(regmap, NAU8821_R1D_I2S_PCM_CTRL2,
1135 NAU8821_I2S_MS_MASK, NAU8821_I2S_MS_SLAVE);
1137 /* Not bypass de-bounce circuit */
1138 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1139 NAU8821_JACK_DET_DB_BYPASS, 0);
1141 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1142 NAU8821_IRQ_EJECT_EN, 0);
1143 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1144 NAU8821_IRQ_EJECT_DIS, 0);
1147 static irqreturn_t nau8821_interrupt(int irq, void *data)
1149 struct nau8821 *nau8821 = (struct nau8821 *)data;
1150 struct regmap *regmap = nau8821->regmap;
1151 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1153 if (regmap_read(regmap, NAU8821_R10_IRQ_STATUS, &active_irq)) {
1154 dev_err(nau8821->dev, "failed to read irq status\n");
1158 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1160 if ((active_irq & NAU8821_JACK_EJECT_IRQ_MASK) ==
1161 NAU8821_JACK_EJECT_DETECTED) {
1162 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1163 NAU8821_MICDET_MASK, NAU8821_MICDET_DIS);
1164 nau8821_eject_jack(nau8821);
1165 event_mask |= SND_JACK_HEADSET;
1166 clear_irq = NAU8821_JACK_EJECT_IRQ_MASK;
1167 } else if (active_irq & NAU8821_KEY_SHORT_PRESS_IRQ) {
1168 event |= NAU8821_BUTTON;
1169 event_mask |= NAU8821_BUTTON;
1170 clear_irq = NAU8821_KEY_SHORT_PRESS_IRQ;
1171 } else if (active_irq & NAU8821_KEY_RELEASE_IRQ) {
1172 event_mask = NAU8821_BUTTON;
1173 clear_irq = NAU8821_KEY_RELEASE_IRQ;
1174 } else if ((active_irq & NAU8821_JACK_INSERT_IRQ_MASK) ==
1175 NAU8821_JACK_INSERT_DETECTED) {
1176 regmap_update_bits(regmap, NAU8821_R71_ANALOG_ADC_1,
1177 NAU8821_MICDET_MASK, NAU8821_MICDET_EN);
1178 if (nau8821_is_jack_inserted(regmap)) {
1179 /* detect microphone and jack type */
1180 cancel_work_sync(&nau8821->jdet_work);
1181 schedule_work(&nau8821->jdet_work);
1182 /* Turn off insertion interruption at manual mode */
1183 regmap_update_bits(regmap,
1184 NAU8821_R12_INTERRUPT_DIS_CTRL,
1185 NAU8821_IRQ_INSERT_DIS,
1186 NAU8821_IRQ_INSERT_DIS);
1187 regmap_update_bits(regmap,
1188 NAU8821_R0F_INTERRUPT_MASK,
1189 NAU8821_IRQ_INSERT_EN,
1190 NAU8821_IRQ_INSERT_EN);
1191 nau8821_setup_inserted_irq(nau8821);
1193 dev_warn(nau8821->dev,
1194 "Inserted IRQ fired but not connected\n");
1195 nau8821_eject_jack(nau8821);
1200 clear_irq = active_irq;
1201 /* clears the rightmost interruption */
1202 regmap_write(regmap, NAU8821_R11_INT_CLR_KEY_STATUS, clear_irq);
1205 snd_soc_jack_report(nau8821->jack, event, event_mask);
1210 static const struct regmap_config nau8821_regmap_config = {
1211 .val_bits = NAU8821_REG_DATA_LEN,
1212 .reg_bits = NAU8821_REG_ADDR_LEN,
1214 .max_register = NAU8821_REG_MAX,
1215 .readable_reg = nau8821_readable_reg,
1216 .writeable_reg = nau8821_writeable_reg,
1217 .volatile_reg = nau8821_volatile_reg,
1219 .cache_type = REGCACHE_RBTREE,
1220 .reg_defaults = nau8821_reg_defaults,
1221 .num_reg_defaults = ARRAY_SIZE(nau8821_reg_defaults),
1224 static int nau8821_component_probe(struct snd_soc_component *component)
1226 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1227 struct snd_soc_dapm_context *dapm =
1228 snd_soc_component_get_dapm(component);
1230 nau8821->dapm = dapm;
1236 * nau8821_calc_fll_param - Calculate FLL parameters.
1237 * @fll_in: external clock provided to codec.
1238 * @fs: sampling rate.
1239 * @fll_param: Pointer to structure of FLL parameters.
1241 * Calculate FLL parameters to configure codec.
1243 * Returns 0 for success or negative error code.
1245 static int nau8821_calc_fll_param(unsigned int fll_in,
1246 unsigned int fs, struct nau8821_fll *fll_param)
1249 unsigned int fref, i, fvco_sel;
1251 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by
1252 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1253 * FREF = freq_in / NAU8821_FLL_REF_DIV_MASK
1255 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1256 fref = fll_in >> fll_pre_scalar[i].param;
1257 if (fref <= NAU_FREF_MAX)
1260 if (i == ARRAY_SIZE(fll_pre_scalar))
1262 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1264 /* Choose the FLL ratio based on FREF */
1265 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1266 if (fref >= fll_ratio[i].param)
1269 if (i == ARRAY_SIZE(fll_ratio))
1271 fll_param->ratio = fll_ratio[i].val;
1273 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1274 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1275 * guaranteed across the full range of operation.
1276 * FDCO = freq_out * 2 * mclk_src_scaling
1279 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1280 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1281 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1282 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1288 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1290 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1292 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1293 * input based on FDCO, FREF and FLL ratio.
1295 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1296 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1297 fll_param->fll_frac = fvco & 0xffffff;
1302 static void nau8821_fll_apply(struct nau8821 *nau8821,
1303 struct nau8821_fll *fll_param)
1305 struct regmap *regmap = nau8821->regmap;
1307 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1308 NAU8821_CLK_SRC_MASK | NAU8821_CLK_MCLK_SRC_MASK,
1309 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1310 /* Make DSP operate at high speed for better performance. */
1311 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1312 NAU8821_FLL_RATIO_MASK | NAU8821_ICTRL_LATCH_MASK,
1313 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1314 /* FLL 24-bit fractional input */
1315 regmap_write(regmap, NAU8821_R0A_FLL7,
1316 (fll_param->fll_frac >> 16) & 0xff);
1317 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1318 /* FLL 10-bit integer input */
1319 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1320 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1321 /* FLL pre-scaler */
1322 regmap_update_bits(regmap, NAU8821_R07_FLL4,
1323 NAU8821_HIGHBW_EN | NAU8821_FLL_REF_DIV_MASK,
1325 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1326 /* select divided VCO input */
1327 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1328 NAU8821_FLL_CLK_SW_MASK, NAU8821_FLL_CLK_SW_REF);
1329 /* Disable free-running mode */
1330 regmap_update_bits(regmap,
1331 NAU8821_R09_FLL6, NAU8821_DCO_EN, 0);
1332 if (fll_param->fll_frac) {
1333 /* set FLL loop filter enable and cutoff frequency at 500Khz */
1334 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1335 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1336 NAU8821_FLL_FTR_SW_MASK,
1337 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1338 NAU8821_FLL_FTR_SW_FILTER);
1339 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1340 NAU8821_SDM_EN | NAU8821_CUTOFF500,
1341 NAU8821_SDM_EN | NAU8821_CUTOFF500);
1343 /* disable FLL loop filter and cutoff frequency */
1344 regmap_update_bits(regmap, NAU8821_R08_FLL5,
1345 NAU8821_FLL_PDB_DAC_EN | NAU8821_FLL_LOOP_FTR_EN |
1346 NAU8821_FLL_FTR_SW_MASK, NAU8821_FLL_FTR_SW_ACCU);
1347 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1348 NAU8821_SDM_EN | NAU8821_CUTOFF500, 0);
1353 * nau8821_set_fll - FLL configuration of nau8821
1354 * @component: codec component
1355 * @pll_id: PLL requested
1356 * @source: clock source
1357 * @freq_in: frequency of input clock source
1358 * @freq_out: must be 256*Fs in order to achieve the best performance
1360 * The FLL function can select BCLK or MCLK as the input clock source.
1362 * Returns 0 if the parameters have been applied successfully
1363 * or negative error code.
1365 static int nau8821_set_fll(struct snd_soc_component *component,
1366 int pll_id, int source, unsigned int freq_in, unsigned int freq_out)
1368 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1369 struct nau8821_fll fll_set_param, *fll_param = &fll_set_param;
1373 ret = nau8821_calc_fll_param(freq_in, fs, fll_param);
1375 dev_err(nau8821->dev,
1376 "Unsupported input clock %d to output clock %d\n",
1380 dev_dbg(nau8821->dev,
1381 "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1382 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1383 fll_param->fll_int, fll_param->clk_ref_div);
1385 nau8821_fll_apply(nau8821, fll_param);
1387 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1388 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1393 static void nau8821_configure_mclk_as_sysclk(struct regmap *regmap)
1395 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1396 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_MCLK);
1397 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1399 /* Make DSP operate as default setting for power saving. */
1400 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1401 NAU8821_ICTRL_LATCH_MASK, 0);
1404 static int nau8821_configure_sysclk(struct nau8821 *nau8821,
1405 int clk_id, unsigned int freq)
1407 struct regmap *regmap = nau8821->regmap;
1410 case NAU8821_CLK_DIS:
1411 /* Clock provided externally and disable internal VCO clock */
1412 nau8821_configure_mclk_as_sysclk(regmap);
1414 case NAU8821_CLK_MCLK:
1415 nau8821_configure_mclk_as_sysclk(regmap);
1416 /* MCLK not changed by clock tree */
1417 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1418 NAU8821_CLK_MCLK_SRC_MASK, 0);
1420 case NAU8821_CLK_INTERNAL:
1421 if (nau8821_is_jack_inserted(regmap)) {
1422 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1423 NAU8821_DCO_EN, NAU8821_DCO_EN);
1424 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1425 NAU8821_CLK_SRC_MASK, NAU8821_CLK_SRC_VCO);
1426 /* Decrease the VCO frequency and make DSP operate
1427 * as default setting for power saving.
1429 regmap_update_bits(regmap, NAU8821_R03_CLK_DIVIDER,
1430 NAU8821_CLK_MCLK_SRC_MASK, 0xf);
1431 regmap_update_bits(regmap, NAU8821_R04_FLL1,
1432 NAU8821_ICTRL_LATCH_MASK |
1433 NAU8821_FLL_RATIO_MASK, 0x10);
1434 regmap_update_bits(regmap, NAU8821_R09_FLL6,
1435 NAU8821_SDM_EN, NAU8821_SDM_EN);
1438 case NAU8821_CLK_FLL_MCLK:
1439 /* Higher FLL reference input frequency can only set lower
1440 * gain error, such as 0000 for input reference from MCLK
1443 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1444 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1445 NAU8821_FLL_CLK_SRC_MCLK | 0);
1447 case NAU8821_CLK_FLL_BLK:
1448 /* If FLL reference input is from low frequency source,
1449 * higher error gain can apply such as 0xf which has
1450 * the most sensitive gain error correction threshold,
1451 * Therefore, FLL has the most accurate DCO to
1454 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1455 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1456 NAU8821_FLL_CLK_SRC_BLK |
1457 (0xf << NAU8821_GAIN_ERR_SFT));
1459 case NAU8821_CLK_FLL_FS:
1460 /* If FLL reference input is from low frequency source,
1461 * higher error gain can apply such as 0xf which has
1462 * the most sensitive gain error correction threshold,
1463 * Therefore, FLL has the most accurate DCO to
1466 regmap_update_bits(regmap, NAU8821_R06_FLL3,
1467 NAU8821_FLL_CLK_SRC_MASK | NAU8821_GAIN_ERR_MASK,
1468 NAU8821_FLL_CLK_SRC_FS |
1469 (0xf << NAU8821_GAIN_ERR_SFT));
1472 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1475 nau8821->clk_id = clk_id;
1476 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1482 static int nau8821_set_sysclk(struct snd_soc_component *component, int clk_id,
1483 int source, unsigned int freq, int dir)
1485 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1487 return nau8821_configure_sysclk(nau8821, clk_id, freq);
1490 static int nau8821_resume_setup(struct nau8821 *nau8821)
1492 struct regmap *regmap = nau8821->regmap;
1494 /* Close clock when jack type detection at manual mode */
1495 nau8821_configure_sysclk(nau8821, NAU8821_CLK_DIS, 0);
1497 /* Clear all interruption status */
1498 nau8821_int_status_clear_all(regmap);
1500 /* Enable both insertion and ejection interruptions, and then
1501 * bypass de-bounce circuit.
1503 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1504 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN, 0);
1505 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1506 NAU8821_JACK_DET_DB_BYPASS,
1507 NAU8821_JACK_DET_DB_BYPASS);
1508 regmap_update_bits(regmap, NAU8821_R12_INTERRUPT_DIS_CTRL,
1509 NAU8821_IRQ_INSERT_DIS | NAU8821_IRQ_EJECT_DIS, 0);
1515 static int nau8821_set_bias_level(struct snd_soc_component *component,
1516 enum snd_soc_bias_level level)
1518 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1519 struct regmap *regmap = nau8821->regmap;
1522 case SND_SOC_BIAS_ON:
1525 case SND_SOC_BIAS_PREPARE:
1528 case SND_SOC_BIAS_STANDBY:
1529 /* Setup codec configuration after resume */
1530 if (snd_soc_component_get_bias_level(component) ==
1532 nau8821_resume_setup(nau8821);
1535 case SND_SOC_BIAS_OFF:
1536 /* HPL/HPR short to ground */
1537 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1538 NAU8821_SPKR_DWN1R | NAU8821_SPKR_DWN1L, 0);
1540 /* Reset the configuration of jack type for detection.
1541 * Detach 2kOhm Resistors from MICBIAS to MICGND1/2.
1543 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1544 NAU8821_MICBIAS_JKR2, 0);
1545 /* Turn off all interruptions before system shutdown.
1546 * Keep theinterruption quiet before resume
1549 regmap_write(regmap,
1550 NAU8821_R12_INTERRUPT_DIS_CTRL, 0xffff);
1551 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1552 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN,
1553 NAU8821_IRQ_EJECT_EN | NAU8821_IRQ_INSERT_EN);
1563 static int __maybe_unused nau8821_suspend(struct snd_soc_component *component)
1565 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1568 disable_irq(nau8821->irq);
1569 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1570 /* Power down codec power; don't support button wakeup */
1571 snd_soc_component_disable_pin(component, "MICBIAS");
1572 snd_soc_dapm_sync(nau8821->dapm);
1573 regcache_cache_only(nau8821->regmap, true);
1574 regcache_mark_dirty(nau8821->regmap);
1579 static int __maybe_unused nau8821_resume(struct snd_soc_component *component)
1581 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1583 regcache_cache_only(nau8821->regmap, false);
1584 regcache_sync(nau8821->regmap);
1586 enable_irq(nau8821->irq);
1591 static const struct snd_soc_component_driver nau8821_component_driver = {
1592 .probe = nau8821_component_probe,
1593 .set_sysclk = nau8821_set_sysclk,
1594 .set_pll = nau8821_set_fll,
1595 .set_bias_level = nau8821_set_bias_level,
1596 .suspend = nau8821_suspend,
1597 .resume = nau8821_resume,
1598 .controls = nau8821_controls,
1599 .num_controls = ARRAY_SIZE(nau8821_controls),
1600 .dapm_widgets = nau8821_dapm_widgets,
1601 .num_dapm_widgets = ARRAY_SIZE(nau8821_dapm_widgets),
1602 .dapm_routes = nau8821_dapm_routes,
1603 .num_dapm_routes = ARRAY_SIZE(nau8821_dapm_routes),
1604 .suspend_bias_off = 1,
1606 .use_pmdown_time = 1,
1611 * nau8821_enable_jack_detect - Specify a jack for event reporting
1613 * @component: component to register the jack with
1614 * @jack: jack to use to report headset and button events on
1616 * After this function has been called the headset insert/remove and button
1617 * events will be routed to the given jack. Jack can be null to stop
1620 int nau8821_enable_jack_detect(struct snd_soc_component *component,
1621 struct snd_soc_jack *jack)
1623 struct nau8821 *nau8821 = snd_soc_component_get_drvdata(component);
1626 nau8821->jack = jack;
1627 /* Initiate jack detection work queue */
1628 INIT_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1629 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1630 nau8821_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1631 "nau8821", nau8821);
1633 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1640 EXPORT_SYMBOL_GPL(nau8821_enable_jack_detect);
1642 static void nau8821_reset_chip(struct regmap *regmap)
1644 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1645 regmap_write(regmap, NAU8821_R00_RESET, 0xffff);
1648 static void nau8821_print_device_properties(struct nau8821 *nau8821)
1650 struct device *dev = nau8821->dev;
1652 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1653 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1654 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1655 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1656 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1657 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1658 dev_dbg(dev, "jack-insert-debounce: %d\n",
1659 nau8821->jack_insert_debounce);
1660 dev_dbg(dev, "jack-eject-debounce: %d\n",
1661 nau8821->jack_eject_debounce);
1662 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1663 nau8821->dmic_clk_threshold);
1664 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
1667 static int nau8821_read_device_properties(struct device *dev,
1668 struct nau8821 *nau8821)
1672 nau8821->jkdet_enable = device_property_read_bool(dev,
1673 "nuvoton,jkdet-enable");
1674 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1675 "nuvoton,jkdet-pull-enable");
1676 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1677 "nuvoton,jkdet-pull-up");
1678 nau8821->key_enable = device_property_read_bool(dev,
1679 "nuvoton,key-enable");
1680 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1681 &nau8821->jkdet_polarity);
1683 nau8821->jkdet_polarity = 1;
1684 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1685 &nau8821->micbias_voltage);
1687 nau8821->micbias_voltage = 6;
1688 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1689 &nau8821->vref_impedance);
1691 nau8821->vref_impedance = 2;
1692 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1693 &nau8821->jack_insert_debounce);
1695 nau8821->jack_insert_debounce = 7;
1696 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1697 &nau8821->jack_eject_debounce);
1699 nau8821->jack_eject_debounce = 0;
1700 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1701 &nau8821->dmic_clk_threshold);
1703 nau8821->dmic_clk_threshold = 3072000;
1708 static void nau8821_init_regs(struct nau8821 *nau8821)
1710 struct regmap *regmap = nau8821->regmap;
1712 /* Enable Bias/Vmid */
1713 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1714 NAU8821_BIAS_VMID, NAU8821_BIAS_VMID);
1715 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1716 NAU8821_GLOBAL_BIAS_EN, NAU8821_GLOBAL_BIAS_EN);
1717 /* VMID Tieoff setting and enable TESTDAC.
1718 * This sets the analog DAC inputs to a '0' input signal to avoid
1719 * any glitches due to power up transients in both the analog and
1720 * digital DAC circuit.
1722 regmap_update_bits(regmap, NAU8821_R66_BIAS_ADJ,
1723 NAU8821_BIAS_VMID_SEL_MASK | NAU8821_BIAS_TESTDAC_EN,
1724 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1725 NAU8821_BIAS_TESTDAC_EN);
1726 /* Disable short Frame Sync detection logic */
1727 regmap_update_bits(regmap, NAU8821_R1E_LEFT_TIME_SLOT,
1728 NAU8821_DIS_FS_SHORT_DET, NAU8821_DIS_FS_SHORT_DET);
1729 /* Disable Boost Driver, Automatic Short circuit protection enable */
1730 regmap_update_bits(regmap, NAU8821_R76_BOOST,
1731 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1732 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN,
1733 NAU8821_PRECHARGE_DIS | NAU8821_HP_BOOST_DIS |
1734 NAU8821_HP_BOOST_G_DIS | NAU8821_SHORT_SHUTDOWN_EN);
1735 /* Class G timer 64ms */
1736 regmap_update_bits(regmap, NAU8821_R4B_CLASSG_CTRL,
1737 NAU8821_CLASSG_TIMER_MASK,
1738 0x20 << NAU8821_CLASSG_TIMER_SFT);
1739 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1740 regmap_update_bits(regmap, NAU8821_R6A_ANALOG_CONTROL_2,
1741 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1742 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB,
1743 NAU8821_HP_NON_CLASSG_CURRENT_2xADJ |
1744 NAU8821_DAC_CAPACITOR_MSB | NAU8821_DAC_CAPACITOR_LSB);
1745 /* Disable DACR/L power */
1746 regmap_update_bits(regmap, NAU8821_R80_CHARGE_PUMP,
1747 NAU8821_POWER_DOWN_DACR | NAU8821_POWER_DOWN_DACL, 0);
1748 /* DAC clock delay 2ns, VREF */
1749 regmap_update_bits(regmap, NAU8821_R73_RDAC,
1750 NAU8821_DAC_CLK_DELAY_MASK | NAU8821_DAC_VREF_MASK,
1751 (0x2 << NAU8821_DAC_CLK_DELAY_SFT) |
1752 (0x3 << NAU8821_DAC_VREF_SFT));
1754 regmap_update_bits(regmap, NAU8821_R74_MIC_BIAS,
1755 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1756 /* Default oversampling/decimations settings are unusable
1757 * (audible hiss). Set it to something better.
1759 regmap_update_bits(regmap, NAU8821_R2B_ADC_RATE,
1760 NAU8821_ADC_SYNC_DOWN_MASK, NAU8821_ADC_SYNC_DOWN_64);
1761 regmap_update_bits(regmap, NAU8821_R2C_DAC_CTRL1,
1762 NAU8821_DAC_OVERSAMPLE_MASK, NAU8821_DAC_OVERSAMPLE_64);
1765 static int nau8821_setup_irq(struct nau8821 *nau8821)
1767 struct regmap *regmap = nau8821->regmap;
1769 /* Jack detection */
1770 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1771 NAU8821_JKDET_OUTPUT_EN,
1772 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1773 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1774 NAU8821_JKDET_PULL_EN,
1775 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1776 regmap_update_bits(regmap, NAU8821_R1A_GPIO12_CTRL,
1777 NAU8821_JKDET_PULL_UP,
1778 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1779 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1780 NAU8821_JACK_POLARITY,
1781 /* jkdet_polarity - 1 is for active-low */
1782 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1783 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1784 NAU8821_JACK_INSERT_DEBOUNCE_MASK,
1785 nau8821->jack_insert_debounce <<
1786 NAU8821_JACK_INSERT_DEBOUNCE_SFT);
1787 regmap_update_bits(regmap, NAU8821_R0D_JACK_DET_CTRL,
1788 NAU8821_JACK_EJECT_DEBOUNCE_MASK,
1789 nau8821->jack_eject_debounce <<
1790 NAU8821_JACK_EJECT_DEBOUNCE_SFT);
1791 /* Pull up IRQ pin */
1792 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK,
1793 NAU8821_IRQ_PIN_PULL_UP | NAU8821_IRQ_PIN_PULL_EN |
1794 NAU8821_IRQ_OUTPUT_EN, NAU8821_IRQ_PIN_PULL_UP |
1795 NAU8821_IRQ_PIN_PULL_EN | NAU8821_IRQ_OUTPUT_EN);
1796 /* Disable interruption before codec initiation done */
1797 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1798 regmap_update_bits(regmap, NAU8821_R0F_INTERRUPT_MASK, 0x3f5, 0x3f5);
1803 /* Please keep this list alphabetically sorted */
1804 static const struct dmi_system_id nau8821_quirk_table[] = {
1806 /* Positivo CW14Q01P-V2 */
1808 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1809 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"),
1811 .driver_data = (void *)(NAU8821_JD_ACTIVE_HIGH),
1816 static void nau8821_check_quirks(void)
1818 const struct dmi_system_id *dmi_id;
1820 if (quirk_override != -1) {
1821 nau8821_quirk = quirk_override;
1825 dmi_id = dmi_first_match(nau8821_quirk_table);
1827 nau8821_quirk = (unsigned long)dmi_id->driver_data;
1830 static int nau8821_i2c_probe(struct i2c_client *i2c)
1832 struct device *dev = &i2c->dev;
1833 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1837 nau8821 = devm_kzalloc(dev, sizeof(*nau8821), GFP_KERNEL);
1840 nau8821_read_device_properties(dev, nau8821);
1842 i2c_set_clientdata(i2c, nau8821);
1844 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1845 if (IS_ERR(nau8821->regmap))
1846 return PTR_ERR(nau8821->regmap);
1849 nau8821->irq = i2c->irq;
1851 nau8821_check_quirks();
1853 if (nau8821_quirk & NAU8821_JD_ACTIVE_HIGH)
1854 nau8821->jkdet_polarity = 0;
1856 nau8821_print_device_properties(nau8821);
1858 nau8821_reset_chip(nau8821->regmap);
1859 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1861 dev_err(dev, "Failed to read device id (%d)\n", ret);
1864 nau8821_init_regs(nau8821);
1867 nau8821_setup_irq(nau8821);
1869 ret = devm_snd_soc_register_component(&i2c->dev,
1870 &nau8821_component_driver, &nau8821_dai, 1);
1875 static const struct i2c_device_id nau8821_i2c_ids[] = {
1879 MODULE_DEVICE_TABLE(i2c, nau8821_i2c_ids);
1882 static const struct of_device_id nau8821_of_ids[] = {
1883 { .compatible = "nuvoton,nau8821", },
1886 MODULE_DEVICE_TABLE(of, nau8821_of_ids);
1890 static const struct acpi_device_id nau8821_acpi_match[] = {
1894 MODULE_DEVICE_TABLE(acpi, nau8821_acpi_match);
1897 static struct i2c_driver nau8821_driver = {
1900 .of_match_table = of_match_ptr(nau8821_of_ids),
1901 .acpi_match_table = ACPI_PTR(nau8821_acpi_match),
1903 .probe = nau8821_i2c_probe,
1904 .id_table = nau8821_i2c_ids,
1906 module_i2c_driver(nau8821_driver);
1908 MODULE_DESCRIPTION("ASoC nau8821 driver");
1909 MODULE_AUTHOR("John Hsu <kchsu0@nuvoton.com>");
1910 MODULE_AUTHOR("Seven Lee <wtli@nuvoton.com>");
1911 MODULE_LICENSE("GPL");