2 * Copyright (C) ST-Ericsson SA 2012
4 * Author: Ola Lilja <ola.o.lilja@stericsson.com>,
5 * Kristoffer Karlsson <kristoffer.karlsson@stericsson.com>,
6 * Roger Nilsson <roger.xr.nilsson@stericsson.com>,
9 * Based on the early work done by:
10 * Mikko J. Lehto <mikko.lehto@symbio.com>,
11 * Mikko Sarmanne <mikko.sarmanne@symbio.com>,
12 * Jarmo K. Kuronen <jarmo.kuronen@symbio.com>,
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License version 2 as published
19 * by the Free Software Foundation.
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/device.h>
25 #include <linux/slab.h>
26 #include <linux/moduleparam.h>
27 #include <linux/init.h>
28 #include <linux/delay.h>
30 #include <linux/platform_device.h>
31 #include <linux/mutex.h>
32 #include <linux/mfd/abx500/ab8500.h>
33 #include <linux/mfd/abx500.h>
34 #include <linux/mfd/abx500/ab8500-sysctrl.h>
35 #include <linux/mfd/abx500/ab8500-codec.h>
36 #include <linux/regulator/consumer.h>
39 #include <sound/core.h>
40 #include <sound/pcm.h>
41 #include <sound/pcm_params.h>
42 #include <sound/initval.h>
43 #include <sound/soc.h>
44 #include <sound/soc-dapm.h>
45 #include <sound/tlv.h>
47 #include "ab8500-codec.h"
49 /* Macrocell value definitions */
50 #define CLK_32K_OUT2_DISABLE 0x01
51 #define INACTIVE_RESET_AUDIO 0x02
52 #define ENABLE_AUDIO_CLK_TO_AUDIO_BLK 0x10
53 #define ENABLE_VINTCORE12_SUPPLY 0x04
54 #define GPIO27_DIR_OUTPUT 0x04
55 #define GPIO29_DIR_OUTPUT 0x10
56 #define GPIO31_DIR_OUTPUT 0x40
58 /* Macrocell register definitions */
59 #define AB8500_CTRL3_REG 0x0200
60 #define AB8500_GPIO_DIR4_REG 0x1013
62 /* Nr of FIR/IIR-coeff banks in ANC-block */
63 #define AB8500_NR_OF_ANC_COEFF_BANKS 2
65 /* Minimum duration to keep ANC IIR Init bit high or
66 low before proceeding with the configuration sequence */
67 #define AB8500_ANC_SM_DELAY 2000
69 #define AB8500_FILTER_CONTROL(xname, xcount, xmin, xmax) \
70 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
71 .info = filter_control_info, \
72 .get = filter_control_get, .put = filter_control_put, \
73 .private_value = (unsigned long)&(struct filter_control) \
74 {.count = xcount, .min = xmin, .max = xmax} }
76 struct filter_control {
83 static const char * const enum_sid_state[] = {
91 SID_FIR_CONFIGURED = 2,
94 static const char * const enum_anc_state[] = {
97 "FIR and IIR are configured",
104 ANC_UNCONFIGURED = 0,
105 ANC_APPLY_FIR_IIR = 1,
106 ANC_FIR_IIR_CONFIGURED = 2,
108 ANC_FIR_CONFIGURED = 4,
110 ANC_IIR_CONFIGURED = 6
113 /* Analog microphones */
120 struct ab8500_codec_drvdata_dbg {
121 struct regulator *vaud;
122 struct regulator *vamic1;
123 struct regulator *vamic2;
124 struct regulator *vdmic;
127 /* Private data for AB8500 device-driver */
128 struct ab8500_codec_drvdata {
129 struct regmap *regmap;
132 long *sid_fir_values;
133 enum sid_state sid_status;
136 struct mutex anc_lock;
137 long *anc_fir_values;
138 long *anc_iir_values;
139 enum anc_state anc_status;
142 static inline const char *amic_micbias_str(enum amic_micbias micbias)
145 case AMIC_MICBIAS_VAMIC1:
147 case AMIC_MICBIAS_VAMIC2:
154 static inline const char *amic_type_str(enum amic_type type)
157 case AMIC_TYPE_DIFFERENTIAL:
158 return "DIFFERENTIAL";
159 case AMIC_TYPE_SINGLE_ENDED:
160 return "SINGLE ENDED";
167 * Read'n'write functions
170 /* Read a register from the audio-bank of AB8500 */
171 static int ab8500_codec_read_reg(void *context, unsigned int reg,
174 struct device *dev = context;
178 status = abx500_get_register_interruptible(dev, AB8500_AUDIO,
180 *value = (unsigned int)value8;
185 /* Write to a register in the audio-bank of AB8500 */
186 static int ab8500_codec_write_reg(void *context, unsigned int reg,
189 struct device *dev = context;
191 return abx500_set_register_interruptible(dev, AB8500_AUDIO,
195 static const struct regmap_config ab8500_codec_regmap = {
196 .reg_read = ab8500_codec_read_reg,
197 .reg_write = ab8500_codec_write_reg,
206 /* Earpiece source selector */
207 static const char * const enum_ear_lineout_source[] = {"Headset Left",
209 static SOC_ENUM_SINGLE_DECL(dapm_enum_ear_lineout_source, AB8500_DMICFILTCONF,
210 AB8500_DMICFILTCONF_DA3TOEAR, enum_ear_lineout_source);
211 static const struct snd_kcontrol_new dapm_ear_lineout_source =
212 SOC_DAPM_ENUM("Earpiece or LineOut Mono Source",
213 dapm_enum_ear_lineout_source);
217 /* LineOut source selector */
218 static const char * const enum_lineout_source[] = {"Mono Path", "Stereo Path"};
219 static SOC_ENUM_DOUBLE_DECL(dapm_enum_lineout_source, AB8500_ANACONF5,
220 AB8500_ANACONF5_HSLDACTOLOL,
221 AB8500_ANACONF5_HSRDACTOLOR, enum_lineout_source);
222 static const struct snd_kcontrol_new dapm_lineout_source[] = {
223 SOC_DAPM_ENUM("LineOut Source", dapm_enum_lineout_source),
228 /* Speaker Left - ANC selector */
229 static const char * const enum_HFx_sel[] = {"Audio Path", "ANC"};
230 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFl_sel, AB8500_DIGMULTCONF2,
231 AB8500_DIGMULTCONF2_HFLSEL, enum_HFx_sel);
232 static const struct snd_kcontrol_new dapm_HFl_select[] = {
233 SOC_DAPM_ENUM("Speaker Left Source", dapm_enum_HFl_sel),
236 /* Speaker Right - ANC selector */
237 static SOC_ENUM_SINGLE_DECL(dapm_enum_HFr_sel, AB8500_DIGMULTCONF2,
238 AB8500_DIGMULTCONF2_HFRSEL, enum_HFx_sel);
239 static const struct snd_kcontrol_new dapm_HFr_select[] = {
240 SOC_DAPM_ENUM("Speaker Right Source", dapm_enum_HFr_sel),
245 /* Mic 1 - Mic 1a or 1b selector */
246 static const char * const enum_mic1ab_sel[] = {"Mic 1b", "Mic 1a"};
247 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic1ab_sel, AB8500_ANACONF3,
248 AB8500_ANACONF3_MIC1SEL, enum_mic1ab_sel);
249 static const struct snd_kcontrol_new dapm_mic1ab_mux[] = {
250 SOC_DAPM_ENUM("Mic 1a or 1b Select", dapm_enum_mic1ab_sel),
253 /* Mic 1 - AD3 - Mic 1 or DMic 3 selector */
254 static const char * const enum_ad3_sel[] = {"Mic 1", "DMic 3"};
255 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad3_sel, AB8500_DIGMULTCONF1,
256 AB8500_DIGMULTCONF1_AD3SEL, enum_ad3_sel);
257 static const struct snd_kcontrol_new dapm_ad3_select[] = {
258 SOC_DAPM_ENUM("AD3 Source Select", dapm_enum_ad3_sel),
261 /* Mic 1 - AD6 - Mic 1 or DMic 6 selector */
262 static const char * const enum_ad6_sel[] = {"Mic 1", "DMic 6"};
263 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad6_sel, AB8500_DIGMULTCONF1,
264 AB8500_DIGMULTCONF1_AD6SEL, enum_ad6_sel);
265 static const struct snd_kcontrol_new dapm_ad6_select[] = {
266 SOC_DAPM_ENUM("AD6 Source Select", dapm_enum_ad6_sel),
271 /* Mic 2 - AD5 - Mic 2 or DMic 5 selector */
272 static const char * const enum_ad5_sel[] = {"Mic 2", "DMic 5"};
273 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad5_sel, AB8500_DIGMULTCONF1,
274 AB8500_DIGMULTCONF1_AD5SEL, enum_ad5_sel);
275 static const struct snd_kcontrol_new dapm_ad5_select[] = {
276 SOC_DAPM_ENUM("AD5 Source Select", dapm_enum_ad5_sel),
281 /* LineIn left - AD1 - LineIn Left or DMic 1 selector */
282 static const char * const enum_ad1_sel[] = {"LineIn Left", "DMic 1"};
283 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad1_sel, AB8500_DIGMULTCONF1,
284 AB8500_DIGMULTCONF1_AD1SEL, enum_ad1_sel);
285 static const struct snd_kcontrol_new dapm_ad1_select[] = {
286 SOC_DAPM_ENUM("AD1 Source Select", dapm_enum_ad1_sel),
289 /* LineIn right - Mic 2 or LineIn Right selector */
290 static const char * const enum_mic2lr_sel[] = {"Mic 2", "LineIn Right"};
291 static SOC_ENUM_SINGLE_DECL(dapm_enum_mic2lr_sel, AB8500_ANACONF3,
292 AB8500_ANACONF3_LINRSEL, enum_mic2lr_sel);
293 static const struct snd_kcontrol_new dapm_mic2lr_select[] = {
294 SOC_DAPM_ENUM("Mic 2 or LINR Select", dapm_enum_mic2lr_sel),
297 /* LineIn right - AD2 - LineIn Right or DMic2 selector */
298 static const char * const enum_ad2_sel[] = {"LineIn Right", "DMic 2"};
299 static SOC_ENUM_SINGLE_DECL(dapm_enum_ad2_sel, AB8500_DIGMULTCONF1,
300 AB8500_DIGMULTCONF1_AD2SEL, enum_ad2_sel);
301 static const struct snd_kcontrol_new dapm_ad2_select[] = {
302 SOC_DAPM_ENUM("AD2 Source Select", dapm_enum_ad2_sel),
308 static const char * const enum_anc_in_sel[] = {"Mic 1 / DMic 6",
310 static SOC_ENUM_SINGLE_DECL(dapm_enum_anc_in_sel, AB8500_DMICFILTCONF,
311 AB8500_DMICFILTCONF_ANCINSEL, enum_anc_in_sel);
312 static const struct snd_kcontrol_new dapm_anc_in_select[] = {
313 SOC_DAPM_ENUM("ANC Source", dapm_enum_anc_in_sel),
316 /* ANC - Enable/Disable */
317 static const struct snd_kcontrol_new dapm_anc_enable[] = {
318 SOC_DAPM_SINGLE("Switch", AB8500_ANCCONF1,
319 AB8500_ANCCONF1_ENANC, 0, 0),
322 /* ANC to Earpiece - Mute */
323 static const struct snd_kcontrol_new dapm_anc_ear_mute[] = {
324 SOC_DAPM_SINGLE("Switch", AB8500_DIGMULTCONF1,
325 AB8500_DIGMULTCONF1_ANCSEL, 1, 0),
332 /* Sidetone left - Input selector */
333 static const char * const enum_stfir1_in_sel[] = {
334 "LineIn Left", "LineIn Right", "Mic 1", "Headset Left"
336 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir1_in_sel, AB8500_DIGMULTCONF2,
337 AB8500_DIGMULTCONF2_FIRSID1SEL, enum_stfir1_in_sel);
338 static const struct snd_kcontrol_new dapm_stfir1_in_select[] = {
339 SOC_DAPM_ENUM("Sidetone Left Source", dapm_enum_stfir1_in_sel),
342 /* Sidetone right path */
344 /* Sidetone right - Input selector */
345 static const char * const enum_stfir2_in_sel[] = {
346 "LineIn Right", "Mic 1", "DMic 4", "Headset Right"
348 static SOC_ENUM_SINGLE_DECL(dapm_enum_stfir2_in_sel, AB8500_DIGMULTCONF2,
349 AB8500_DIGMULTCONF2_FIRSID2SEL, enum_stfir2_in_sel);
350 static const struct snd_kcontrol_new dapm_stfir2_in_select[] = {
351 SOC_DAPM_ENUM("Sidetone Right Source", dapm_enum_stfir2_in_sel),
356 static const char * const enum_pwm2vibx[] = {"Audio Path", "PWM Generator"};
358 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib1, AB8500_PWMGENCONF1,
359 AB8500_PWMGENCONF1_PWMTOVIB1, enum_pwm2vibx);
361 static const struct snd_kcontrol_new dapm_pwm2vib1[] = {
362 SOC_DAPM_ENUM("Vibra 1 Controller", dapm_enum_pwm2vib1),
365 static SOC_ENUM_SINGLE_DECL(dapm_enum_pwm2vib2, AB8500_PWMGENCONF1,
366 AB8500_PWMGENCONF1_PWMTOVIB2, enum_pwm2vibx);
368 static const struct snd_kcontrol_new dapm_pwm2vib2[] = {
369 SOC_DAPM_ENUM("Vibra 2 Controller", dapm_enum_pwm2vib2),
376 static const struct snd_soc_dapm_widget ab8500_dapm_widgets[] = {
379 SND_SOC_DAPM_CLOCK_SUPPLY("audioclk"),
382 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AUD", 0, 0),
383 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC1", 0, 0),
384 SND_SOC_DAPM_REGULATOR_SUPPLY("V-AMIC2", 0, 0),
385 SND_SOC_DAPM_REGULATOR_SUPPLY("V-DMIC", 0, 0),
388 SND_SOC_DAPM_SUPPLY("Audio Power",
389 AB8500_POWERUP, AB8500_POWERUP_POWERUP, 0,
390 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
391 SND_SOC_DAPM_SUPPLY("Audio Analog Power",
392 AB8500_POWERUP, AB8500_POWERUP_ENANA, 0,
393 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
395 /* Main supply node */
396 SND_SOC_DAPM_SUPPLY("Main Supply", SND_SOC_NOPM, 0, 0,
397 NULL, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
401 SND_SOC_DAPM_INPUT("ADC Input"),
402 SND_SOC_DAPM_ADC("ADC", "ab8500_0c", SND_SOC_NOPM, 0, 0),
404 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
405 SND_SOC_DAPM_OUTPUT("DAC Output"),
407 SND_SOC_DAPM_AIF_IN("DA_IN1", NULL, 0, SND_SOC_NOPM, 0, 0),
408 SND_SOC_DAPM_AIF_IN("DA_IN2", NULL, 0, SND_SOC_NOPM, 0, 0),
409 SND_SOC_DAPM_AIF_IN("DA_IN3", NULL, 0, SND_SOC_NOPM, 0, 0),
410 SND_SOC_DAPM_AIF_IN("DA_IN4", NULL, 0, SND_SOC_NOPM, 0, 0),
411 SND_SOC_DAPM_AIF_IN("DA_IN5", NULL, 0, SND_SOC_NOPM, 0, 0),
412 SND_SOC_DAPM_AIF_IN("DA_IN6", NULL, 0, SND_SOC_NOPM, 0, 0),
413 SND_SOC_DAPM_AIF_OUT("AD_OUT1", NULL, 0, SND_SOC_NOPM, 0, 0),
414 SND_SOC_DAPM_AIF_OUT("AD_OUT2", NULL, 0, SND_SOC_NOPM, 0, 0),
415 SND_SOC_DAPM_AIF_OUT("AD_OUT3", NULL, 0, SND_SOC_NOPM, 0, 0),
416 SND_SOC_DAPM_AIF_OUT("AD_OUT4", NULL, 0, SND_SOC_NOPM, 0, 0),
417 SND_SOC_DAPM_AIF_OUT("AD_OUT57", NULL, 0, SND_SOC_NOPM, 0, 0),
418 SND_SOC_DAPM_AIF_OUT("AD_OUT68", NULL, 0, SND_SOC_NOPM, 0, 0),
422 SND_SOC_DAPM_SUPPLY("Charge Pump", AB8500_ANACONF5,
423 AB8500_ANACONF5_ENCPHS, 0, NULL, 0),
425 SND_SOC_DAPM_DAC("DA1 Enable", "ab8500_0p",
426 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA1, 0),
427 SND_SOC_DAPM_DAC("DA2 Enable", "ab8500_0p",
428 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA2, 0),
430 SND_SOC_DAPM_PGA("HSL Digital Volume", SND_SOC_NOPM, 0, 0,
432 SND_SOC_DAPM_PGA("HSR Digital Volume", SND_SOC_NOPM, 0, 0,
435 SND_SOC_DAPM_DAC("HSL DAC", "ab8500_0p",
436 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSL, 0),
437 SND_SOC_DAPM_DAC("HSR DAC", "ab8500_0p",
438 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHSR, 0),
439 SND_SOC_DAPM_MIXER("HSL DAC Mute", AB8500_MUTECONF,
440 AB8500_MUTECONF_MUTDACHSL, 1,
442 SND_SOC_DAPM_MIXER("HSR DAC Mute", AB8500_MUTECONF,
443 AB8500_MUTECONF_MUTDACHSR, 1,
445 SND_SOC_DAPM_DAC("HSL DAC Driver", "ab8500_0p",
446 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSL, 0),
447 SND_SOC_DAPM_DAC("HSR DAC Driver", "ab8500_0p",
448 AB8500_ANACONF3, AB8500_ANACONF3_ENDRVHSR, 0),
450 SND_SOC_DAPM_MIXER("HSL Mute",
451 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSL, 1,
453 SND_SOC_DAPM_MIXER("HSR Mute",
454 AB8500_MUTECONF, AB8500_MUTECONF_MUTHSR, 1,
456 SND_SOC_DAPM_MIXER("HSL Enable",
457 AB8500_ANACONF4, AB8500_ANACONF4_ENHSL, 0,
459 SND_SOC_DAPM_MIXER("HSR Enable",
460 AB8500_ANACONF4, AB8500_ANACONF4_ENHSR, 0,
462 SND_SOC_DAPM_PGA("HSL Volume",
465 SND_SOC_DAPM_PGA("HSR Volume",
469 SND_SOC_DAPM_OUTPUT("Headset Left"),
470 SND_SOC_DAPM_OUTPUT("Headset Right"),
474 SND_SOC_DAPM_MUX("LineOut Source",
475 SND_SOC_NOPM, 0, 0, dapm_lineout_source),
477 SND_SOC_DAPM_MIXER("LOL Disable HFL",
478 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 1,
480 SND_SOC_DAPM_MIXER("LOR Disable HFR",
481 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 1,
484 SND_SOC_DAPM_MIXER("LOL Enable",
485 AB8500_ANACONF5, AB8500_ANACONF5_ENLOL, 0,
487 SND_SOC_DAPM_MIXER("LOR Enable",
488 AB8500_ANACONF5, AB8500_ANACONF5_ENLOR, 0,
491 SND_SOC_DAPM_OUTPUT("LineOut Left"),
492 SND_SOC_DAPM_OUTPUT("LineOut Right"),
496 SND_SOC_DAPM_MUX("Earpiece or LineOut Mono Source",
497 SND_SOC_NOPM, 0, 0, &dapm_ear_lineout_source),
498 SND_SOC_DAPM_MIXER("EAR DAC",
499 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACEAR, 0,
501 SND_SOC_DAPM_MIXER("EAR Mute",
502 AB8500_MUTECONF, AB8500_MUTECONF_MUTEAR, 1,
504 SND_SOC_DAPM_MIXER("EAR Enable",
505 AB8500_ANACONF4, AB8500_ANACONF4_ENEAR, 0,
508 SND_SOC_DAPM_OUTPUT("Earpiece"),
512 SND_SOC_DAPM_MIXER("DA3 Channel Volume",
513 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA3, 0,
515 SND_SOC_DAPM_MIXER("DA4 Channel Volume",
516 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA4, 0,
518 SND_SOC_DAPM_MUX("Speaker Left Source",
519 SND_SOC_NOPM, 0, 0, dapm_HFl_select),
520 SND_SOC_DAPM_MUX("Speaker Right Source",
521 SND_SOC_NOPM, 0, 0, dapm_HFr_select),
522 SND_SOC_DAPM_MIXER("HFL DAC", AB8500_DAPATHCONF,
523 AB8500_DAPATHCONF_ENDACHFL, 0,
525 SND_SOC_DAPM_MIXER("HFR DAC",
526 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACHFR, 0,
528 SND_SOC_DAPM_MIXER("DA4 or ANC path to HfR",
529 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFREN, 0,
531 SND_SOC_DAPM_MIXER("DA3 or ANC path to HfL",
532 AB8500_DIGMULTCONF2, AB8500_DIGMULTCONF2_DATOHFLEN, 0,
534 SND_SOC_DAPM_MIXER("HFL Enable",
535 AB8500_ANACONF4, AB8500_ANACONF4_ENHFL, 0,
537 SND_SOC_DAPM_MIXER("HFR Enable",
538 AB8500_ANACONF4, AB8500_ANACONF4_ENHFR, 0,
541 SND_SOC_DAPM_OUTPUT("Speaker Left"),
542 SND_SOC_DAPM_OUTPUT("Speaker Right"),
546 SND_SOC_DAPM_INPUT("PWMGEN1"),
547 SND_SOC_DAPM_INPUT("PWMGEN2"),
549 SND_SOC_DAPM_MIXER("DA5 Channel Volume",
550 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA5, 0,
552 SND_SOC_DAPM_MIXER("DA6 Channel Volume",
553 AB8500_DAPATHENA, AB8500_DAPATHENA_ENDA6, 0,
555 SND_SOC_DAPM_MIXER("VIB1 DAC",
556 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB1, 0,
558 SND_SOC_DAPM_MIXER("VIB2 DAC",
559 AB8500_DAPATHCONF, AB8500_DAPATHCONF_ENDACVIB2, 0,
561 SND_SOC_DAPM_MUX("Vibra 1 Controller",
562 SND_SOC_NOPM, 0, 0, dapm_pwm2vib1),
563 SND_SOC_DAPM_MUX("Vibra 2 Controller",
564 SND_SOC_NOPM, 0, 0, dapm_pwm2vib2),
565 SND_SOC_DAPM_MIXER("VIB1 Enable",
566 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB1, 0,
568 SND_SOC_DAPM_MIXER("VIB2 Enable",
569 AB8500_ANACONF4, AB8500_ANACONF4_ENVIB2, 0,
572 SND_SOC_DAPM_OUTPUT("Vibra 1"),
573 SND_SOC_DAPM_OUTPUT("Vibra 2"),
577 SND_SOC_DAPM_INPUT("Mic 1"),
579 SND_SOC_DAPM_MUX("Mic 1a or 1b Select",
580 SND_SOC_NOPM, 0, 0, dapm_mic1ab_mux),
581 SND_SOC_DAPM_MIXER("MIC1 Mute",
582 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC1, 1,
584 SND_SOC_DAPM_MIXER("MIC1A V-AMICx Enable",
585 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
587 SND_SOC_DAPM_MIXER("MIC1B V-AMICx Enable",
588 AB8500_ANACONF2, AB8500_ANACONF2_ENMIC1, 0,
590 SND_SOC_DAPM_MIXER("MIC1 ADC",
591 AB8500_ANACONF3, AB8500_ANACONF3_ENADCMIC, 0,
593 SND_SOC_DAPM_MUX("AD3 Source Select",
594 SND_SOC_NOPM, 0, 0, dapm_ad3_select),
595 SND_SOC_DAPM_MIXER("AD3 Channel Volume",
598 SND_SOC_DAPM_MIXER("AD3 Enable",
599 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34, 0,
604 SND_SOC_DAPM_INPUT("Mic 2"),
606 SND_SOC_DAPM_MIXER("MIC2 Mute",
607 AB8500_ANACONF2, AB8500_ANACONF2_MUTMIC2, 1,
609 SND_SOC_DAPM_MIXER("MIC2 V-AMICx Enable", AB8500_ANACONF2,
610 AB8500_ANACONF2_ENMIC2, 0,
615 SND_SOC_DAPM_INPUT("LineIn Left"),
616 SND_SOC_DAPM_INPUT("LineIn Right"),
618 SND_SOC_DAPM_MIXER("LINL Mute",
619 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINL, 1,
621 SND_SOC_DAPM_MIXER("LINR Mute",
622 AB8500_ANACONF2, AB8500_ANACONF2_MUTLINR, 1,
624 SND_SOC_DAPM_MIXER("LINL Enable", AB8500_ANACONF2,
625 AB8500_ANACONF2_ENLINL, 0,
627 SND_SOC_DAPM_MIXER("LINR Enable", AB8500_ANACONF2,
628 AB8500_ANACONF2_ENLINR, 0,
631 /* LineIn Bypass path */
632 SND_SOC_DAPM_MIXER("LINL to HSL Volume",
635 SND_SOC_DAPM_MIXER("LINR to HSR Volume",
640 SND_SOC_DAPM_MUX("Mic 2 or LINR Select",
641 SND_SOC_NOPM, 0, 0, dapm_mic2lr_select),
642 SND_SOC_DAPM_MIXER("LINL ADC", AB8500_ANACONF3,
643 AB8500_ANACONF3_ENADCLINL, 0,
645 SND_SOC_DAPM_MIXER("LINR ADC", AB8500_ANACONF3,
646 AB8500_ANACONF3_ENADCLINR, 0,
648 SND_SOC_DAPM_MUX("AD1 Source Select",
649 SND_SOC_NOPM, 0, 0, dapm_ad1_select),
650 SND_SOC_DAPM_MUX("AD2 Source Select",
651 SND_SOC_NOPM, 0, 0, dapm_ad2_select),
652 SND_SOC_DAPM_MIXER("AD1 Channel Volume",
655 SND_SOC_DAPM_MIXER("AD2 Channel Volume",
659 SND_SOC_DAPM_MIXER("AD12 Enable",
660 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD12, 0,
663 /* HD Capture path */
665 SND_SOC_DAPM_MUX("AD5 Source Select",
666 SND_SOC_NOPM, 0, 0, dapm_ad5_select),
667 SND_SOC_DAPM_MUX("AD6 Source Select",
668 SND_SOC_NOPM, 0, 0, dapm_ad6_select),
669 SND_SOC_DAPM_MIXER("AD5 Channel Volume",
672 SND_SOC_DAPM_MIXER("AD6 Channel Volume",
675 SND_SOC_DAPM_MIXER("AD57 Enable",
676 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
678 SND_SOC_DAPM_MIXER("AD68 Enable",
679 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD5768, 0,
682 /* Digital Microphone path */
684 SND_SOC_DAPM_INPUT("DMic 1"),
685 SND_SOC_DAPM_INPUT("DMic 2"),
686 SND_SOC_DAPM_INPUT("DMic 3"),
687 SND_SOC_DAPM_INPUT("DMic 4"),
688 SND_SOC_DAPM_INPUT("DMic 5"),
689 SND_SOC_DAPM_INPUT("DMic 6"),
691 SND_SOC_DAPM_MIXER("DMIC1",
692 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC1, 0,
694 SND_SOC_DAPM_MIXER("DMIC2",
695 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC2, 0,
697 SND_SOC_DAPM_MIXER("DMIC3",
698 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC3, 0,
700 SND_SOC_DAPM_MIXER("DMIC4",
701 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC4, 0,
703 SND_SOC_DAPM_MIXER("DMIC5",
704 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC5, 0,
706 SND_SOC_DAPM_MIXER("DMIC6",
707 AB8500_DIGMICCONF, AB8500_DIGMICCONF_ENDMIC6, 0,
709 SND_SOC_DAPM_MIXER("AD4 Channel Volume",
712 SND_SOC_DAPM_MIXER("AD4 Enable",
713 AB8500_ADPATHENA, AB8500_ADPATHENA_ENAD34,
716 /* Acoustical Noise Cancellation path */
718 SND_SOC_DAPM_INPUT("ANC Configure Input"),
719 SND_SOC_DAPM_OUTPUT("ANC Configure Output"),
721 SND_SOC_DAPM_MUX("ANC Source",
724 SND_SOC_DAPM_SWITCH("ANC",
727 SND_SOC_DAPM_SWITCH("ANC to Earpiece",
731 /* Sidetone Filter path */
733 SND_SOC_DAPM_MUX("Sidetone Left Source",
735 dapm_stfir1_in_select),
736 SND_SOC_DAPM_MUX("Sidetone Right Source",
738 dapm_stfir2_in_select),
739 SND_SOC_DAPM_MIXER("STFIR1 Control",
742 SND_SOC_DAPM_MIXER("STFIR2 Control",
745 SND_SOC_DAPM_MIXER("STFIR1 Volume",
748 SND_SOC_DAPM_MIXER("STFIR2 Volume",
756 static const struct snd_soc_dapm_route ab8500_dapm_routes[] = {
757 /* Power AB8500 audio-block when AD/DA is active */
758 {"Main Supply", NULL, "V-AUD"},
759 {"Main Supply", NULL, "audioclk"},
760 {"Main Supply", NULL, "Audio Power"},
761 {"Main Supply", NULL, "Audio Analog Power"},
763 {"DAC", NULL, "ab8500_0p"},
764 {"DAC", NULL, "Main Supply"},
765 {"ADC", NULL, "ab8500_0c"},
766 {"ADC", NULL, "Main Supply"},
769 {"ANC Configure Input", NULL, "Main Supply"},
770 {"ANC Configure Output", NULL, "ANC Configure Input"},
773 {"ADC", NULL, "ADC Input"},
774 {"DAC Output", NULL, "DAC"},
776 /* Powerup charge pump if DA1/2 is in use */
778 {"DA_IN1", NULL, "ab8500_0p"},
779 {"DA_IN1", NULL, "Charge Pump"},
780 {"DA_IN2", NULL, "ab8500_0p"},
781 {"DA_IN2", NULL, "Charge Pump"},
785 {"DA1 Enable", NULL, "DA_IN1"},
786 {"DA2 Enable", NULL, "DA_IN2"},
788 {"HSL Digital Volume", NULL, "DA1 Enable"},
789 {"HSR Digital Volume", NULL, "DA2 Enable"},
791 {"HSL DAC", NULL, "HSL Digital Volume"},
792 {"HSR DAC", NULL, "HSR Digital Volume"},
794 {"HSL DAC Mute", NULL, "HSL DAC"},
795 {"HSR DAC Mute", NULL, "HSR DAC"},
797 {"HSL DAC Driver", NULL, "HSL DAC Mute"},
798 {"HSR DAC Driver", NULL, "HSR DAC Mute"},
800 {"HSL Mute", NULL, "HSL DAC Driver"},
801 {"HSR Mute", NULL, "HSR DAC Driver"},
803 {"HSL Enable", NULL, "HSL Mute"},
804 {"HSR Enable", NULL, "HSR Mute"},
806 {"HSL Volume", NULL, "HSL Enable"},
807 {"HSR Volume", NULL, "HSR Enable"},
809 {"Headset Left", NULL, "HSL Volume"},
810 {"Headset Right", NULL, "HSR Volume"},
812 /* HF or LineOut path */
814 {"DA_IN3", NULL, "ab8500_0p"},
815 {"DA3 Channel Volume", NULL, "DA_IN3"},
816 {"DA_IN4", NULL, "ab8500_0p"},
817 {"DA4 Channel Volume", NULL, "DA_IN4"},
819 {"Speaker Left Source", "Audio Path", "DA3 Channel Volume"},
820 {"Speaker Right Source", "Audio Path", "DA4 Channel Volume"},
822 {"DA3 or ANC path to HfL", NULL, "Speaker Left Source"},
823 {"DA4 or ANC path to HfR", NULL, "Speaker Right Source"},
827 {"HFL DAC", NULL, "DA3 or ANC path to HfL"},
828 {"HFR DAC", NULL, "DA4 or ANC path to HfR"},
830 {"HFL Enable", NULL, "HFL DAC"},
831 {"HFR Enable", NULL, "HFR DAC"},
833 {"Speaker Left", NULL, "HFL Enable"},
834 {"Speaker Right", NULL, "HFR Enable"},
838 {"Earpiece or LineOut Mono Source", "Headset Left",
839 "HSL Digital Volume"},
840 {"Earpiece or LineOut Mono Source", "Speaker Left",
841 "DA3 or ANC path to HfL"},
843 {"EAR DAC", NULL, "Earpiece or LineOut Mono Source"},
845 {"EAR Mute", NULL, "EAR DAC"},
847 {"EAR Enable", NULL, "EAR Mute"},
849 {"Earpiece", NULL, "EAR Enable"},
851 /* LineOut path stereo */
853 {"LineOut Source", "Stereo Path", "HSL DAC Driver"},
854 {"LineOut Source", "Stereo Path", "HSR DAC Driver"},
856 /* LineOut path mono */
858 {"LineOut Source", "Mono Path", "EAR DAC"},
862 {"LOL Disable HFL", NULL, "LineOut Source"},
863 {"LOR Disable HFR", NULL, "LineOut Source"},
865 {"LOL Enable", NULL, "LOL Disable HFL"},
866 {"LOR Enable", NULL, "LOR Disable HFR"},
868 {"LineOut Left", NULL, "LOL Enable"},
869 {"LineOut Right", NULL, "LOR Enable"},
873 {"DA_IN5", NULL, "ab8500_0p"},
874 {"DA5 Channel Volume", NULL, "DA_IN5"},
875 {"DA_IN6", NULL, "ab8500_0p"},
876 {"DA6 Channel Volume", NULL, "DA_IN6"},
878 {"VIB1 DAC", NULL, "DA5 Channel Volume"},
879 {"VIB2 DAC", NULL, "DA6 Channel Volume"},
881 {"Vibra 1 Controller", "Audio Path", "VIB1 DAC"},
882 {"Vibra 2 Controller", "Audio Path", "VIB2 DAC"},
883 {"Vibra 1 Controller", "PWM Generator", "PWMGEN1"},
884 {"Vibra 2 Controller", "PWM Generator", "PWMGEN2"},
886 {"VIB1 Enable", NULL, "Vibra 1 Controller"},
887 {"VIB2 Enable", NULL, "Vibra 2 Controller"},
889 {"Vibra 1", NULL, "VIB1 Enable"},
890 {"Vibra 2", NULL, "VIB2 Enable"},
895 {"MIC2 V-AMICx Enable", NULL, "Mic 2"},
898 {"LINL Mute", NULL, "LineIn Left"},
899 {"LINR Mute", NULL, "LineIn Right"},
901 {"LINL Enable", NULL, "LINL Mute"},
902 {"LINR Enable", NULL, "LINR Mute"},
905 {"Mic 2 or LINR Select", "LineIn Right", "LINR Enable"},
906 {"Mic 2 or LINR Select", "Mic 2", "MIC2 V-AMICx Enable"},
908 {"LINL ADC", NULL, "LINL Enable"},
909 {"LINR ADC", NULL, "Mic 2 or LINR Select"},
911 {"AD1 Source Select", "LineIn Left", "LINL ADC"},
912 {"AD2 Source Select", "LineIn Right", "LINR ADC"},
914 {"AD1 Channel Volume", NULL, "AD1 Source Select"},
915 {"AD2 Channel Volume", NULL, "AD2 Source Select"},
917 {"AD12 Enable", NULL, "AD1 Channel Volume"},
918 {"AD12 Enable", NULL, "AD2 Channel Volume"},
920 {"AD_OUT1", NULL, "ab8500_0c"},
921 {"AD_OUT1", NULL, "AD12 Enable"},
922 {"AD_OUT2", NULL, "ab8500_0c"},
923 {"AD_OUT2", NULL, "AD12 Enable"},
927 {"MIC1 Mute", NULL, "Mic 1"},
929 {"MIC1A V-AMICx Enable", NULL, "MIC1 Mute"},
930 {"MIC1B V-AMICx Enable", NULL, "MIC1 Mute"},
932 {"Mic 1a or 1b Select", "Mic 1a", "MIC1A V-AMICx Enable"},
933 {"Mic 1a or 1b Select", "Mic 1b", "MIC1B V-AMICx Enable"},
935 {"MIC1 ADC", NULL, "Mic 1a or 1b Select"},
937 {"AD3 Source Select", "Mic 1", "MIC1 ADC"},
939 {"AD3 Channel Volume", NULL, "AD3 Source Select"},
941 {"AD3 Enable", NULL, "AD3 Channel Volume"},
943 {"AD_OUT3", NULL, "ab8500_0c"},
944 {"AD_OUT3", NULL, "AD3 Enable"},
946 /* HD Capture path */
948 {"AD5 Source Select", "Mic 2", "LINR ADC"},
949 {"AD6 Source Select", "Mic 1", "MIC1 ADC"},
951 {"AD5 Channel Volume", NULL, "AD5 Source Select"},
952 {"AD6 Channel Volume", NULL, "AD6 Source Select"},
954 {"AD57 Enable", NULL, "AD5 Channel Volume"},
955 {"AD68 Enable", NULL, "AD6 Channel Volume"},
957 {"AD_OUT57", NULL, "ab8500_0c"},
958 {"AD_OUT57", NULL, "AD57 Enable"},
959 {"AD_OUT68", NULL, "ab8500_0c"},
960 {"AD_OUT68", NULL, "AD68 Enable"},
962 /* Digital Microphone path */
964 {"DMic 1", NULL, "V-DMIC"},
965 {"DMic 2", NULL, "V-DMIC"},
966 {"DMic 3", NULL, "V-DMIC"},
967 {"DMic 4", NULL, "V-DMIC"},
968 {"DMic 5", NULL, "V-DMIC"},
969 {"DMic 6", NULL, "V-DMIC"},
971 {"AD1 Source Select", NULL, "DMic 1"},
972 {"AD2 Source Select", NULL, "DMic 2"},
973 {"AD3 Source Select", NULL, "DMic 3"},
974 {"AD5 Source Select", NULL, "DMic 5"},
975 {"AD6 Source Select", NULL, "DMic 6"},
977 {"AD4 Channel Volume", NULL, "DMic 4"},
978 {"AD4 Enable", NULL, "AD4 Channel Volume"},
980 {"AD_OUT4", NULL, "ab8500_0c"},
981 {"AD_OUT4", NULL, "AD4 Enable"},
983 /* LineIn Bypass path */
985 {"LINL to HSL Volume", NULL, "LINL Enable"},
986 {"LINR to HSR Volume", NULL, "LINR Enable"},
988 {"HSL DAC Driver", NULL, "LINL to HSL Volume"},
989 {"HSR DAC Driver", NULL, "LINR to HSR Volume"},
991 /* ANC path (Acoustic Noise Cancellation) */
993 {"ANC Source", "Mic 2 / DMic 5", "AD5 Channel Volume"},
994 {"ANC Source", "Mic 1 / DMic 6", "AD6 Channel Volume"},
996 {"ANC", "Switch", "ANC Source"},
998 {"Speaker Left Source", "ANC", "ANC"},
999 {"Speaker Right Source", "ANC", "ANC"},
1000 {"ANC to Earpiece", "Switch", "ANC"},
1002 {"HSL Digital Volume", NULL, "ANC to Earpiece"},
1004 /* Sidetone Filter path */
1006 {"Sidetone Left Source", "LineIn Left", "AD12 Enable"},
1007 {"Sidetone Left Source", "LineIn Right", "AD12 Enable"},
1008 {"Sidetone Left Source", "Mic 1", "AD3 Enable"},
1009 {"Sidetone Left Source", "Headset Left", "DA_IN1"},
1010 {"Sidetone Right Source", "LineIn Right", "AD12 Enable"},
1011 {"Sidetone Right Source", "Mic 1", "AD3 Enable"},
1012 {"Sidetone Right Source", "DMic 4", "AD4 Enable"},
1013 {"Sidetone Right Source", "Headset Right", "DA_IN2"},
1015 {"STFIR1 Control", NULL, "Sidetone Left Source"},
1016 {"STFIR2 Control", NULL, "Sidetone Right Source"},
1018 {"STFIR1 Volume", NULL, "STFIR1 Control"},
1019 {"STFIR2 Volume", NULL, "STFIR2 Control"},
1021 {"DA1 Enable", NULL, "STFIR1 Volume"},
1022 {"DA2 Enable", NULL, "STFIR2 Volume"},
1025 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1a_vamicx[] = {
1026 {"MIC1A V-AMICx Enable", NULL, "V-AMIC1"},
1027 {"MIC1A V-AMICx Enable", NULL, "V-AMIC2"},
1030 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic1b_vamicx[] = {
1031 {"MIC1B V-AMICx Enable", NULL, "V-AMIC1"},
1032 {"MIC1B V-AMICx Enable", NULL, "V-AMIC2"},
1035 static const struct snd_soc_dapm_route ab8500_dapm_routes_mic2_vamicx[] = {
1036 {"MIC2 V-AMICx Enable", NULL, "V-AMIC1"},
1037 {"MIC2 V-AMICx Enable", NULL, "V-AMIC2"},
1040 /* ANC FIR-coefficients configuration sequence */
1041 static void anc_fir(struct snd_soc_codec *codec,
1042 unsigned int bnk, unsigned int par, unsigned int val)
1044 if (par == 0 && bnk == 0)
1045 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1046 BIT(AB8500_ANCCONF1_ANCFIRUPDATE),
1047 BIT(AB8500_ANCCONF1_ANCFIRUPDATE));
1049 snd_soc_write(codec, AB8500_ANCCONF5, val >> 8 & 0xff);
1050 snd_soc_write(codec, AB8500_ANCCONF6, val & 0xff);
1052 if (par == AB8500_ANC_FIR_COEFFS - 1 && bnk == 1)
1053 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1054 BIT(AB8500_ANCCONF1_ANCFIRUPDATE), 0);
1057 /* ANC IIR-coefficients configuration sequence */
1058 static void anc_iir(struct snd_soc_codec *codec, unsigned int bnk,
1059 unsigned int par, unsigned int val)
1063 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1064 BIT(AB8500_ANCCONF1_ANCIIRINIT),
1065 BIT(AB8500_ANCCONF1_ANCIIRINIT));
1066 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1067 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1068 BIT(AB8500_ANCCONF1_ANCIIRINIT), 0);
1069 usleep_range(AB8500_ANC_SM_DELAY, AB8500_ANC_SM_DELAY);
1071 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1072 BIT(AB8500_ANCCONF1_ANCIIRUPDATE),
1073 BIT(AB8500_ANCCONF1_ANCIIRUPDATE));
1075 } else if (par > 3) {
1076 snd_soc_write(codec, AB8500_ANCCONF7, 0);
1077 snd_soc_write(codec, AB8500_ANCCONF8, val >> 16 & 0xff);
1080 snd_soc_write(codec, AB8500_ANCCONF7, val >> 8 & 0xff);
1081 snd_soc_write(codec, AB8500_ANCCONF8, val & 0xff);
1083 if (par == AB8500_ANC_IIR_COEFFS - 1 && bnk == 1)
1084 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1085 BIT(AB8500_ANCCONF1_ANCIIRUPDATE), 0);
1088 /* ANC IIR-/FIR-coefficients configuration sequence */
1089 static void anc_configure(struct snd_soc_codec *codec,
1090 bool apply_fir, bool apply_iir)
1092 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1093 unsigned int bnk, par, val;
1095 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1098 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1099 BIT(AB8500_ANCCONF1_ENANC), 0);
1101 snd_soc_update_bits(codec, AB8500_ANCCONF1,
1102 BIT(AB8500_ANCCONF1_ENANC), BIT(AB8500_ANCCONF1_ENANC));
1105 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1106 for (par = 0; par < AB8500_ANC_FIR_COEFFS; par++) {
1107 val = snd_soc_read(codec,
1108 drvdata->anc_fir_values[par]);
1109 anc_fir(codec, bnk, par, val);
1113 for (bnk = 0; bnk < AB8500_NR_OF_ANC_COEFF_BANKS; bnk++)
1114 for (par = 0; par < AB8500_ANC_IIR_COEFFS; par++) {
1115 val = snd_soc_read(codec,
1116 drvdata->anc_iir_values[par]);
1117 anc_iir(codec, bnk, par, val);
1120 dev_dbg(codec->dev, "%s: Exit.\n", __func__);
1127 static int sid_status_control_get(struct snd_kcontrol *kcontrol,
1128 struct snd_ctl_elem_value *ucontrol)
1130 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1131 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1133 mutex_lock(&codec->mutex);
1134 ucontrol->value.integer.value[0] = drvdata->sid_status;
1135 mutex_unlock(&codec->mutex);
1140 /* Write sidetone FIR-coefficients configuration sequence */
1141 static int sid_status_control_put(struct snd_kcontrol *kcontrol,
1142 struct snd_ctl_elem_value *ucontrol)
1144 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1145 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1146 unsigned int param, sidconf, val;
1149 dev_dbg(codec->dev, "%s: Enter\n", __func__);
1151 if (ucontrol->value.integer.value[0] != SID_APPLY_FIR) {
1153 "%s: ERROR: This control supports '%s' only!\n",
1154 __func__, enum_sid_state[SID_APPLY_FIR]);
1158 mutex_lock(&codec->mutex);
1160 sidconf = snd_soc_read(codec, AB8500_SIDFIRCONF);
1161 if (((sidconf & BIT(AB8500_SIDFIRCONF_FIRSIDBUSY)) != 0)) {
1162 if ((sidconf & BIT(AB8500_SIDFIRCONF_ENFIRSIDS)) == 0) {
1163 dev_err(codec->dev, "%s: Sidetone busy while off!\n",
1172 snd_soc_write(codec, AB8500_SIDFIRADR, 0);
1174 for (param = 0; param < AB8500_SID_FIR_COEFFS; param++) {
1175 val = snd_soc_read(codec, drvdata->sid_fir_values[param]);
1176 snd_soc_write(codec, AB8500_SIDFIRCOEF1, val >> 8 & 0xff);
1177 snd_soc_write(codec, AB8500_SIDFIRCOEF2, val & 0xff);
1180 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1181 BIT(AB8500_SIDFIRADR_FIRSIDSET),
1182 BIT(AB8500_SIDFIRADR_FIRSIDSET));
1183 snd_soc_update_bits(codec, AB8500_SIDFIRADR,
1184 BIT(AB8500_SIDFIRADR_FIRSIDSET), 0);
1186 drvdata->sid_status = SID_FIR_CONFIGURED;
1189 mutex_unlock(&codec->mutex);
1191 dev_dbg(codec->dev, "%s: Exit\n", __func__);
1196 static int anc_status_control_get(struct snd_kcontrol *kcontrol,
1197 struct snd_ctl_elem_value *ucontrol)
1199 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1200 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1202 mutex_lock(&codec->mutex);
1203 ucontrol->value.integer.value[0] = drvdata->anc_status;
1204 mutex_unlock(&codec->mutex);
1209 static int anc_status_control_put(struct snd_kcontrol *kcontrol,
1210 struct snd_ctl_elem_value *ucontrol)
1212 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1213 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(codec->dev);
1214 struct device *dev = codec->dev;
1215 bool apply_fir, apply_iir;
1219 dev_dbg(dev, "%s: Enter.\n", __func__);
1221 mutex_lock(&drvdata->anc_lock);
1223 req = ucontrol->value.integer.value[0];
1224 if (req >= ARRAY_SIZE(enum_anc_state)) {
1228 if (req != ANC_APPLY_FIR_IIR && req != ANC_APPLY_FIR &&
1229 req != ANC_APPLY_IIR) {
1230 dev_err(dev, "%s: ERROR: Unsupported status to set '%s'!\n",
1231 __func__, enum_anc_state[req]);
1235 apply_fir = req == ANC_APPLY_FIR || req == ANC_APPLY_FIR_IIR;
1236 apply_iir = req == ANC_APPLY_IIR || req == ANC_APPLY_FIR_IIR;
1238 status = snd_soc_dapm_force_enable_pin(&codec->dapm,
1239 "ANC Configure Input");
1242 "%s: ERROR: Failed to enable power (status = %d)!\n",
1246 snd_soc_dapm_sync(&codec->dapm);
1248 mutex_lock(&codec->mutex);
1249 anc_configure(codec, apply_fir, apply_iir);
1250 mutex_unlock(&codec->mutex);
1253 if (drvdata->anc_status == ANC_IIR_CONFIGURED)
1254 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1255 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1256 drvdata->anc_status = ANC_FIR_CONFIGURED;
1259 if (drvdata->anc_status == ANC_FIR_CONFIGURED)
1260 drvdata->anc_status = ANC_FIR_IIR_CONFIGURED;
1261 else if (drvdata->anc_status != ANC_FIR_IIR_CONFIGURED)
1262 drvdata->anc_status = ANC_IIR_CONFIGURED;
1265 status = snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
1266 snd_soc_dapm_sync(&codec->dapm);
1269 mutex_unlock(&drvdata->anc_lock);
1272 dev_err(dev, "%s: Unable to configure ANC! (status = %d)\n",
1275 dev_dbg(dev, "%s: Exit.\n", __func__);
1277 return (status < 0) ? status : 1;
1280 static int filter_control_info(struct snd_kcontrol *kcontrol,
1281 struct snd_ctl_elem_info *uinfo)
1283 struct filter_control *fc =
1284 (struct filter_control *)kcontrol->private_value;
1286 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1287 uinfo->count = fc->count;
1288 uinfo->value.integer.min = fc->min;
1289 uinfo->value.integer.max = fc->max;
1294 static int filter_control_get(struct snd_kcontrol *kcontrol,
1295 struct snd_ctl_elem_value *ucontrol)
1297 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1298 struct filter_control *fc =
1299 (struct filter_control *)kcontrol->private_value;
1302 mutex_lock(&codec->mutex);
1303 for (i = 0; i < fc->count; i++)
1304 ucontrol->value.integer.value[i] = fc->value[i];
1305 mutex_unlock(&codec->mutex);
1310 static int filter_control_put(struct snd_kcontrol *kcontrol,
1311 struct snd_ctl_elem_value *ucontrol)
1313 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1314 struct filter_control *fc =
1315 (struct filter_control *)kcontrol->private_value;
1318 mutex_lock(&codec->mutex);
1319 for (i = 0; i < fc->count; i++)
1320 fc->value[i] = ucontrol->value.integer.value[i];
1321 mutex_unlock(&codec->mutex);
1327 * Controls - Non-DAPM ASoC
1330 static DECLARE_TLV_DB_SCALE(adx_dig_gain_tlv, -3200, 100, 1);
1333 static DECLARE_TLV_DB_SCALE(dax_dig_gain_tlv, -6300, 100, 1);
1336 static DECLARE_TLV_DB_SCALE(hs_ear_dig_gain_tlv, -100, 100, 1);
1339 static const unsigned int hs_gain_tlv[] = {
1340 TLV_DB_RANGE_HEAD(2),
1341 0, 3, TLV_DB_SCALE_ITEM(-3200, 400, 0),
1342 4, 15, TLV_DB_SCALE_ITEM(-1800, 200, 0),
1345 static DECLARE_TLV_DB_SCALE(mic_gain_tlv, 0, 100, 0);
1347 static DECLARE_TLV_DB_SCALE(lin_gain_tlv, -1000, 200, 0);
1349 static DECLARE_TLV_DB_SCALE(lin2hs_gain_tlv, -3800, 200, 1);
1352 static const char * const enum_hsfadspeed[] = {"2ms", "0.5ms", "10.6ms",
1354 static SOC_ENUM_SINGLE_DECL(soc_enum_hsfadspeed,
1355 AB8500_DIGMICCONF, AB8500_DIGMICCONF_HSFADSPEED, enum_hsfadspeed);
1357 static const char * const enum_envdetthre[] = {
1358 "250mV", "300mV", "350mV", "400mV",
1359 "450mV", "500mV", "550mV", "600mV",
1360 "650mV", "700mV", "750mV", "800mV",
1361 "850mV", "900mV", "950mV", "1.00V" };
1362 static SOC_ENUM_SINGLE_DECL(soc_enum_envdeththre,
1363 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETHTHRE, enum_envdetthre);
1364 static SOC_ENUM_SINGLE_DECL(soc_enum_envdetlthre,
1365 AB8500_ENVCPCONF, AB8500_ENVCPCONF_ENVDETLTHRE, enum_envdetthre);
1366 static const char * const enum_envdettime[] = {
1367 "26.6us", "53.2us", "106us", "213us",
1368 "426us", "851us", "1.70ms", "3.40ms",
1369 "6.81ms", "13.6ms", "27.2ms", "54.5ms",
1370 "109ms", "218ms", "436ms", "872ms" };
1371 static SOC_ENUM_SINGLE_DECL(soc_enum_envdettime,
1372 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETTIME, enum_envdettime);
1374 static const char * const enum_sinc31[] = {"Sinc 3", "Sinc 1"};
1375 static SOC_ENUM_SINGLE_DECL(soc_enum_hsesinc, AB8500_HSLEARDIGGAIN,
1376 AB8500_HSLEARDIGGAIN_HSSINC1, enum_sinc31);
1378 static const char * const enum_fadespeed[] = {"1ms", "4ms", "8ms", "16ms"};
1379 static SOC_ENUM_SINGLE_DECL(soc_enum_fadespeed, AB8500_HSRDIGGAIN,
1380 AB8500_HSRDIGGAIN_FADESPEED, enum_fadespeed);
1384 static const char * const enum_lowpow[] = {"Normal", "Low Power"};
1385 static SOC_ENUM_SINGLE_DECL(soc_enum_eardaclowpow, AB8500_ANACONF1,
1386 AB8500_ANACONF1_EARDACLOWPOW, enum_lowpow);
1387 static SOC_ENUM_SINGLE_DECL(soc_enum_eardrvlowpow, AB8500_ANACONF1,
1388 AB8500_ANACONF1_EARDRVLOWPOW, enum_lowpow);
1390 static const char * const enum_av_mode[] = {"Audio", "Voice"};
1391 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad12voice, AB8500_ADFILTCONF,
1392 AB8500_ADFILTCONF_AD1VOICE, AB8500_ADFILTCONF_AD2VOICE, enum_av_mode);
1393 static SOC_ENUM_DOUBLE_DECL(soc_enum_ad34voice, AB8500_ADFILTCONF,
1394 AB8500_ADFILTCONF_AD3VOICE, AB8500_ADFILTCONF_AD4VOICE, enum_av_mode);
1398 static SOC_ENUM_SINGLE_DECL(soc_enum_da12voice,
1399 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DA12VOICE,
1401 static SOC_ENUM_SINGLE_DECL(soc_enum_da34voice,
1402 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DA34VOICE,
1404 static SOC_ENUM_SINGLE_DECL(soc_enum_da56voice,
1405 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DA56VOICE,
1408 static const char * const enum_da2hslr[] = {"Sidetone", "Audio Path"};
1409 static SOC_ENUM_DOUBLE_DECL(soc_enum_da2hslr, AB8500_DIGMULTCONF1,
1410 AB8500_DIGMULTCONF1_DATOHSLEN,
1411 AB8500_DIGMULTCONF1_DATOHSREN, enum_da2hslr);
1413 static const char * const enum_sinc53[] = {"Sinc 5", "Sinc 3"};
1414 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic12sinc, AB8500_DMICFILTCONF,
1415 AB8500_DMICFILTCONF_DMIC1SINC3,
1416 AB8500_DMICFILTCONF_DMIC2SINC3, enum_sinc53);
1417 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic34sinc, AB8500_DMICFILTCONF,
1418 AB8500_DMICFILTCONF_DMIC3SINC3,
1419 AB8500_DMICFILTCONF_DMIC4SINC3, enum_sinc53);
1420 static SOC_ENUM_DOUBLE_DECL(soc_enum_dmic56sinc, AB8500_DMICFILTCONF,
1421 AB8500_DMICFILTCONF_DMIC5SINC3,
1422 AB8500_DMICFILTCONF_DMIC6SINC3, enum_sinc53);
1424 /* Digital interface - DA from slot mapping */
1425 static const char * const enum_da_from_slot_map[] = {"SLOT0",
1457 static SOC_ENUM_SINGLE_DECL(soc_enum_da1slotmap,
1458 AB8500_DASLOTCONF1, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1459 enum_da_from_slot_map);
1460 static SOC_ENUM_SINGLE_DECL(soc_enum_da2slotmap,
1461 AB8500_DASLOTCONF2, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1462 enum_da_from_slot_map);
1463 static SOC_ENUM_SINGLE_DECL(soc_enum_da3slotmap,
1464 AB8500_DASLOTCONF3, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1465 enum_da_from_slot_map);
1466 static SOC_ENUM_SINGLE_DECL(soc_enum_da4slotmap,
1467 AB8500_DASLOTCONF4, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1468 enum_da_from_slot_map);
1469 static SOC_ENUM_SINGLE_DECL(soc_enum_da5slotmap,
1470 AB8500_DASLOTCONF5, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1471 enum_da_from_slot_map);
1472 static SOC_ENUM_SINGLE_DECL(soc_enum_da6slotmap,
1473 AB8500_DASLOTCONF6, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1474 enum_da_from_slot_map);
1475 static SOC_ENUM_SINGLE_DECL(soc_enum_da7slotmap,
1476 AB8500_DASLOTCONF7, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1477 enum_da_from_slot_map);
1478 static SOC_ENUM_SINGLE_DECL(soc_enum_da8slotmap,
1479 AB8500_DASLOTCONF8, AB8500_DASLOTCONFX_SLTODAX_SHIFT,
1480 enum_da_from_slot_map);
1482 /* Digital interface - AD to slot mapping */
1483 static const char * const enum_ad_to_slot_map[] = {"AD_OUT1",
1499 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot0map,
1500 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_EVEN_SHIFT,
1501 enum_ad_to_slot_map);
1502 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot1map,
1503 AB8500_ADSLOTSEL1, AB8500_ADSLOTSELX_ODD_SHIFT,
1504 enum_ad_to_slot_map);
1505 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot2map,
1506 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_EVEN_SHIFT,
1507 enum_ad_to_slot_map);
1508 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot3map,
1509 AB8500_ADSLOTSEL2, AB8500_ADSLOTSELX_ODD_SHIFT,
1510 enum_ad_to_slot_map);
1511 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot4map,
1512 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_EVEN_SHIFT,
1513 enum_ad_to_slot_map);
1514 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot5map,
1515 AB8500_ADSLOTSEL3, AB8500_ADSLOTSELX_ODD_SHIFT,
1516 enum_ad_to_slot_map);
1517 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot6map,
1518 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_EVEN_SHIFT,
1519 enum_ad_to_slot_map);
1520 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot7map,
1521 AB8500_ADSLOTSEL4, AB8500_ADSLOTSELX_ODD_SHIFT,
1522 enum_ad_to_slot_map);
1523 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot8map,
1524 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_EVEN_SHIFT,
1525 enum_ad_to_slot_map);
1526 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot9map,
1527 AB8500_ADSLOTSEL5, AB8500_ADSLOTSELX_ODD_SHIFT,
1528 enum_ad_to_slot_map);
1529 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot10map,
1530 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_EVEN_SHIFT,
1531 enum_ad_to_slot_map);
1532 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot11map,
1533 AB8500_ADSLOTSEL6, AB8500_ADSLOTSELX_ODD_SHIFT,
1534 enum_ad_to_slot_map);
1535 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot12map,
1536 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_EVEN_SHIFT,
1537 enum_ad_to_slot_map);
1538 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot13map,
1539 AB8500_ADSLOTSEL7, AB8500_ADSLOTSELX_ODD_SHIFT,
1540 enum_ad_to_slot_map);
1541 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot14map,
1542 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_EVEN_SHIFT,
1543 enum_ad_to_slot_map);
1544 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot15map,
1545 AB8500_ADSLOTSEL8, AB8500_ADSLOTSELX_ODD_SHIFT,
1546 enum_ad_to_slot_map);
1547 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot16map,
1548 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_EVEN_SHIFT,
1549 enum_ad_to_slot_map);
1550 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot17map,
1551 AB8500_ADSLOTSEL9, AB8500_ADSLOTSELX_ODD_SHIFT,
1552 enum_ad_to_slot_map);
1553 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot18map,
1554 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_EVEN_SHIFT,
1555 enum_ad_to_slot_map);
1556 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot19map,
1557 AB8500_ADSLOTSEL10, AB8500_ADSLOTSELX_ODD_SHIFT,
1558 enum_ad_to_slot_map);
1559 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot20map,
1560 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_EVEN_SHIFT,
1561 enum_ad_to_slot_map);
1562 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot21map,
1563 AB8500_ADSLOTSEL11, AB8500_ADSLOTSELX_ODD_SHIFT,
1564 enum_ad_to_slot_map);
1565 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot22map,
1566 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_EVEN_SHIFT,
1567 enum_ad_to_slot_map);
1568 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot23map,
1569 AB8500_ADSLOTSEL12, AB8500_ADSLOTSELX_ODD_SHIFT,
1570 enum_ad_to_slot_map);
1571 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot24map,
1572 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_EVEN_SHIFT,
1573 enum_ad_to_slot_map);
1574 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot25map,
1575 AB8500_ADSLOTSEL13, AB8500_ADSLOTSELX_ODD_SHIFT,
1576 enum_ad_to_slot_map);
1577 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot26map,
1578 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_EVEN_SHIFT,
1579 enum_ad_to_slot_map);
1580 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot27map,
1581 AB8500_ADSLOTSEL14, AB8500_ADSLOTSELX_ODD_SHIFT,
1582 enum_ad_to_slot_map);
1583 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot28map,
1584 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_EVEN_SHIFT,
1585 enum_ad_to_slot_map);
1586 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot29map,
1587 AB8500_ADSLOTSEL15, AB8500_ADSLOTSELX_ODD_SHIFT,
1588 enum_ad_to_slot_map);
1589 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot30map,
1590 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_EVEN_SHIFT,
1591 enum_ad_to_slot_map);
1592 static SOC_ENUM_SINGLE_DECL(soc_enum_adslot31map,
1593 AB8500_ADSLOTSEL16, AB8500_ADSLOTSELX_ODD_SHIFT,
1594 enum_ad_to_slot_map);
1596 /* Digital interface - Burst mode */
1597 static const char * const enum_mask[] = {"Unmasked", "Masked"};
1598 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomask,
1599 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOMASK,
1601 static const char * const enum_bitclk0[] = {"19_2_MHz", "38_4_MHz"};
1602 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifo19m2,
1603 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFO19M2,
1605 static const char * const enum_slavemaster[] = {"Slave", "Master"};
1606 static SOC_ENUM_SINGLE_DECL(soc_enum_bfifomast,
1607 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOMAST_SHIFT,
1611 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_sidstate, enum_sid_state);
1614 static SOC_ENUM_SINGLE_EXT_DECL(soc_enum_ancstate, enum_anc_state);
1616 static struct snd_kcontrol_new ab8500_ctrls[] = {
1618 SOC_ENUM("Charge Pump High Threshold For Low Voltage",
1619 soc_enum_envdeththre),
1620 SOC_ENUM("Charge Pump Low Threshold For Low Voltage",
1621 soc_enum_envdetlthre),
1622 SOC_SINGLE("Charge Pump Envelope Detection Switch",
1623 AB8500_SIGENVCONF, AB8500_SIGENVCONF_ENVDETCPEN,
1625 SOC_ENUM("Charge Pump Envelope Detection Decay Time",
1626 soc_enum_envdettime),
1629 SOC_ENUM("Headset Mode", soc_enum_da12voice),
1630 SOC_SINGLE("Headset High Pass Switch",
1631 AB8500_ANACONF1, AB8500_ANACONF1_HSHPEN,
1633 SOC_SINGLE("Headset Low Power Switch",
1634 AB8500_ANACONF1, AB8500_ANACONF1_HSLOWPOW,
1636 SOC_SINGLE("Headset DAC Low Power Switch",
1637 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW1,
1639 SOC_SINGLE("Headset DAC Drv Low Power Switch",
1640 AB8500_ANACONF1, AB8500_ANACONF1_DACLOWPOW0,
1642 SOC_ENUM("Headset Fade Speed", soc_enum_hsfadspeed),
1643 SOC_ENUM("Headset Source", soc_enum_da2hslr),
1644 SOC_ENUM("Headset Filter", soc_enum_hsesinc),
1645 SOC_DOUBLE_R_TLV("Headset Master Volume",
1646 AB8500_DADIGGAIN1, AB8500_DADIGGAIN2,
1647 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1648 SOC_DOUBLE_R_TLV("Headset Digital Volume",
1649 AB8500_HSLEARDIGGAIN, AB8500_HSRDIGGAIN,
1650 0, AB8500_HSLEARDIGGAIN_HSLDGAIN_MAX, 1, hs_ear_dig_gain_tlv),
1651 SOC_DOUBLE_TLV("Headset Volume",
1653 AB8500_ANAGAIN3_HSLGAIN, AB8500_ANAGAIN3_HSRGAIN,
1654 AB8500_ANAGAIN3_HSXGAIN_MAX, 1, hs_gain_tlv),
1657 SOC_ENUM("Earpiece DAC Mode",
1658 soc_enum_eardaclowpow),
1659 SOC_ENUM("Earpiece DAC Drv Mode",
1660 soc_enum_eardrvlowpow),
1663 SOC_ENUM("HF Mode", soc_enum_da34voice),
1664 SOC_SINGLE("HF and Headset Swap Switch",
1665 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_SWAPDA12_34,
1667 SOC_DOUBLE("HF Low EMI Mode Switch",
1669 AB8500_CLASSDCONF1_HFLSWAPEN, AB8500_CLASSDCONF1_HFRSWAPEN,
1671 SOC_DOUBLE("HF FIR Bypass Switch",
1673 AB8500_CLASSDCONF2_FIRBYP0, AB8500_CLASSDCONF2_FIRBYP1,
1675 SOC_DOUBLE("HF High Volume Switch",
1677 AB8500_CLASSDCONF2_HIGHVOLEN0, AB8500_CLASSDCONF2_HIGHVOLEN1,
1679 SOC_SINGLE("HF L and R Bridge Switch",
1680 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLHF,
1682 SOC_DOUBLE_R_TLV("HF Master Volume",
1683 AB8500_DADIGGAIN3, AB8500_DADIGGAIN4,
1684 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1687 SOC_DOUBLE("Vibra High Volume Switch",
1689 AB8500_CLASSDCONF2_HIGHVOLEN2, AB8500_CLASSDCONF2_HIGHVOLEN3,
1691 SOC_DOUBLE("Vibra Low EMI Mode Switch",
1693 AB8500_CLASSDCONF1_VIB1SWAPEN, AB8500_CLASSDCONF1_VIB2SWAPEN,
1695 SOC_DOUBLE("Vibra FIR Bypass Switch",
1697 AB8500_CLASSDCONF2_FIRBYP2, AB8500_CLASSDCONF2_FIRBYP3,
1699 SOC_ENUM("Vibra Mode", soc_enum_da56voice),
1700 SOC_DOUBLE_R("Vibra PWM Duty Cycle N",
1701 AB8500_PWMGENCONF3, AB8500_PWMGENCONF5,
1702 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1703 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1704 SOC_DOUBLE_R("Vibra PWM Duty Cycle P",
1705 AB8500_PWMGENCONF2, AB8500_PWMGENCONF4,
1706 AB8500_PWMGENCONFX_PWMVIBXDUTCYC,
1707 AB8500_PWMGENCONFX_PWMVIBXDUTCYC_MAX, 0),
1708 SOC_SINGLE("Vibra 1 and 2 Bridge Switch",
1709 AB8500_CLASSDCONF1, AB8500_CLASSDCONF1_PARLVIB,
1711 SOC_DOUBLE_R_TLV("Vibra Master Volume",
1712 AB8500_DADIGGAIN5, AB8500_DADIGGAIN6,
1713 0, AB8500_DADIGGAINX_DAXGAIN_MAX, 1, dax_dig_gain_tlv),
1715 /* HandsFree, Vibra */
1716 SOC_SINGLE("ClassD High Pass Volume",
1717 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHHPGAIN,
1718 AB8500_CLASSDCONF3_DITHHPGAIN_MAX, 0),
1719 SOC_SINGLE("ClassD White Volume",
1720 AB8500_CLASSDCONF3, AB8500_CLASSDCONF3_DITHWGAIN,
1721 AB8500_CLASSDCONF3_DITHWGAIN_MAX, 0),
1723 /* Mic 1, Mic 2, LineIn */
1724 SOC_DOUBLE_R_TLV("Mic Master Volume",
1725 AB8500_ADDIGGAIN3, AB8500_ADDIGGAIN4,
1726 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1729 SOC_SINGLE_TLV("Mic 1",
1731 AB8500_ANAGAINX_MICXGAIN,
1732 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1733 SOC_SINGLE("Mic 1 Low Power Switch",
1734 AB8500_ANAGAIN1, AB8500_ANAGAINX_LOWPOWMICX,
1738 SOC_DOUBLE("Mic High Pass Switch",
1740 AB8500_ADFILTCONF_AD3NH, AB8500_ADFILTCONF_AD4NH,
1742 SOC_ENUM("Mic Mode", soc_enum_ad34voice),
1743 SOC_ENUM("Mic Filter", soc_enum_dmic34sinc),
1744 SOC_SINGLE_TLV("Mic 2",
1746 AB8500_ANAGAINX_MICXGAIN,
1747 AB8500_ANAGAINX_MICXGAIN_MAX, 0, mic_gain_tlv),
1748 SOC_SINGLE("Mic 2 Low Power Switch",
1749 AB8500_ANAGAIN2, AB8500_ANAGAINX_LOWPOWMICX,
1753 SOC_DOUBLE("LineIn High Pass Switch",
1755 AB8500_ADFILTCONF_AD1NH, AB8500_ADFILTCONF_AD2NH,
1757 SOC_ENUM("LineIn Filter", soc_enum_dmic12sinc),
1758 SOC_ENUM("LineIn Mode", soc_enum_ad12voice),
1759 SOC_DOUBLE_R_TLV("LineIn Master Volume",
1760 AB8500_ADDIGGAIN1, AB8500_ADDIGGAIN2,
1761 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1762 SOC_DOUBLE_TLV("LineIn",
1764 AB8500_ANAGAIN4_LINLGAIN, AB8500_ANAGAIN4_LINRGAIN,
1765 AB8500_ANAGAIN4_LINXGAIN_MAX, 0, lin_gain_tlv),
1766 SOC_DOUBLE_R_TLV("LineIn to Headset Volume",
1767 AB8500_DIGLINHSLGAIN, AB8500_DIGLINHSRGAIN,
1768 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN,
1769 AB8500_DIGLINHSXGAIN_LINTOHSXGAIN_MAX,
1770 1, lin2hs_gain_tlv),
1773 SOC_ENUM("DMic Filter", soc_enum_dmic56sinc),
1774 SOC_DOUBLE_R_TLV("DMic Master Volume",
1775 AB8500_ADDIGGAIN5, AB8500_ADDIGGAIN6,
1776 0, AB8500_ADDIGGAINX_ADXGAIN_MAX, 1, adx_dig_gain_tlv),
1779 SOC_ENUM("Digital Gain Fade Speed", soc_enum_fadespeed),
1781 /* Analog loopback */
1782 SOC_DOUBLE_R_TLV("Analog Loopback Volume",
1783 AB8500_ADDIGLOOPGAIN1, AB8500_ADDIGLOOPGAIN2,
1784 0, AB8500_ADDIGLOOPGAINX_ADXLBGAIN_MAX, 1, dax_dig_gain_tlv),
1786 /* Digital interface - DA from slot mapping */
1787 SOC_ENUM("Digital Interface DA 1 From Slot Map", soc_enum_da1slotmap),
1788 SOC_ENUM("Digital Interface DA 2 From Slot Map", soc_enum_da2slotmap),
1789 SOC_ENUM("Digital Interface DA 3 From Slot Map", soc_enum_da3slotmap),
1790 SOC_ENUM("Digital Interface DA 4 From Slot Map", soc_enum_da4slotmap),
1791 SOC_ENUM("Digital Interface DA 5 From Slot Map", soc_enum_da5slotmap),
1792 SOC_ENUM("Digital Interface DA 6 From Slot Map", soc_enum_da6slotmap),
1793 SOC_ENUM("Digital Interface DA 7 From Slot Map", soc_enum_da7slotmap),
1794 SOC_ENUM("Digital Interface DA 8 From Slot Map", soc_enum_da8slotmap),
1796 /* Digital interface - AD to slot mapping */
1797 SOC_ENUM("Digital Interface AD To Slot 0 Map", soc_enum_adslot0map),
1798 SOC_ENUM("Digital Interface AD To Slot 1 Map", soc_enum_adslot1map),
1799 SOC_ENUM("Digital Interface AD To Slot 2 Map", soc_enum_adslot2map),
1800 SOC_ENUM("Digital Interface AD To Slot 3 Map", soc_enum_adslot3map),
1801 SOC_ENUM("Digital Interface AD To Slot 4 Map", soc_enum_adslot4map),
1802 SOC_ENUM("Digital Interface AD To Slot 5 Map", soc_enum_adslot5map),
1803 SOC_ENUM("Digital Interface AD To Slot 6 Map", soc_enum_adslot6map),
1804 SOC_ENUM("Digital Interface AD To Slot 7 Map", soc_enum_adslot7map),
1805 SOC_ENUM("Digital Interface AD To Slot 8 Map", soc_enum_adslot8map),
1806 SOC_ENUM("Digital Interface AD To Slot 9 Map", soc_enum_adslot9map),
1807 SOC_ENUM("Digital Interface AD To Slot 10 Map", soc_enum_adslot10map),
1808 SOC_ENUM("Digital Interface AD To Slot 11 Map", soc_enum_adslot11map),
1809 SOC_ENUM("Digital Interface AD To Slot 12 Map", soc_enum_adslot12map),
1810 SOC_ENUM("Digital Interface AD To Slot 13 Map", soc_enum_adslot13map),
1811 SOC_ENUM("Digital Interface AD To Slot 14 Map", soc_enum_adslot14map),
1812 SOC_ENUM("Digital Interface AD To Slot 15 Map", soc_enum_adslot15map),
1813 SOC_ENUM("Digital Interface AD To Slot 16 Map", soc_enum_adslot16map),
1814 SOC_ENUM("Digital Interface AD To Slot 17 Map", soc_enum_adslot17map),
1815 SOC_ENUM("Digital Interface AD To Slot 18 Map", soc_enum_adslot18map),
1816 SOC_ENUM("Digital Interface AD To Slot 19 Map", soc_enum_adslot19map),
1817 SOC_ENUM("Digital Interface AD To Slot 20 Map", soc_enum_adslot20map),
1818 SOC_ENUM("Digital Interface AD To Slot 21 Map", soc_enum_adslot21map),
1819 SOC_ENUM("Digital Interface AD To Slot 22 Map", soc_enum_adslot22map),
1820 SOC_ENUM("Digital Interface AD To Slot 23 Map", soc_enum_adslot23map),
1821 SOC_ENUM("Digital Interface AD To Slot 24 Map", soc_enum_adslot24map),
1822 SOC_ENUM("Digital Interface AD To Slot 25 Map", soc_enum_adslot25map),
1823 SOC_ENUM("Digital Interface AD To Slot 26 Map", soc_enum_adslot26map),
1824 SOC_ENUM("Digital Interface AD To Slot 27 Map", soc_enum_adslot27map),
1825 SOC_ENUM("Digital Interface AD To Slot 28 Map", soc_enum_adslot28map),
1826 SOC_ENUM("Digital Interface AD To Slot 29 Map", soc_enum_adslot29map),
1827 SOC_ENUM("Digital Interface AD To Slot 30 Map", soc_enum_adslot30map),
1828 SOC_ENUM("Digital Interface AD To Slot 31 Map", soc_enum_adslot31map),
1830 /* Digital interface - Loopback */
1831 SOC_SINGLE("Digital Interface AD 1 Loopback Switch",
1832 AB8500_DASLOTCONF1, AB8500_DASLOTCONF1_DAI7TOADO1,
1834 SOC_SINGLE("Digital Interface AD 2 Loopback Switch",
1835 AB8500_DASLOTCONF2, AB8500_DASLOTCONF2_DAI8TOADO2,
1837 SOC_SINGLE("Digital Interface AD 3 Loopback Switch",
1838 AB8500_DASLOTCONF3, AB8500_DASLOTCONF3_DAI7TOADO3,
1840 SOC_SINGLE("Digital Interface AD 4 Loopback Switch",
1841 AB8500_DASLOTCONF4, AB8500_DASLOTCONF4_DAI8TOADO4,
1843 SOC_SINGLE("Digital Interface AD 5 Loopback Switch",
1844 AB8500_DASLOTCONF5, AB8500_DASLOTCONF5_DAI7TOADO5,
1846 SOC_SINGLE("Digital Interface AD 6 Loopback Switch",
1847 AB8500_DASLOTCONF6, AB8500_DASLOTCONF6_DAI8TOADO6,
1849 SOC_SINGLE("Digital Interface AD 7 Loopback Switch",
1850 AB8500_DASLOTCONF7, AB8500_DASLOTCONF7_DAI8TOADO7,
1852 SOC_SINGLE("Digital Interface AD 8 Loopback Switch",
1853 AB8500_DASLOTCONF8, AB8500_DASLOTCONF8_DAI7TOADO8,
1856 /* Digital interface - Burst FIFO */
1857 SOC_SINGLE("Digital Interface 0 FIFO Enable Switch",
1858 AB8500_DIGIFCONF3, AB8500_DIGIFCONF3_IF0BFIFOEN,
1860 SOC_ENUM("Burst FIFO Mask", soc_enum_bfifomask),
1861 SOC_ENUM("Burst FIFO Bit-clock Frequency", soc_enum_bfifo19m2),
1862 SOC_SINGLE("Burst FIFO Threshold",
1863 AB8500_FIFOCONF1, AB8500_FIFOCONF1_BFIFOINT_SHIFT,
1864 AB8500_FIFOCONF1_BFIFOINT_MAX, 0),
1865 SOC_SINGLE("Burst FIFO Length",
1866 AB8500_FIFOCONF2, AB8500_FIFOCONF2_BFIFOTX_SHIFT,
1867 AB8500_FIFOCONF2_BFIFOTX_MAX, 0),
1868 SOC_SINGLE("Burst FIFO EOS Extra Slots",
1869 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFOEXSL_SHIFT,
1870 AB8500_FIFOCONF3_BFIFOEXSL_MAX, 0),
1871 SOC_SINGLE("Burst FIFO FS Extra Bit-clocks",
1872 AB8500_FIFOCONF3, AB8500_FIFOCONF3_PREBITCLK0_SHIFT,
1873 AB8500_FIFOCONF3_PREBITCLK0_MAX, 0),
1874 SOC_ENUM("Burst FIFO Interface Mode", soc_enum_bfifomast),
1876 SOC_SINGLE("Burst FIFO Interface Switch",
1877 AB8500_FIFOCONF3, AB8500_FIFOCONF3_BFIFORUN_SHIFT,
1879 SOC_SINGLE("Burst FIFO Switch Frame Number",
1880 AB8500_FIFOCONF4, AB8500_FIFOCONF4_BFIFOFRAMSW_SHIFT,
1881 AB8500_FIFOCONF4_BFIFOFRAMSW_MAX, 0),
1882 SOC_SINGLE("Burst FIFO Wake Up Delay",
1883 AB8500_FIFOCONF5, AB8500_FIFOCONF5_BFIFOWAKEUP_SHIFT,
1884 AB8500_FIFOCONF5_BFIFOWAKEUP_MAX, 0),
1885 SOC_SINGLE("Burst FIFO Samples In FIFO",
1886 AB8500_FIFOCONF6, AB8500_FIFOCONF6_BFIFOSAMPLE_SHIFT,
1887 AB8500_FIFOCONF6_BFIFOSAMPLE_MAX, 0),
1890 SOC_ENUM_EXT("ANC Status", soc_enum_ancstate,
1891 anc_status_control_get, anc_status_control_put),
1892 SOC_SINGLE_XR_SX("ANC Warp Delay Shift",
1893 AB8500_ANCCONF2, 1, AB8500_ANCCONF2_SHIFT,
1894 AB8500_ANCCONF2_MIN, AB8500_ANCCONF2_MAX, 0),
1895 SOC_SINGLE_XR_SX("ANC FIR Output Shift",
1896 AB8500_ANCCONF3, 1, AB8500_ANCCONF3_SHIFT,
1897 AB8500_ANCCONF3_MIN, AB8500_ANCCONF3_MAX, 0),
1898 SOC_SINGLE_XR_SX("ANC IIR Output Shift",
1899 AB8500_ANCCONF4, 1, AB8500_ANCCONF4_SHIFT,
1900 AB8500_ANCCONF4_MIN, AB8500_ANCCONF4_MAX, 0),
1901 SOC_SINGLE_XR_SX("ANC Warp Delay",
1902 AB8500_ANCCONF9, 2, AB8500_ANC_WARP_DELAY_SHIFT,
1903 AB8500_ANC_WARP_DELAY_MIN, AB8500_ANC_WARP_DELAY_MAX, 0),
1906 SOC_ENUM_EXT("Sidetone Status", soc_enum_sidstate,
1907 sid_status_control_get, sid_status_control_put),
1908 SOC_SINGLE_STROBE("Sidetone Reset",
1909 AB8500_SIDFIRADR, AB8500_SIDFIRADR_FIRSIDSET, 0),
1912 static struct snd_kcontrol_new ab8500_filter_controls[] = {
1913 AB8500_FILTER_CONTROL("ANC FIR Coefficients", AB8500_ANC_FIR_COEFFS,
1914 AB8500_ANC_FIR_COEFF_MIN, AB8500_ANC_FIR_COEFF_MAX),
1915 AB8500_FILTER_CONTROL("ANC IIR Coefficients", AB8500_ANC_IIR_COEFFS,
1916 AB8500_ANC_IIR_COEFF_MIN, AB8500_ANC_IIR_COEFF_MAX),
1917 AB8500_FILTER_CONTROL("Sidetone FIR Coefficients",
1918 AB8500_SID_FIR_COEFFS, AB8500_SID_FIR_COEFF_MIN,
1919 AB8500_SID_FIR_COEFF_MAX)
1921 enum ab8500_filter {
1922 AB8500_FILTER_ANC_FIR = 0,
1923 AB8500_FILTER_ANC_IIR = 1,
1924 AB8500_FILTER_SID_FIR = 2,
1928 * Extended interface for codec-driver
1931 static int ab8500_audio_init_audioblock(struct snd_soc_codec *codec)
1935 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1937 /* Reset audio-registers and disable 32kHz-clock output 2 */
1938 status = ab8500_sysctrl_write(AB8500_STW4500CTRL3,
1939 AB8500_STW4500CTRL3_CLK32KOUT2DIS |
1940 AB8500_STW4500CTRL3_RESETAUDN,
1941 AB8500_STW4500CTRL3_RESETAUDN);
1948 static int ab8500_audio_setup_mics(struct snd_soc_codec *codec,
1949 struct amic_settings *amics)
1954 const struct snd_soc_dapm_route *route;
1956 dev_dbg(codec->dev, "%s: Enter.\n", __func__);
1958 /* Set DMic-clocks to outputs */
1959 status = abx500_get_register_interruptible(codec->dev, (u8)AB8500_MISC,
1960 (u8)AB8500_GPIO_DIR4_REG,
1964 value = value8 | GPIO27_DIR_OUTPUT | GPIO29_DIR_OUTPUT |
1966 status = abx500_set_register_interruptible(codec->dev,
1968 (u8)AB8500_GPIO_DIR4_REG,
1973 /* Attach regulators to AMic DAPM-paths */
1974 dev_dbg(codec->dev, "%s: Mic 1a regulator: %s\n", __func__,
1975 amic_micbias_str(amics->mic1a_micbias));
1976 route = &ab8500_dapm_routes_mic1a_vamicx[amics->mic1a_micbias];
1977 status = snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1978 dev_dbg(codec->dev, "%s: Mic 1b regulator: %s\n", __func__,
1979 amic_micbias_str(amics->mic1b_micbias));
1980 route = &ab8500_dapm_routes_mic1b_vamicx[amics->mic1b_micbias];
1981 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1982 dev_dbg(codec->dev, "%s: Mic 2 regulator: %s\n", __func__,
1983 amic_micbias_str(amics->mic2_micbias));
1984 route = &ab8500_dapm_routes_mic2_vamicx[amics->mic2_micbias];
1985 status |= snd_soc_dapm_add_routes(&codec->dapm, route, 1);
1988 "%s: Failed to add AMic-regulator DAPM-routes (%d).\n",
1993 /* Set AMic-configuration */
1994 dev_dbg(codec->dev, "%s: Mic 1 mic-type: %s\n", __func__,
1995 amic_type_str(amics->mic1_type));
1996 snd_soc_update_bits(codec, AB8500_ANAGAIN1, AB8500_ANAGAINX_ENSEMICX,
1997 amics->mic1_type == AMIC_TYPE_DIFFERENTIAL ?
1998 0 : AB8500_ANAGAINX_ENSEMICX);
1999 dev_dbg(codec->dev, "%s: Mic 2 mic-type: %s\n", __func__,
2000 amic_type_str(amics->mic2_type));
2001 snd_soc_update_bits(codec, AB8500_ANAGAIN2, AB8500_ANAGAINX_ENSEMICX,
2002 amics->mic2_type == AMIC_TYPE_DIFFERENTIAL ?
2003 0 : AB8500_ANAGAINX_ENSEMICX);
2007 EXPORT_SYMBOL_GPL(ab8500_audio_setup_mics);
2009 static int ab8500_audio_set_ear_cmv(struct snd_soc_codec *codec,
2010 enum ear_cm_voltage ear_cmv)
2029 "%s: Unknown earpiece CM-voltage (%d)!\n",
2030 __func__, (int)ear_cmv);
2033 dev_dbg(codec->dev, "%s: Earpiece CM-voltage: %s\n", __func__,
2035 snd_soc_update_bits(codec, AB8500_ANACONF1, AB8500_ANACONF1_EARSELCM,
2040 EXPORT_SYMBOL_GPL(ab8500_audio_set_ear_cmv);
2042 static int ab8500_audio_set_bit_delay(struct snd_soc_dai *dai,
2045 unsigned int mask, val;
2046 struct snd_soc_codec *codec = dai->codec;
2048 mask = BIT(AB8500_DIGIFCONF2_IF0DEL);
2055 val |= BIT(AB8500_DIGIFCONF2_IF0DEL);
2058 dev_err(dai->codec->dev,
2059 "%s: ERROR: Unsupported bit-delay (0x%x)!\n",
2064 dev_dbg(dai->codec->dev, "%s: IF0 Bit-delay: %d bits.\n",
2066 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2071 /* Gates clocking according format mask */
2072 static int ab8500_codec_set_dai_clock_gate(struct snd_soc_codec *codec,
2078 mask = BIT(AB8500_DIGIFCONF1_ENMASTGEN) |
2079 BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2081 val = BIT(AB8500_DIGIFCONF1_ENMASTGEN);
2083 switch (fmt & SND_SOC_DAIFMT_CLOCK_MASK) {
2084 case SND_SOC_DAIFMT_CONT: /* continuous clock */
2085 dev_dbg(codec->dev, "%s: IF0 Clock is continuous.\n",
2087 val |= BIT(AB8500_DIGIFCONF1_ENFSBITCLK0);
2089 case SND_SOC_DAIFMT_GATED: /* clock is gated */
2090 dev_dbg(codec->dev, "%s: IF0 Clock is gated.\n",
2095 "%s: ERROR: Unsupported clock mask (0x%x)!\n",
2096 __func__, fmt & SND_SOC_DAIFMT_CLOCK_MASK);
2100 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2105 static int ab8500_codec_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2109 struct snd_soc_codec *codec = dai->codec;
2112 dev_dbg(codec->dev, "%s: Enter (fmt = 0x%x)\n", __func__, fmt);
2114 mask = BIT(AB8500_DIGIFCONF3_IF1DATOIF0AD) |
2115 BIT(AB8500_DIGIFCONF3_IF1CLKTOIF0CLK) |
2116 BIT(AB8500_DIGIFCONF3_IF0BFIFOEN) |
2117 BIT(AB8500_DIGIFCONF3_IF0MASTER);
2120 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2121 case SND_SOC_DAIFMT_CBM_CFM: /* codec clk & FRM master */
2122 dev_dbg(dai->codec->dev,
2123 "%s: IF0 Master-mode: AB8500 master.\n", __func__);
2124 val |= BIT(AB8500_DIGIFCONF3_IF0MASTER);
2126 case SND_SOC_DAIFMT_CBS_CFS: /* codec clk & FRM slave */
2127 dev_dbg(dai->codec->dev,
2128 "%s: IF0 Master-mode: AB8500 slave.\n", __func__);
2130 case SND_SOC_DAIFMT_CBS_CFM: /* codec clk slave & FRM master */
2131 case SND_SOC_DAIFMT_CBM_CFS: /* codec clk master & frame slave */
2132 dev_err(dai->codec->dev,
2133 "%s: ERROR: The device is either a master or a slave.\n",
2136 dev_err(dai->codec->dev,
2137 "%s: ERROR: Unsupporter master mask 0x%x\n",
2138 __func__, fmt & SND_SOC_DAIFMT_MASTER_MASK);
2143 snd_soc_update_bits(codec, AB8500_DIGIFCONF3, mask, val);
2145 /* Set clock gating */
2146 status = ab8500_codec_set_dai_clock_gate(codec, fmt);
2148 dev_err(dai->codec->dev,
2149 "%s: ERROR: Failed to set clock gate (%d).\n",
2154 /* Setting data transfer format */
2156 mask = BIT(AB8500_DIGIFCONF2_IF0FORMAT0) |
2157 BIT(AB8500_DIGIFCONF2_IF0FORMAT1) |
2158 BIT(AB8500_DIGIFCONF2_FSYNC0P) |
2159 BIT(AB8500_DIGIFCONF2_BITCLK0P);
2162 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2163 case SND_SOC_DAIFMT_I2S: /* I2S mode */
2164 dev_dbg(dai->codec->dev, "%s: IF0 Protocol: I2S\n", __func__);
2165 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT1);
2166 ab8500_audio_set_bit_delay(dai, 0);
2169 case SND_SOC_DAIFMT_DSP_A: /* L data MSB after FRM LRC */
2170 dev_dbg(dai->codec->dev,
2171 "%s: IF0 Protocol: DSP A (TDM)\n", __func__);
2172 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2173 ab8500_audio_set_bit_delay(dai, 1);
2176 case SND_SOC_DAIFMT_DSP_B: /* L data MSB during FRM LRC */
2177 dev_dbg(dai->codec->dev,
2178 "%s: IF0 Protocol: DSP B (TDM)\n", __func__);
2179 val |= BIT(AB8500_DIGIFCONF2_IF0FORMAT0);
2180 ab8500_audio_set_bit_delay(dai, 0);
2184 dev_err(dai->codec->dev,
2185 "%s: ERROR: Unsupported format (0x%x)!\n",
2186 __func__, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
2190 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2191 case SND_SOC_DAIFMT_NB_NF: /* normal bit clock + frame */
2192 dev_dbg(dai->codec->dev,
2193 "%s: IF0: Normal bit clock, normal frame\n",
2196 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */
2197 dev_dbg(dai->codec->dev,
2198 "%s: IF0: Normal bit clock, inverted frame\n",
2200 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2202 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */
2203 dev_dbg(dai->codec->dev,
2204 "%s: IF0: Inverted bit clock, normal frame\n",
2206 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2208 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */
2209 dev_dbg(dai->codec->dev,
2210 "%s: IF0: Inverted bit clock, inverted frame\n",
2212 val |= BIT(AB8500_DIGIFCONF2_FSYNC0P);
2213 val |= BIT(AB8500_DIGIFCONF2_BITCLK0P);
2216 dev_err(dai->codec->dev,
2217 "%s: ERROR: Unsupported INV mask 0x%x\n",
2218 __func__, fmt & SND_SOC_DAIFMT_INV_MASK);
2222 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2227 static int ab8500_codec_set_dai_tdm_slot(struct snd_soc_dai *dai,
2228 unsigned int tx_mask, unsigned int rx_mask,
2229 int slots, int slot_width)
2231 struct snd_soc_codec *codec = dai->codec;
2232 unsigned int val, mask, slot, slots_active;
2234 mask = BIT(AB8500_DIGIFCONF2_IF0WL0) |
2235 BIT(AB8500_DIGIFCONF2_IF0WL1);
2238 switch (slot_width) {
2242 val |= BIT(AB8500_DIGIFCONF2_IF0WL0);
2245 val |= BIT(AB8500_DIGIFCONF2_IF0WL1);
2248 val |= BIT(AB8500_DIGIFCONF2_IF0WL1) |
2249 BIT(AB8500_DIGIFCONF2_IF0WL0);
2252 dev_err(dai->codec->dev, "%s: Unsupported slot-width 0x%x\n",
2253 __func__, slot_width);
2257 dev_dbg(dai->codec->dev, "%s: IF0 slot-width: %d bits.\n",
2258 __func__, slot_width);
2259 snd_soc_update_bits(codec, AB8500_DIGIFCONF2, mask, val);
2261 /* Setup TDM clocking according to slot count */
2262 dev_dbg(dai->codec->dev, "%s: Slots, total: %d\n", __func__, slots);
2263 mask = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2264 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2267 val = AB8500_MASK_NONE;
2270 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0);
2273 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2276 val = BIT(AB8500_DIGIFCONF1_IF0BITCLKOS0) |
2277 BIT(AB8500_DIGIFCONF1_IF0BITCLKOS1);
2280 dev_err(dai->codec->dev,
2281 "%s: ERROR: Unsupported number of slots (%d)!\n",
2285 snd_soc_update_bits(codec, AB8500_DIGIFCONF1, mask, val);
2287 /* Setup TDM DA according to active tx slots */
2289 if (tx_mask & ~0xff)
2292 mask = AB8500_DASLOTCONFX_SLTODAX_MASK;
2293 tx_mask = tx_mask << AB8500_DA_DATA0_OFFSET;
2294 slots_active = hweight32(tx_mask);
2296 dev_dbg(dai->codec->dev, "%s: Slots, active, TX: %d\n", __func__,
2299 switch (slots_active) {
2303 slot = find_first_bit((unsigned long *)&tx_mask, 32);
2304 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2305 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2306 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2307 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2310 slot = find_first_bit((unsigned long *)&tx_mask, 32);
2311 snd_soc_update_bits(codec, AB8500_DASLOTCONF1, mask, slot);
2312 snd_soc_update_bits(codec, AB8500_DASLOTCONF3, mask, slot);
2313 slot = find_next_bit((unsigned long *)&tx_mask, 32, slot + 1);
2314 snd_soc_update_bits(codec, AB8500_DASLOTCONF2, mask, slot);
2315 snd_soc_update_bits(codec, AB8500_DASLOTCONF4, mask, slot);
2318 dev_dbg(dai->codec->dev,
2319 "%s: In 8-channel mode DA-from-slot mapping is set manually.",
2323 dev_err(dai->codec->dev,
2324 "%s: Unsupported number of active TX-slots (%d)!\n",
2325 __func__, slots_active);
2329 /* Setup TDM AD according to active RX-slots */
2331 if (rx_mask & ~0xff)
2334 rx_mask = rx_mask << AB8500_AD_DATA0_OFFSET;
2335 slots_active = hweight32(rx_mask);
2337 dev_dbg(dai->codec->dev, "%s: Slots, active, RX: %d\n", __func__,
2340 switch (slots_active) {
2344 slot = find_first_bit((unsigned long *)&rx_mask, 32);
2345 snd_soc_update_bits(codec, AB8500_ADSLOTSEL(slot),
2346 AB8500_MASK_SLOT(slot),
2347 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2350 slot = find_first_bit((unsigned long *)&rx_mask, 32);
2351 snd_soc_update_bits(codec,
2352 AB8500_ADSLOTSEL(slot),
2353 AB8500_MASK_SLOT(slot),
2354 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT3, slot));
2355 slot = find_next_bit((unsigned long *)&rx_mask, 32, slot + 1);
2356 snd_soc_update_bits(codec,
2357 AB8500_ADSLOTSEL(slot),
2358 AB8500_MASK_SLOT(slot),
2359 AB8500_ADSLOTSELX_AD_OUT_TO_SLOT(AB8500_AD_OUT2, slot));
2362 dev_dbg(dai->codec->dev,
2363 "%s: In 8-channel mode AD-to-slot mapping is set manually.",
2367 dev_err(dai->codec->dev,
2368 "%s: Unsupported number of active RX-slots (%d)!\n",
2369 __func__, slots_active);
2376 static const struct snd_soc_dai_ops ab8500_codec_ops = {
2377 .set_fmt = ab8500_codec_set_dai_fmt,
2378 .set_tdm_slot = ab8500_codec_set_dai_tdm_slot,
2381 static struct snd_soc_dai_driver ab8500_codec_dai[] = {
2383 .name = "ab8500-codec-dai.0",
2386 .stream_name = "ab8500_0p",
2389 .rates = AB8500_SUPPORTED_RATE,
2390 .formats = AB8500_SUPPORTED_FMT,
2392 .ops = &ab8500_codec_ops,
2393 .symmetric_rates = 1
2396 .name = "ab8500-codec-dai.1",
2399 .stream_name = "ab8500_0c",
2402 .rates = AB8500_SUPPORTED_RATE,
2403 .formats = AB8500_SUPPORTED_FMT,
2405 .ops = &ab8500_codec_ops,
2406 .symmetric_rates = 1
2410 static void ab8500_codec_of_probe(struct device *dev, struct device_node *np,
2411 struct ab8500_codec_platform_data *codec)
2415 if (of_get_property(np, "stericsson,amic1-type-single-ended", NULL))
2416 codec->amics.mic1_type = AMIC_TYPE_SINGLE_ENDED;
2418 codec->amics.mic1_type = AMIC_TYPE_DIFFERENTIAL;
2420 if (of_get_property(np, "stericsson,amic2-type-single-ended", NULL))
2421 codec->amics.mic2_type = AMIC_TYPE_SINGLE_ENDED;
2423 codec->amics.mic2_type = AMIC_TYPE_DIFFERENTIAL;
2425 /* Has a non-standard Vamic been requested? */
2426 if (of_get_property(np, "stericsson,amic1a-bias-vamic2", NULL))
2427 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC2;
2429 codec->amics.mic1a_micbias = AMIC_MICBIAS_VAMIC1;
2431 if (of_get_property(np, "stericsson,amic1b-bias-vamic2", NULL))
2432 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC2;
2434 codec->amics.mic1b_micbias = AMIC_MICBIAS_VAMIC1;
2436 if (of_get_property(np, "stericsson,amic2-bias-vamic1", NULL))
2437 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC1;
2439 codec->amics.mic2_micbias = AMIC_MICBIAS_VAMIC2;
2441 if (!of_property_read_u32(np, "stericsson,earpeice-cmv", &value)) {
2444 codec->ear_cmv = EAR_CMV_0_95V;
2447 codec->ear_cmv = EAR_CMV_1_10V;
2450 codec->ear_cmv = EAR_CMV_1_27V;
2453 codec->ear_cmv = EAR_CMV_1_58V;
2456 codec->ear_cmv = EAR_CMV_UNKNOWN;
2457 dev_err(dev, "Unsuitable earpiece voltage found in DT\n");
2460 dev_warn(dev, "No earpiece voltage found in DT - using default\n");
2461 codec->ear_cmv = EAR_CMV_0_95V;
2465 static int ab8500_codec_probe(struct snd_soc_codec *codec)
2467 struct device *dev = codec->dev;
2468 struct device_node *np = dev->of_node;
2469 struct ab8500_codec_drvdata *drvdata = dev_get_drvdata(dev);
2470 struct ab8500_platform_data *pdata;
2471 struct filter_control *fc;
2474 dev_dbg(dev, "%s: Enter.\n", __func__);
2476 snd_soc_codec_set_cache_io(codec, 0, 0, SND_SOC_REGMAP);
2478 /* Setup AB8500 according to board-settings */
2479 pdata = dev_get_platdata(dev->parent);
2481 codec->control_data = drvdata->regmap;
2485 pdata = devm_kzalloc(dev,
2486 sizeof(struct ab8500_platform_data),
2489 if (pdata && !pdata->codec)
2492 sizeof(struct ab8500_codec_platform_data),
2495 if (!(pdata && pdata->codec))
2498 ab8500_codec_of_probe(dev, np, pdata->codec);
2501 if (!(pdata && pdata->codec)) {
2502 dev_err(dev, "No codec platform data or DT found\n");
2507 status = ab8500_audio_setup_mics(codec, &pdata->codec->amics);
2509 pr_err("%s: Failed to setup mics (%d)!\n", __func__, status);
2512 status = ab8500_audio_set_ear_cmv(codec, pdata->codec->ear_cmv);
2514 pr_err("%s: Failed to set earpiece CM-voltage (%d)!\n",
2519 status = ab8500_audio_init_audioblock(codec);
2521 dev_err(dev, "%s: failed to init audio-block (%d)!\n",
2526 /* Override HW-defaults */
2527 snd_soc_write(codec, AB8500_ANACONF5,
2528 BIT(AB8500_ANACONF5_HSAUTOEN));
2529 snd_soc_write(codec, AB8500_SHORTCIRCONF,
2530 BIT(AB8500_SHORTCIRCONF_HSZCDDIS));
2532 /* Add filter controls */
2533 status = snd_soc_add_codec_controls(codec, ab8500_filter_controls,
2534 ARRAY_SIZE(ab8500_filter_controls));
2537 "%s: failed to add ab8500 filter controls (%d).\n",
2541 fc = (struct filter_control *)
2542 &ab8500_filter_controls[AB8500_FILTER_ANC_FIR].private_value;
2543 drvdata->anc_fir_values = (long *)fc->value;
2544 fc = (struct filter_control *)
2545 &ab8500_filter_controls[AB8500_FILTER_ANC_IIR].private_value;
2546 drvdata->anc_iir_values = (long *)fc->value;
2547 fc = (struct filter_control *)
2548 &ab8500_filter_controls[AB8500_FILTER_SID_FIR].private_value;
2549 drvdata->sid_fir_values = (long *)fc->value;
2551 (void)snd_soc_dapm_disable_pin(&codec->dapm, "ANC Configure Input");
2553 mutex_init(&drvdata->anc_lock);
2558 static struct snd_soc_codec_driver ab8500_codec_driver = {
2559 .probe = ab8500_codec_probe,
2560 .controls = ab8500_ctrls,
2561 .num_controls = ARRAY_SIZE(ab8500_ctrls),
2562 .dapm_widgets = ab8500_dapm_widgets,
2563 .num_dapm_widgets = ARRAY_SIZE(ab8500_dapm_widgets),
2564 .dapm_routes = ab8500_dapm_routes,
2565 .num_dapm_routes = ARRAY_SIZE(ab8500_dapm_routes),
2568 static int ab8500_codec_driver_probe(struct platform_device *pdev)
2571 struct ab8500_codec_drvdata *drvdata;
2573 dev_dbg(&pdev->dev, "%s: Enter.\n", __func__);
2575 /* Create driver private-data struct */
2576 drvdata = devm_kzalloc(&pdev->dev, sizeof(struct ab8500_codec_drvdata),
2578 drvdata->sid_status = SID_UNCONFIGURED;
2579 drvdata->anc_status = ANC_UNCONFIGURED;
2580 dev_set_drvdata(&pdev->dev, drvdata);
2582 drvdata->regmap = devm_regmap_init(&pdev->dev, NULL, &pdev->dev,
2583 &ab8500_codec_regmap);
2584 if (IS_ERR(drvdata->regmap)) {
2585 status = PTR_ERR(drvdata->regmap);
2586 dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
2591 dev_dbg(&pdev->dev, "%s: Register codec.\n", __func__);
2592 status = snd_soc_register_codec(&pdev->dev, &ab8500_codec_driver,
2594 ARRAY_SIZE(ab8500_codec_dai));
2597 "%s: Error: Failed to register codec (%d).\n",
2603 static int ab8500_codec_driver_remove(struct platform_device *pdev)
2605 dev_dbg(&pdev->dev, "%s Enter.\n", __func__);
2607 snd_soc_unregister_codec(&pdev->dev);
2612 static struct platform_driver ab8500_codec_platform_driver = {
2614 .name = "ab8500-codec",
2615 .owner = THIS_MODULE,
2617 .probe = ab8500_codec_driver_probe,
2618 .remove = ab8500_codec_driver_remove,
2622 module_platform_driver(ab8500_codec_platform_driver);
2624 MODULE_LICENSE("GPL v2");