1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/sound/soc/ep93xx-i2s.c
6 * Copyright (C) 2010 Ryan Mallon
8 * Based on the original driver by:
9 * Copyright (C) 2007 Chase Douglas <chasedouglas@gmail>
10 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/slab.h>
16 #include <linux/clk.h>
20 #include <sound/core.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm.h>
23 #include <sound/pcm_params.h>
24 #include <sound/initval.h>
25 #include <sound/soc.h>
27 #include <linux/platform_data/dma-ep93xx.h>
28 #include <linux/soc/cirrus/ep93xx.h>
30 #include "ep93xx-pcm.h"
32 #define EP93XX_I2S_TXCLKCFG 0x00
33 #define EP93XX_I2S_RXCLKCFG 0x04
34 #define EP93XX_I2S_GLSTS 0x08
35 #define EP93XX_I2S_GLCTRL 0x0C
37 #define EP93XX_I2S_I2STX0LFT 0x10
38 #define EP93XX_I2S_I2STX0RT 0x14
40 #define EP93XX_I2S_TXLINCTRLDATA 0x28
41 #define EP93XX_I2S_TXCTRL 0x2C
42 #define EP93XX_I2S_TXWRDLEN 0x30
43 #define EP93XX_I2S_TX0EN 0x34
45 #define EP93XX_I2S_RXLINCTRLDATA 0x58
46 #define EP93XX_I2S_RXCTRL 0x5C
47 #define EP93XX_I2S_RXWRDLEN 0x60
48 #define EP93XX_I2S_RX0EN 0x64
50 #define EP93XX_I2S_WRDLEN_16 (0 << 0)
51 #define EP93XX_I2S_WRDLEN_24 (1 << 0)
52 #define EP93XX_I2S_WRDLEN_32 (2 << 0)
54 #define EP93XX_I2S_RXLINCTRLDATA_R_JUST BIT(1) /* Right justify */
56 #define EP93XX_I2S_TXLINCTRLDATA_R_JUST BIT(2) /* Right justify */
59 * Transmit empty interrupt level select:
60 * 0 - Generate interrupt when FIFO is half empty
61 * 1 - Generate interrupt when FIFO is empty
63 #define EP93XX_I2S_TXCTRL_TXEMPTY_LVL BIT(0)
64 #define EP93XX_I2S_TXCTRL_TXUFIE BIT(1) /* Transmit interrupt enable */
66 #define EP93XX_I2S_CLKCFG_LRS (1 << 0) /* lrclk polarity */
67 #define EP93XX_I2S_CLKCFG_CKP (1 << 1) /* Bit clock polarity */
68 #define EP93XX_I2S_CLKCFG_REL (1 << 2) /* First bit transition */
69 #define EP93XX_I2S_CLKCFG_MASTER (1 << 3) /* Master mode */
70 #define EP93XX_I2S_CLKCFG_NBCG (1 << 4) /* Not bit clock gating */
72 #define EP93XX_I2S_GLSTS_TX0_FIFO_FULL BIT(12)
74 struct ep93xx_i2s_info {
79 struct snd_dmaengine_dai_dma_data dma_params_rx;
80 struct snd_dmaengine_dai_dma_data dma_params_tx;
83 static struct ep93xx_dma_data ep93xx_i2s_dma_data[] = {
84 [SNDRV_PCM_STREAM_PLAYBACK] = {
85 .name = "i2s-pcm-out",
86 .port = EP93XX_DMA_I2S1,
87 .direction = DMA_MEM_TO_DEV,
89 [SNDRV_PCM_STREAM_CAPTURE] = {
91 .port = EP93XX_DMA_I2S1,
92 .direction = DMA_DEV_TO_MEM,
96 static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
97 unsigned reg, unsigned val)
99 __raw_writel(val, info->regs + reg);
102 static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
105 return __raw_readl(info->regs + reg);
108 static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
112 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
113 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
115 clk_prepare_enable(info->mclk);
116 clk_prepare_enable(info->sclk);
117 clk_prepare_enable(info->lrclk);
120 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
124 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
125 base_reg = EP93XX_I2S_TX0EN;
127 base_reg = EP93XX_I2S_RX0EN;
128 ep93xx_i2s_write_reg(info, base_reg, 1);
130 /* Enable TX IRQs (FIFO empty or underflow) */
131 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
132 stream == SNDRV_PCM_STREAM_PLAYBACK)
133 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL,
134 EP93XX_I2S_TXCTRL_TXEMPTY_LVL |
135 EP93XX_I2S_TXCTRL_TXUFIE);
138 static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
143 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG) &&
144 stream == SNDRV_PCM_STREAM_PLAYBACK)
145 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCTRL, 0);
148 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
149 base_reg = EP93XX_I2S_TX0EN;
151 base_reg = EP93XX_I2S_RX0EN;
152 ep93xx_i2s_write_reg(info, base_reg, 0);
154 if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
155 (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
157 ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
160 clk_disable_unprepare(info->lrclk);
161 clk_disable_unprepare(info->sclk);
162 clk_disable_unprepare(info->mclk);
167 * According to documentation I2S controller can handle underflow conditions
168 * just fine, but in reality the state machine is sometimes confused so that
169 * the whole stream is shifted by one byte. The watchdog below disables the TX
170 * FIFO, fills the buffer with zeroes and re-enables the FIFO. State machine
171 * is being reset and by filling the buffer we get some time before next
174 static irqreturn_t ep93xx_i2s_interrupt(int irq, void *dev_id)
176 struct ep93xx_i2s_info *info = dev_id;
179 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 0);
181 * Fill TX FIFO with zeroes, this way we can defer next IRQs as much as
182 * possible and get more time for DMA to catch up. Actually there are
183 * only 8 samples in this FIFO, so even on 8kHz maximum deferral here is
186 while (!(ep93xx_i2s_read_reg(info, EP93XX_I2S_GLSTS) &
187 EP93XX_I2S_GLSTS_TX0_FIFO_FULL)) {
188 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0LFT, 0);
189 ep93xx_i2s_write_reg(info, EP93XX_I2S_I2STX0RT, 0);
192 ep93xx_i2s_write_reg(info, EP93XX_I2S_TX0EN, 1);
197 static int ep93xx_i2s_dai_probe(struct snd_soc_dai *dai)
199 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
201 info->dma_params_tx.filter_data =
202 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_PLAYBACK];
203 info->dma_params_rx.filter_data =
204 &ep93xx_i2s_dma_data[SNDRV_PCM_STREAM_CAPTURE];
206 snd_soc_dai_init_dma_data(dai, &info->dma_params_tx,
207 &info->dma_params_rx);
212 static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
213 struct snd_soc_dai *dai)
215 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
217 ep93xx_i2s_enable(info, substream->stream);
222 static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
223 struct snd_soc_dai *dai)
225 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
227 ep93xx_i2s_disable(info, substream->stream);
230 static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
233 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
234 unsigned int clk_cfg;
235 unsigned int txlin_ctrl = 0;
236 unsigned int rxlin_ctrl = 0;
238 clk_cfg = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
240 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
241 case SND_SOC_DAIFMT_I2S:
242 clk_cfg |= EP93XX_I2S_CLKCFG_REL;
245 case SND_SOC_DAIFMT_LEFT_J:
246 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
249 case SND_SOC_DAIFMT_RIGHT_J:
250 clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
251 rxlin_ctrl |= EP93XX_I2S_RXLINCTRLDATA_R_JUST;
252 txlin_ctrl |= EP93XX_I2S_TXLINCTRLDATA_R_JUST;
259 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
260 case SND_SOC_DAIFMT_BP_FP:
261 /* CPU is provider */
262 clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
265 case SND_SOC_DAIFMT_BC_FC:
266 /* Codec is provider */
267 clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
274 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
275 case SND_SOC_DAIFMT_NB_NF:
276 /* Negative bit clock, lrclk low on left word */
277 clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS);
280 case SND_SOC_DAIFMT_NB_IF:
281 /* Negative bit clock, lrclk low on right word */
282 clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
283 clk_cfg |= EP93XX_I2S_CLKCFG_LRS;
286 case SND_SOC_DAIFMT_IB_NF:
287 /* Positive bit clock, lrclk low on left word */
288 clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
289 clk_cfg &= ~EP93XX_I2S_CLKCFG_LRS;
292 case SND_SOC_DAIFMT_IB_IF:
293 /* Positive bit clock, lrclk low on right word */
294 clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_LRS;
298 /* Write new register values */
299 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
300 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
301 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, rxlin_ctrl);
302 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, txlin_ctrl);
306 static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
307 struct snd_pcm_hw_params *params,
308 struct snd_soc_dai *dai)
310 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(dai);
311 unsigned word_len, div, sdiv, lrdiv;
314 switch (params_format(params)) {
315 case SNDRV_PCM_FORMAT_S16_LE:
316 word_len = EP93XX_I2S_WRDLEN_16;
319 case SNDRV_PCM_FORMAT_S24_LE:
320 word_len = EP93XX_I2S_WRDLEN_24;
323 case SNDRV_PCM_FORMAT_S32_LE:
324 word_len = EP93XX_I2S_WRDLEN_32;
331 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
332 ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
334 ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
337 * EP93xx I2S module can be setup so SCLK / LRCLK value can be
338 * 32, 64, 128. MCLK / SCLK value can be 2 and 4.
339 * We set LRCLK equal to `rate' and minimum SCLK / LRCLK
340 * value is 64, because our sample size is 32 bit * 2 channels.
341 * I2S standard permits us to transmit more bits than
344 div = clk_get_rate(info->mclk) / params_rate(params);
346 if (div > (256 + 512) / 2) {
350 if (div < (128 + 256) / 2)
354 err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
358 err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
365 static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
366 unsigned int freq, int dir)
368 struct ep93xx_i2s_info *info = snd_soc_dai_get_drvdata(cpu_dai);
370 if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
375 return clk_set_rate(info->mclk, freq);
379 static int ep93xx_i2s_suspend(struct snd_soc_component *component)
381 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
383 if (!snd_soc_component_active(component))
386 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
387 ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
392 static int ep93xx_i2s_resume(struct snd_soc_component *component)
394 struct ep93xx_i2s_info *info = snd_soc_component_get_drvdata(component);
396 if (!snd_soc_component_active(component))
399 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
400 ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
405 #define ep93xx_i2s_suspend NULL
406 #define ep93xx_i2s_resume NULL
409 static const struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
410 .startup = ep93xx_i2s_startup,
411 .shutdown = ep93xx_i2s_shutdown,
412 .hw_params = ep93xx_i2s_hw_params,
413 .set_sysclk = ep93xx_i2s_set_sysclk,
414 .set_fmt = ep93xx_i2s_set_dai_fmt,
417 #define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S32_LE)
419 static struct snd_soc_dai_driver ep93xx_i2s_dai = {
421 .probe = ep93xx_i2s_dai_probe,
425 .rates = SNDRV_PCM_RATE_8000_192000,
426 .formats = EP93XX_I2S_FORMATS,
431 .rates = SNDRV_PCM_RATE_8000_192000,
432 .formats = EP93XX_I2S_FORMATS,
434 .ops = &ep93xx_i2s_dai_ops,
437 static const struct snd_soc_component_driver ep93xx_i2s_component = {
438 .name = "ep93xx-i2s",
439 .suspend = ep93xx_i2s_suspend,
440 .resume = ep93xx_i2s_resume,
441 .legacy_dai_naming = 1,
444 static int ep93xx_i2s_probe(struct platform_device *pdev)
446 struct ep93xx_i2s_info *info;
449 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
453 info->regs = devm_platform_ioremap_resource(pdev, 0);
454 if (IS_ERR(info->regs))
455 return PTR_ERR(info->regs);
457 if (IS_ENABLED(CONFIG_SND_EP93XX_SOC_I2S_WATCHDOG)) {
458 int irq = platform_get_irq(pdev, 0);
460 return irq < 0 ? irq : -ENODEV;
462 err = devm_request_irq(&pdev->dev, irq, ep93xx_i2s_interrupt, 0,
468 info->mclk = clk_get(&pdev->dev, "mclk");
469 if (IS_ERR(info->mclk)) {
470 err = PTR_ERR(info->mclk);
474 info->sclk = clk_get(&pdev->dev, "sclk");
475 if (IS_ERR(info->sclk)) {
476 err = PTR_ERR(info->sclk);
480 info->lrclk = clk_get(&pdev->dev, "lrclk");
481 if (IS_ERR(info->lrclk)) {
482 err = PTR_ERR(info->lrclk);
486 dev_set_drvdata(&pdev->dev, info);
488 err = devm_snd_soc_register_component(&pdev->dev, &ep93xx_i2s_component,
493 err = devm_ep93xx_pcm_platform_register(&pdev->dev);
500 clk_put(info->lrclk);
509 static void ep93xx_i2s_remove(struct platform_device *pdev)
511 struct ep93xx_i2s_info *info = dev_get_drvdata(&pdev->dev);
513 clk_put(info->lrclk);
518 static const struct of_device_id ep93xx_i2s_of_ids[] = {
519 { .compatible = "cirrus,ep9301-i2s" },
522 MODULE_DEVICE_TABLE(of, ep93xx_i2s_of_ids);
524 static struct platform_driver ep93xx_i2s_driver = {
525 .probe = ep93xx_i2s_probe,
526 .remove_new = ep93xx_i2s_remove,
528 .name = "ep93xx-i2s",
529 .of_match_table = ep93xx_i2s_of_ids,
533 module_platform_driver(ep93xx_i2s_driver);
535 MODULE_ALIAS("platform:ep93xx-i2s");
536 MODULE_AUTHOR("Ryan Mallon");
537 MODULE_DESCRIPTION("EP93XX I2S driver");
538 MODULE_LICENSE("GPL");